JPH0499040A - Mounting method and mounting substrate of semiconductor element - Google Patents
Mounting method and mounting substrate of semiconductor elementInfo
- Publication number
- JPH0499040A JPH0499040A JP2208583A JP20858390A JPH0499040A JP H0499040 A JPH0499040 A JP H0499040A JP 2208583 A JP2208583 A JP 2208583A JP 20858390 A JP20858390 A JP 20858390A JP H0499040 A JPH0499040 A JP H0499040A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- projected
- conductors
- semiconductor chip
- jig
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000004020 conductor Substances 0.000 claims abstract description 35
- 229920005989 resin Polymers 0.000 claims abstract description 8
- 239000011347 resin Substances 0.000 claims abstract description 8
- 239000000919 ceramic Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000001035 drying Methods 0.000 claims description 3
- 238000005245 sintering Methods 0.000 claims 1
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 2
- 238000007639 printing Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 101150006573 PAN1 gene Proteins 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/06102—Disposition the bonding areas being at different heights
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、コンピューター等の電子機器に搭載する半導
体素子を基板にアセンブリーする半導体素子の実装方法
および実装基板に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor element mounting method and a mounting board for assembling a semiconductor element mounted on an electronic device such as a computer onto a substrate.
従来の技術
近年、半導体製造技術の進展に伴い、ＬＳＩの高集積化
が進み、電子機器の小型・軽量化は一段と進んでいる。BACKGROUND OF THE INVENTION In recent years, as semiconductor manufacturing technology has progressed, LSIs have become more highly integrated, and electronic devices have become smaller and lighter.
これらの軽薄短小化に伴い半導体素子モパッケージから
フィルムキャリアによる半導体チップ実装が用いられる
ようになり、さらには実装密度を上げるため半導体チッ
プを直接実装するようにもなった。As these devices became lighter, thinner, and smaller, semiconductor chip mounting using film carriers began to be used instead of semiconductor element modules, and furthermore, semiconductor chips began to be directly mounted to increase packaging density.
半導体チップを直接実装する時、チップを上に向けて基
板に固定し金線でチップのパッドと基板を結んで後チッ
プを樹脂でモールドする方法とチップ上のパッドに半田
等でバンプを形成しチップを下に向けて基板に実装しそ
の後樹脂でモールドする方法がある。前者の方法では実
装密度が上げられないなどの理由によシ後者すなわち第
３図に示すような方法に変わシつつある。第３図におい
て、１は半導体チップ、２はセラミック等の基板、３は
基板２に設けられた凸状導体、４は半導体チップ１上に
設けられたバンプ、６はコーティング樹脂である。When directly mounting a semiconductor chip, there are two methods: fixing the chip on the board with the chip facing up, connecting the chip pads and the board with gold wire, and then molding the chip with resin, and forming bumps on the pads on the chip with solder etc. There is a method of mounting the chip on a board with the chip facing down and then molding it with resin. Due to the inability to increase packaging density with the former method, the latter method, ie, the method shown in FIG. 3, is being replaced. In FIG. 3, 1 is a semiconductor chip, 2 is a substrate made of ceramic or the like, 3 is a convex conductor provided on the substrate 2, 4 is a bump provided on the semiconductor chip 1, and 6 is a coating resin.
発明が解決しようとする課題
このような従来の半導体素子の実装方法では、セラミッ
ク等の基板２上に印刷法を用いて形成した凸状導体３の
高さは、基板２のそりやうねりによりばらつきがでる。Problems to be Solved by the Invention In such a conventional semiconductor device mounting method, the height of the convex conductor 3 formed using a printing method on a substrate 2 made of ceramic or the like varies due to warpage or waviness of the substrate 2. comes out.
また印刷時の条件ばらつきによっても厚みのばらつきが
生じる。したがって、半導体チップ１との接続に際し−
様な接続が得られず、信頼性の点で問題がある。Also, variations in thickness occur due to variations in conditions during printing. Therefore, when connecting to the semiconductor chip 1, -
It is not possible to obtain a reliable connection, and there is a problem in terms of reliability.
本発明は上記課題を解決するもので、基板のそりやうね
りがあっても接続面の平面性が確保され、信頼性の高い
接続が可能な半導体素子の実装方法および実装基板を提
供することを目的としている。The present invention solves the above-mentioned problems, and aims to provide a mounting method and a mounting board for semiconductor elements, which ensure the flatness of the connection surface even if the board warps or undulates, and enables highly reliable connections. The purpose is
課題を解決するための手段
本発明は上記目的を達成するために、基板上の凸状導体
をパターン形成乾燥後、平滑度の高い面を持った治具に
より押えることにより、凸状導体表面を画一にして平滑
性を高め同時に凸状導体高さのばらつきを小さくしてか
ら、半導体チップとの接続を行うものである。Means for Solving the Problems In order to achieve the above-mentioned object, the present invention, after patterning and drying the convex conductor on a substrate, presses the convex conductor surface with a jig having a highly smooth surface. The convex conductor is made uniform to improve smoothness and at the same time reduce variations in height of the convex conductor, and then connect to the semiconductor chip.
作用
本発明は上記構成により、基板にそりやうねりがあって
も凸状導体と半導体チップとの接続面の平面性が確保さ
れるので、基板上の凸状導体と半導体チップ上のバンプ
との接続が確実にとれる。According to the above structure, the present invention ensures flatness of the connection surface between the convex conductor and the semiconductor chip even if the substrate has warpage or undulation, so that the connection between the convex conductor on the substrate and the bumps on the semiconductor chip is ensured. Connection can be established reliably.
実施例 以下、本発明の実施例について図面を用いて説明する。Example Embodiments of the present invention will be described below with reference to the drawings.
第１図は半導体チップ１１をセラミック等の基板１２に
実装した時の実装体の断面図である。基板１２上に形成
された凸状導体１３は銅ペーストであり、半導体チップ
１１のバンプ１４は半田メツキ法で形成されている。コ
ーティング樹脂１６はエポキシ系の樹脂である。ただし
、凸状導体１３は銅ペースト以外の導体ペーストでもよ
く、またバンプ゛１４においてもメツキによる金パン１
などでもよい。第２図（ム）から（Ｃ）に本実施例の手
順を示す。まず第２図（ム）のように基板１２の上に凸
状導体１３を印刷法で形成する。そして凸状導体１３の
溶剤を抜くため１６０℃で３０分間乾燥を行う。FIG. 1 is a cross-sectional view of a mounted body in which a semiconductor chip 11 is mounted on a substrate 12 made of ceramic or the like. The convex conductor 13 formed on the substrate 12 is made of copper paste, and the bumps 14 of the semiconductor chip 11 are formed by solder plating. The coating resin 16 is an epoxy resin. However, the convex conductor 13 may be made of a conductor paste other than copper paste, and the bump 14 may also be made of gold pan 1 by plating.
etc. FIGS. 2(M) to (C) show the procedure of this embodiment. First, as shown in FIG. 2(m), a convex conductor 13 is formed on a substrate 12 by a printing method. Then, in order to remove the solvent from the convex conductor 13, drying is performed at 160° C. for 30 minutes.
導体１３の幅が半導体チップ１１のパッド上に形成した
バンプ１４に合うように狭いことと、基板１２自体のう
ねりにより凸状導体１３の高さにはばらつきがある。次
に第２図（Ｂ）のようにちょうど半導体チップ１１の面
積よりもやや広く、平滑性ある平面部を有する治具１６
で乾燥した凸状導体１３を軽く押える。凸状導体１３は
まだ硬化あるいは焼結されていないので容易に変形し、
表面が画一になって接続面の平滑性が容易に実現する。The height of the convex conductor 13 varies due to the width of the conductor 13 being narrow to match the bump 14 formed on the pad of the semiconductor chip 11 and the undulation of the substrate 12 itself. Next, as shown in FIG. 2(B), a jig 16 having a flat surface that is slightly wider than the area of the semiconductor chip 11 and has a smooth surface.
Lightly press the dried convex conductor 13 with. Since the convex conductor 13 has not yet been hardened or sintered, it is easily deformed.
The surface becomes uniform and smoothness of the connection surface can be easily achieved.
また接続面が一定の平面上にくるので、凸状基板１２の
うねシを打ち消すことになる。このとき凸状導体１３は
断面が鼓状になる。次に治具１６を離し、９００℃窒素
雰囲気下で凸状導体１３の焼結をおこなう。次に第２図
（Ｃ）のようにバンプ１４をつけた半導体チップ１１を
実装した後リフロー炉を通して固着し、そのおと第１図
のように半導体チップ１１全体を樹脂１６でコーティン
グすると実装は完了する。Furthermore, since the connection surface is on a constant plane, the ridges of the convex substrate 12 are canceled out. At this time, the convex conductor 13 has a drum-shaped cross section. Next, the jig 16 is released, and the convex conductor 13 is sintered at 900° C. in a nitrogen atmosphere. Next, as shown in FIG. 2(C), the semiconductor chip 11 with bumps 14 is mounted and fixed through a reflow oven, and then the entire semiconductor chip 11 is coated with resin 16 as shown in FIG. Complete.
発明の効果
以上の実施例から明らかなように、本発明は基板上にパ
ターン形成された複数個の凸状導体上に平滑性ある平面
部を有する治具をのせて凸状導体の表面を画一にしてか
ら半導体チップを接続するので、基板のそりやうねシが
あっても、接続面の平面性が確保され、信頼性の高い接
続が可能な半導体素子の実装方法および実装基板を提供
できる。Effects of the Invention As is clear from the above embodiments, the present invention involves placing a jig having a smooth flat surface on a plurality of convex conductors patterned on a substrate to define the surface of the convex conductors. Since the semiconductor chips are connected after they are assembled together, even if the board is warped or ridged, the flatness of the connection surface is ensured, making it possible to provide a method for mounting semiconductor elements and a mounting board that allows for highly reliable connections. .
第１図は本発明の一実施例の半導体素子の実装方法によ
シ実装基板に半導体チップを実装した実装体の断面図、
第２図（ム）〜（Ｃ）は第１図の実装体を得るため半導
体素子の実装方法の各手順の断面図、第３図は従来の半
導体素子の実装方法による実装体の断面図である。
１１・・・・・・半導体チップ、１２・・・・・・セラ
ミック等の基板、１３・・・・・・凸状導体、１４・・
・・・・バンプ、１５・・・・・・コーティング樹脂、
１６・・・・・・平滑性ある平面部を有する治具。
ｌｌ・−手港体テッフ。FIG. 1 is a cross-sectional view of a packaged body in which a semiconductor chip is mounted on a mounting board according to a semiconductor device mounting method according to an embodiment of the present invention;
Figures 2 (M) to (C) are cross-sectional views of each step of the semiconductor element mounting method to obtain the mounted body shown in Figure 1, and Figure 3 is a cross-sectional view of the mounted body by the conventional semiconductor element mounting method. be. 11...Semiconductor chip, 12...Substrate such as ceramic, 13...Convex conductor, 14...
...Bump, 15...Coating resin,
16...Jig having a flat surface with smoothness. ll・-hand port body teff.
Claims (2)
ーン形成し乾燥させる工程と、そのパターン形成された
複数個の凸状導体の上に平滑性ある平面部を有する治具
をのせてその複数個の凸状導体の表面を画一になるよう
に変形させる工程と、その表面が画一になった複数個の
凸状導体を設けた基板を熱処理してその凸状導体を焼結
させる工程と、その基板上にバンプを設けた半導体チッ
プを位相を合わせてのせリフロー炉内を通過させて、そ
の半導体チップ上のバンプと、前記基板上の凸状導体を
固着させる工程と、前記半導体チップ上に樹脂をコーテ
ィングさせる工程とを有する半導体素子の実装方法。(1) A process of forming a pattern of a plurality of convex conductors on a substrate such as ceramic and drying it, and placing a jig having a smooth flat surface on top of the patterned convex conductors. A process of deforming the surfaces of the plurality of convex conductors so that they are uniform, and heat treating the substrate on which the plurality of convex conductors with the same surface are provided and sintering the convex conductors. a step of placing a semiconductor chip with bumps on the substrate in phase alignment and passing it through a reflow oven to fix the bumps on the semiconductor chip and the convex conductor on the substrate; A method for mounting a semiconductor element, comprising the step of coating a semiconductor chip with a resin.
体の断面を鼓状にして表面を画一にした実装基板。(2) A mounting board in which a plurality of convex conductors formed on a substrate made of ceramic or the like have a drum-shaped cross section and a uniform surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2208583A JP2881999B2 (en) | 1990-08-06 | 1990-08-06 | Semiconductor element mounting method and mounting substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2208583A JP2881999B2 (en) | 1990-08-06 | 1990-08-06 | Semiconductor element mounting method and mounting substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0499040A true JPH0499040A (en) | 1992-03-31 |
| JP2881999B2 JP2881999B2 (en) | 1999-04-12 |
Family
ID=16558591
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2208583A Expired - Fee Related JP2881999B2 (en) | 1990-08-06 | 1990-08-06 | Semiconductor element mounting method and mounting substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2881999B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6103551A (en) * | 1996-03-06 | 2000-08-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor unit and method for manufacturing the same |
| KR100300758B1 (en) * | 1996-03-06 | 2001-11-02 | 모리시타 요이찌 | Semiconductor device and process for producing the same |
| JP2004000411A (en) * | 2002-04-03 | 2004-01-08 | Canon Inc | Device, method, and system for displaying animation, device, method, and system for processing the same, program, computer-readable storage medium, and method and system for supporting image diagnosis |
| JP2008021902A (en) * | 2006-07-14 | 2008-01-31 | Denso Corp | Semiconductor device, and its manufacturing method |
-
1990
- 1990-08-06 JP JP2208583A patent/JP2881999B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6103551A (en) * | 1996-03-06 | 2000-08-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor unit and method for manufacturing the same |
| KR100300758B1 (en) * | 1996-03-06 | 2001-11-02 | 모리시타 요이찌 | Semiconductor device and process for producing the same |
| US6452280B1 (en) | 1996-03-06 | 2002-09-17 | Matsushita Electric Industrial Co., Ltd. | Flip chip semiconductor apparatus with projecting electrodes and method for producing same |
| JP2004000411A (en) * | 2002-04-03 | 2004-01-08 | Canon Inc | Device, method, and system for displaying animation, device, method, and system for processing the same, program, computer-readable storage medium, and method and system for supporting image diagnosis |
| JP2008021902A (en) * | 2006-07-14 | 2008-01-31 | Denso Corp | Semiconductor device, and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2881999B2 (en) | 1999-04-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4872261A (en) | Method of and apparatus for surface mounting electronic components onto a printed wiring board | |
| US6469393B2 (en) | Semiconductor package and mount board | |
| US4466181A (en) | Method for mounting conjoined devices | |
| US7340829B2 (en) | Method for fabricating electrical connection structure of circuit board | |
| JPH06224334A (en) | Multi-chip module | |
| JPH10233463A (en) | Semiconductor device and its manufacture | |
| US6448106B1 (en) | Modules with pins and methods for making modules with pins | |
| JPH0499040A (en) | Mounting method and mounting substrate of semiconductor element | |
| US6281437B1 (en) | Method of forming an electrical connection between a conductive member having a dual thickness substrate and a conductor and electronic package including said connection | |
| JPH08111578A (en) | Manufacture of board for mounting ball grid array package | |
| US20040003940A1 (en) | Circuit board for flip-chip semiconductor package and fabrication method thereof | |
| JP2000031630A (en) | Connecting structure of semiconductor integrated circuit element to wiring board | |
| JPH08148526A (en) | Semiconductor device | |
| KR0152559B1 (en) | Method for manufacturing solder bump | |
| EP2480058B1 (en) | Multi-layer substrate and manufacture method thereof | |
| EP0949668B1 (en) | Method for forming bump and semiconductor device | |
| JP3598189B2 (en) | Chip size package, its manufacturing method, and its mounting alignment method | |
| JPH03129745A (en) | Mounting of semiconductor device | |
| JP3895020B2 (en) | Method for forming conductive bump | |
| JPS6364916B2 (en) | ||
| JP4599891B2 (en) | Semiconductor device substrate and semiconductor device | |
| US20060141666A1 (en) | Method for producing a module including an integrated circuit on a substrate and an integrated module manufactured thereby | |
| JP2500404B2 (en) | Circuit board mounting structure | |
| JPH1187605A (en) | Semiconductor device and its manufacture | |
| JP2819747B2 (en) | Semiconductor device, its mounting structure, and its mounting method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |