JPH0498872A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0498872A
JPH0498872A JP2216150A JP21615090A JPH0498872A JP H0498872 A JPH0498872 A JP H0498872A JP 2216150 A JP2216150 A JP 2216150A JP 21615090 A JP21615090 A JP 21615090A JP H0498872 A JPH0498872 A JP H0498872A
Authority
JP
Japan
Prior art keywords
transfer gate
capacitor
electrode
semiconductor substrate
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2216150A
Other languages
Japanese (ja)
Inventor
Toshimitsu Kamitaka
神鷹 敏充
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP2216150A priority Critical patent/JPH0498872A/en
Publication of JPH0498872A publication Critical patent/JPH0498872A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable transfer gate transistors provided in a lateral direction to be balanced in threshold voltage or to be protected against an offset phenomenon by a method wherein a capacitor electrode is provided partially overlapping the upper part of a transfer gate electrode. CONSTITUTION:First, an insulating film 10 is selectively formed on the surface of a semiconductor substrate 1 to demarcate an element region, and a gate insulating film 8 is provided onto the element region concerned. Then, transfer gate electrodes 11a and 11b are provided, and the surfaces of the electrodes 11a and 11b are covered with insulating films 12a and 12b respectively. Thereafter, impurity layers 13a, 13b, and 13c whose conductivity types are opposite to that of the semiconductor substrate 1 are provided, grooves 2a and 2b are engraved on the surface of the semiconductor substrate 1, and capacitor insulating films 15a and 15b are formed thereon. Then, capacitor electrodes 14a and 14b are built. Next, interlaminar insulating films 16a and 16b are provided, an opening 18 is bored, and then a wiring metal electrode 17 is formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に半導体基板に溝容量と
、その溝容量と結合するトランスファゲート電極とを有
する半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a trench capacitor in a semiconductor substrate and a transfer gate electrode coupled to the trench capacitor.

〔従来の技術〕[Conventional technology]

従来、容量値−を減少させることなく、パターンの集積
度を向上させる為に、半導体基板に清を刻設し、この溝
の表面全体を容量として用いる半導体装置は、容量とな
る電極を設けた後に、その上にトランスファゲートとな
る電極を設けていた。
Conventionally, in order to improve the degree of integration of patterns without reducing the capacitance value, semiconductor devices have been created in which grooves are carved into the semiconductor substrate and the entire surface of the grooves is used as a capacitor. Later, an electrode that would become a transfer gate was placed on top of it.

第2図は、従来のこの種の半導体装置を示す断面図であ
る。半導体基板1の方面にドライエツチングにより、清
2a、2bを刻設し、この溝2a、2bの表面に容量絶
縁膜3a、3bを形成し、更に、容量電極4を形成する
。しかるのちに、絶縁膜8a、8bを介してトランスフ
ァゲート電極5a、5bを形成し、絶縁膜6を形成した
のちに、配線用電極7を形成する0図中9九〜9eは基
板と反対導電型の拡散層である。このように、溝2a、
2bの表面を利用して容量を形成することから、集積度
を高く維持しつつ、高容量値を得ることができる。
FIG. 2 is a sectional view showing a conventional semiconductor device of this type. Grooves 2a and 2b are etched in the semiconductor substrate 1 by dry etching, capacitor insulating films 3a and 3b are formed on the surfaces of the grooves 2a and 2b, and a capacitor electrode 4 is further formed. Thereafter, transfer gate electrodes 5a and 5b are formed via insulating films 8a and 8b, and after forming an insulating film 6, wiring electrodes 7 are formed. This is a type of diffusion layer. In this way, the groove 2a,
Since the capacitor is formed using the surface of 2b, a high capacitance value can be obtained while maintaining a high degree of integration.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、上述した半導体装!においては、容量電
極の上部にトランスファゲート電極が設けられている為
に次のような問題点が生ずる。
However, the semiconductor device mentioned above! In this case, since the transfer gate electrode is provided above the capacitor electrode, the following problem occurs.

第3図<a>、(b)は、その問題点を示した断面図で
ある。
FIGS. 3A and 3B are cross-sectional views showing the problem.

まず第3図(a)は、容量電極4の端部が左方向にズレ
な場合の図である。この場合、拡散層9bより、容量電
極4が左方向に出ている為に、オフセットが生じ、右側
のトランスファゲート・トランジスタのしきい電圧が左
側トランスファゲート・トランジスタのしきい電圧に比
べて高くなるか、もしくはONLないようになり、回路
動作マージンがせまくなるか、もしくは、正常な動作を
しなくなる。
First, FIG. 3(a) shows a case where the end of the capacitor electrode 4 is shifted to the left. In this case, since the capacitor electrode 4 protrudes to the left from the diffusion layer 9b, an offset occurs, and the threshold voltage of the right transfer gate transistor becomes higher than that of the left transfer gate transistor. Otherwise, the ONL will disappear, and the circuit operation margin will become narrower, or the circuit will not operate normally.

又、第3図<b>は、トランスファゲート電極5a、5
bが右方向ヘズレな場合の図である。この場合は、左右
のトランスファゲート・トランジスタの実効チャンネル
長のアンバランスが生じ、回路動作マージンがせまくな
るが、もしくは正常な動作をしなくなる。
Further, FIG. 3<b> shows transfer gate electrodes 5a, 5
It is a figure when b is shifted rightward. In this case, the effective channel lengths of the left and right transfer gate transistors become unbalanced, and the circuit operation margin becomes narrow or the circuit does not operate normally.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、容量tfiと、トランスファゲ
ートを極の位置関係が従来め半導体装置とは逆で、トラ
ンスファケート電極の上部に容量電極の一部がオーバラ
ップして設けられている。
In the semiconductor device of the present invention, the positional relationship between the capacitor tfi and the transfer gate pole is opposite to that of a conventional semiconductor device, and the capacitor electrode is provided with a portion of the capacitor electrode overlapping the transfer gate electrode.

本発明においては、トランスファゲート電極の上部に容
量電極がオーバラップさせた配置になっているので、前
述の問題点である容量電極か、もしくはトランスアゲー
ト電極のどちらかが目ズレを起こした場合の不具合であ
る左右のトランスファゲート・トランジスタのしきい電
圧のアンバランスや、オフセット現象が生じなくなり、
微細化したパターンについては、特に大きな利点を有す
る事になる。
In the present invention, since the capacitor electrode is arranged to overlap the top of the transfer gate electrode, it is possible to avoid the above-mentioned problem when either the capacitor electrode or the transagate electrode is misaligned. Problems such as imbalance in threshold voltage between left and right transfer gate transistors and offset phenomenon no longer occur.
This has particularly great advantages for finer patterns.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a>及び(b)は、本発明の一実施例を示す平
面図及び断面図である。
FIGS. 1(a) and 1(b) are a plan view and a sectional view showing an embodiment of the present invention.

シリコンなどの半導体基板1の表面に、溝2a、2bを
刻設し、その溝の2a、2bの表面に容量絶縁膜15a
、15bを有し、その表面に容量電極14を有する。又
、半導体基板1と容量電極14の間に絶縁膜12a、1
2bを介してトランスファゲートを極11a、11bを
有し、その上部に、層間絶縁膜16a、16bを介して
配線t[i17が形成されている。
Grooves 2a and 2b are formed on the surface of a semiconductor substrate 1 made of silicon, etc., and a capacitive insulating film 15a is formed on the surface of the grooves 2a and 2b.
, 15b, and has a capacitive electrode 14 on its surface. Further, insulating films 12a, 1 are provided between the semiconductor substrate 1 and the capacitor electrode 14.
The transfer gate has poles 11a and 11b via 2b, and a wiring t[i17 is formed on top of the transfer gate via interlayer insulating films 16a and 16b.

このように構成される半導体装置は、以下の如く製造さ
れる。
The semiconductor device configured as described above is manufactured as follows.

第4図(a)、(b)〜第7図(a>、(b)は、本発
明の一実施例の製造方法を説明するための工程順に配置
した図であり、第4図(a)〜第7図(a>は平面図、
第4図(b)〜第7図(b)は断面図である。
4(a), (b) to FIG. 7(a>, (b) are diagrams arranged in the order of steps for explaining the manufacturing method of one embodiment of the present invention, and FIG. 4(a) ) to Figure 7 (a> is a plan view,
FIG. 4(b) to FIG. 7(b) are cross-sectional views.

猷ず、第4図<a)、(b)に示すように、半導体基板
1の表面に、絶縁膜1oを選択的に形成して素子領域を
区画し、その素子領域上にゲート絶縁膜8を設ける0次
に、第5図(a)、(b)に示すように、トランスファ
ゲート電極11a11bを設け、 次に第6図(a)、(b)に示すように、トランスファ
ゲート電極11a、llbの表面を絶縁!12a、12
bで被う。しかるのちに、半導体基板1と反対電導型の
不純物層L3a、13b13cを設ける。
As shown in FIGS. 4(a) and 4(b), an insulating film 1o is selectively formed on the surface of the semiconductor substrate 1 to define an element region, and a gate insulating film 8 is formed on the element region. Next, as shown in FIGS. 5(a) and (b), transfer gate electrodes 11a and 11b are provided, and then, as shown in FIGS. 6(a) and (b), transfer gate electrodes 11a and 11b are provided. Insulate the surface of llb! 12a, 12
Cover with b. Thereafter, impurity layers L3a and 13b13c of conductivity type opposite to that of the semiconductor substrate 1 are provided.

次に第7図(a)、(b)に示すように、半導体基板1
に表面に漬2a、2bを刻設し、その表面に容量絶縁膜
15a、15bを設ける。しかるのちに容量部電極14
b、14bを設ける。
Next, as shown in FIGS. 7(a) and 7(b), the semiconductor substrate 1
Dip holes 2a and 2b are carved on the surface, and capacitive insulating films 15a and 15b are provided on the surface. After that, the capacitor electrode 14
b, 14b are provided.

次に、第1図<a)、(b)に示すように、層間絶縁膜
16a、16bを設け、開孔部孔18をあけた後、配線
金属電極17を設ける。
Next, as shown in FIGS. 1A and 1B, interlayer insulating films 16a and 16b are provided, and after openings 18 are formed, wiring metal electrodes 17 are provided.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、トランスファゲート電極
の上部に容量triの一部がオーバラップして配置され
ているので、前述の問題点である容量電極かもしくはト
ランスファゲート電極のどちらかが目ズレを起こした場
合の不具合点である左右のトランスファゲートトランジ
スタのしきい電圧のアンバランスや、オフセット現象が
生じなくなり、半導体装置の均一化が可能となる。この
効果は微細化したパターンの半導体装置では、特に大き
な利点を有しているといえよう。
As explained above, in the present invention, a part of the capacitor tri is placed over the transfer gate electrode, so that either the capacitor electrode or the transfer gate electrode is misaligned, which is the problem mentioned above. This eliminates the imbalance of the threshold voltages of the left and right transfer gate transistors and the offset phenomenon, which would otherwise be a problem, and it becomes possible to make the semiconductor device uniform. This effect can be said to have a particularly great advantage in semiconductor devices with finer patterns.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)及び(b)は本発明の一実施例を示す平面
図及び断面図、第2図は、従来の容量部を有する半導体
装置の断面図、第3図(a)及び(b)はいずれも従来
の容量部を有する半導体装置の不具合例を示す断面図、
第4図<a)(b)〜第7図(a)、(b)は、本発明
の半導体装置の製造プロセスを説明するための図であり
、第4図(a)〜第7図(a)は平面図、第4図(b)
〜第7図(b)は断面図である。 1・・・半導体基板、2a、2b・・−溝、3a、3b
・・・容量部絶縁膜、4・・・容量部ゲート電極、5a
。 5b・・・トランスファゲート電極、6・・・層間絶縁
膜、7・・・配線ti、8a、8b・・・トランスファ
ゲート絶縁膜、9a、9b、9c、9d、9e−基板と
反電導型の不純物層、10・・・絶縁膜、11a、ll
b・・・トランスファゲート電極4極、12a。 12 b−・・絶縁膜、13a、13b、  13cm
基板と反電導型の不純物層、14a、14b・・・容量
部電極、15a、15b・・・容量部絶縁膜、16a。 16b・・・層間絶縁膜、17・・・配線電極。
1(a) and (b) are a plan view and a sectional view showing an embodiment of the present invention, FIG. 2 is a sectional view of a conventional semiconductor device having a capacitive part, and FIG. 3(a) and ( b) is a cross-sectional view showing an example of a defect in a conventional semiconductor device having a capacitive part;
FIGS. 4(a) to 7(b) are diagrams for explaining the manufacturing process of the semiconductor device of the present invention, and FIGS. a) is a plan view, Fig. 4(b)
-FIG. 7(b) is a sectional view. 1...Semiconductor substrate, 2a, 2b...-groove, 3a, 3b
... Capacitive part insulating film, 4... Capacitive part gate electrode, 5a
. 5b...Transfer gate electrode, 6...Interlayer insulating film, 7...Wiring ti, 8a, 8b...Transfer gate insulating film, 9a, 9b, 9c, 9d, 9e- anti-conductivity type to substrate Impurity layer, 10...insulating film, 11a, ll
b... Four transfer gate electrodes, 12a. 12 b--Insulating film, 13a, 13b, 13cm
Impurity layer opposite to the substrate, 14a, 14b... Capacitive part electrode, 15a, 15b... Capacitive part insulating film, 16a. 16b... Interlayer insulating film, 17... Wiring electrode.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板に溝容量と、前記溝容量と結合するトランス
ファゲート電極とを有する半導体装置において、前記ト
ランスファゲート電極の上部に前記溝容量の容量電極の
一部がオーバラップして設けられていることを特徴とす
る半導体装置。
In a semiconductor device having a groove capacitor in a semiconductor substrate and a transfer gate electrode coupled to the groove capacitor, a part of the capacitor electrode of the groove capacitor is provided above the transfer gate electrode in an overlapping manner. Characteristic semiconductor devices.
JP2216150A 1990-08-16 1990-08-16 Semiconductor device Pending JPH0498872A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2216150A JPH0498872A (en) 1990-08-16 1990-08-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2216150A JPH0498872A (en) 1990-08-16 1990-08-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0498872A true JPH0498872A (en) 1992-03-31

Family

ID=16684068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2216150A Pending JPH0498872A (en) 1990-08-16 1990-08-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0498872A (en)

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