JPH0497457A - Cache controller - Google Patents

Abstract

PURPOSE:To increase the operating speed of a microcomputer system by outputting an address incremented sequentially from a reference address by receiving a burst request signal from a microprocessor. CONSTITUTION:This controller is equipped with an address control circuit 2 which outputs a burst address signal BAD incremented sequentially setting an address signal AD1 from the microprocessor 20 as reference by receiving a burst address control signal BAC and outputs an address signal AD2 of ordinary mode in accordance with the address signal AD1 from the microprocessor 20 to cache memory 30 by receiving an address control signal AC of ordinary mode. Therefore, continuous memory access in one clock cycle can be performed similarly as a cache controller incorporated in the microprocessor. Thereby, fast memory access is attained, which increases the operating speed of the microcomputer system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache controller, and more particularly to a cache controller provided outside a microprocessor.

[Conventional technology]

Conventionally, this type of cache controller has been used to speed up memory access in microprocessors that do not have a built-in cache controller. It used a burst transfer function for DRAM, such as nibble mode and static column mode, for normal memory access.

On the other hand, some microprocessors have a built-in cache controller, and in order to expand functionality, an external cache controller may be used as a second cache controller.

[Problem to be solved by the invention]

The conventional cache controller described above is configured to perform burst transfer using the normal memory access of the microprocessor, in order to speed up memory access of a microprocessor that does not have a built-in cache controller. Therefore, memory access can only be performed at the minimum number of clocks possible for normal memory access, so it is possible to perform high-speed memory access in which consecutive memory accesses are executed in one clock cycle, such as the burst transfer of a microprocessor with a built-in cache controller. The drawback was that it could only access memory. Also,
When used as a second cache controller for a microprocessor with a built-in cache controller, it has the disadvantage that it cannot perform high-speed memory access like a built-in cache controller, which limits the speedup of the microcomputer system.

SUMMARY OF THE INVENTION An object of the present invention is to provide a cache controller that can perform high-speed memory access like a built-in cache controller and can speed up a microcomputer system.

[Means to solve the problem]

The cache controller of the present invention includes a burst transfer control circuit that receives a burst request signal from a microprocessor and outputs a burst address control signal;
a control circuit that receives a normal mode control signal and outputs a normal mode address control signal; a control circuit that receives the burst address control signal and outputs a burst address signal that is sequentially incremented based on the address signal from the microprocessor; It has an address control circuit which receives a normal mode address control signal and outputs a normal mode address signal corresponding to the address signal from the microprocessor.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This embodiment includes a burst transfer control circuit 1 which receives a burst request signal BRQ from a microprocessor 20 and outputs a burst address control signal BAC and a burst acknowledge signal BAK, and a normal mode control circuit 1 which receives a normal mode control signal CNT and outputs a burst address control signal BAC and a burst acknowledge signal BAK. A control circuit 3 that outputs an address control signal AC, and a burst address control signal BAC.
Address signal A from microprocessor 20 in response to
A burst address signal BAD sequentially incremented based on D is output to the cache memory 30, and upon receiving the normal mode address control signal AC, the normal mode address signal AD2 corresponding to the address signal AD1 from the microprocessor 20 is output to the cache memory. The configuration includes an address control circuit 2 that outputs to 30.

Similar to the cache controller built into a microprocessor, this embodiment enables continuous memory access in one clock cycle, so it can be used with both microprocessors with a built-in cache controller and microprocessors without a built-in cache controller. Processors can also perform high-speed memory access.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

In this embodiment, the cache memory 30A is divided into a plurality of banks to expand the range of data replacement, and the range of data replacement is selectively specified by a plurality of address control circuits 2A to 2D. This has the advantage that it is possible to do so.

Furthermore, the address increment values and address settings of the address control circuits 2A to 2D can be arbitrarily specified.

〔Effect of the invention〕

As explained above, the present invention is configured to receive a burst request signal from a microprocessor and output an address sequentially incremented from a reference address, thereby making it possible to perform continuous memory access in one clock cycle. Therefore, high-speed memory access is possible, which has the effect of speeding up the microcomputer system.

[Brief explanation of drawings]

1 and 2 are block diagrams showing first and second embodiments of the present invention, respectively. 1, IA... burst transfer control circuit, 2, 2A~2
D... address control circuit, 3,3A... control circuit,
10.1OA...cache controller, 20°20A...microprocessor, 30,304...
cache memory.

Claims (1)

[Claims] a burst transfer control circuit that receives a burst request signal from a microprocessor and outputs a burst address control signal; a control circuit that receives a normal mode control signal and outputs a normal mode address control signal; and the burst address control signal. in response to the address signal from the microprocessor, outputting a burst address signal sequentially incremented based on the address signal from the microprocessor, and in response to the normal mode address control signal, outputting a normal mode address signal corresponding to the address signal from the microprocessor. What is claimed is: 1. A cache controller comprising an address control circuit.