JPH0494137A - Field effect transistor - Google Patents

Field effect transistor

Info

Publication number
JPH0494137A
JPH0494137A JP21028090A JP21028090A JPH0494137A JP H0494137 A JPH0494137 A JP H0494137A JP 21028090 A JP21028090 A JP 21028090A JP 21028090 A JP21028090 A JP 21028090A JP H0494137 A JPH0494137 A JP H0494137A
Authority
JP
Japan
Prior art keywords
electrode
gate electrode
source
gate
compound semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21028090A
Other languages
Japanese (ja)
Inventor
Masahiko Yamamoto
雅彦 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eneos Corp
Original Assignee
Nippon Mining Co Ltd
Nikko Kyodo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Mining Co Ltd, Nikko Kyodo Co Ltd filed Critical Nippon Mining Co Ltd
Priority to JP21028090A priority Critical patent/JPH0494137A/en
Publication of JPH0494137A publication Critical patent/JPH0494137A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To take it out without crossing a source electrode by including a gate electrode, which forms a Schottky junction with a compound semiconductor layer and has specified zigzag plane structure with a specified width, and a source electrode and a drain electrode, which are provided severally specified intervals apart from the gate electrode. CONSTITUTION:At the substrate 1 consisting of a semiinsulating GaAs semiconductor is made an active layer, and on the same layer is provided a gate electrode 2, which forms a Schottky junction. The gate electrode 2 is composed of six parallel electrode fingers 2a and five electrode finger 2b, which connect the tips of the electrode fingers 2a alternately. A source electrode 3 and a drain electrode 4 are provided to severally keep specified intervals from the gate electrode 2. The source electrodes 3 and the drain electrodes 4 are alternately provided between the electrode fingers 2a of the gate electrode. Accordingly, the power supply to the gate electrode 2 can be done without crossing the source electrode 3.

Description

【発明の詳細な説明】 (産業−」二の利用分野) 本発明は、電力用電界効果トランジスタの構造、特には
ゲート電極の平面構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Industry - Second Field of Application) The present invention relates to the structure of a power field effect transistor, particularly to the planar structure of a gate electrode.

[従来の技術) G a A sなどの化合物半導体上にショッ!・キー
接合を形成するゲートを設けた電界効果トランジスタ(
以下、FETという)は、マイクロ波帯などの高い周波
数で使用が可能であり、低雑音で電力効率の高い増幅が
可能である。
[Prior art] Shot on compound semiconductors such as GaAs!・A field effect transistor with a gate that forms a key junction (
FETs (hereinafter referred to as FETs) can be used at high frequencies such as microwave bands, and can perform amplification with low noise and high power efficiency.

このようなFE Tの出力電力を増大させるためには、
ゲート幅(すなわち、ソース・ドレイン電、流が流れる
方向に対して垂直な方向のゲート給電部の長さ)を長く
する必要がある。そのため、従来は第2図に示すような
、くし型構造とよばれるゲート電極構造が用いられてい
る。この構造は、所定の不純物を含有する半導体基板l
上において、複数の直線状のゲート電極フィンガー2f
がそれぞれの一端でゲート給電部2gに接続されている
In order to increase the output power of such FET,
The gate width (ie, the length of the gate feed perpendicular to the direction of source-drain current flow) needs to be increased. Therefore, conventionally, a gate electrode structure called a comb structure as shown in FIG. 2 has been used. This structure is based on a semiconductor substrate l containing predetermined impurities.
At the top, a plurality of linear gate electrode fingers 2f
are connected to the gate power supply section 2g at one end of each.

そして、ゲート電極フィンガ−2f間にソース電極3と
ドレイン電極4が交互に設けられている。
Source electrodes 3 and drain electrodes 4 are alternately provided between the gate electrode fingers 2f.

このように、グーl−電極を複数のグーl−電極フィン
ガー2fに分割することで、半導体基板1の寸法を扱い
易い大きさとし、製造過程での破損を防止し、かつ1、
浮遊容量等を低減することでマイクロ波帯での高周波特
性を改善している。
In this way, by dividing the Goo-l-electrode into a plurality of Goo-l-electrode fingers 2f, the dimensions of the semiconductor substrate 1 can be made easy to handle, damage during the manufacturing process can be prevented, and 1.
High frequency characteristics in the microwave band are improved by reducing stray capacitance.

[発明が解決しようとする課題] しかしながら、このようなくし型構造のゲート電極を有
するFETの製造は、複雑な工程が必要である。すなわ
ち、ソース電極3とゲート給電部2gが交差するため、
この部分での2層配線5が必要となる。ゲート・ソース
電極間の電気容量の増大はFETの高周波特性の悪化を
招くため、2層配線5にはエアーブリッジとよばれる空
中配線が用いられる。これにより、FETの製造が複雑
となり、コスト増大の要因となる。
[Problems to be Solved by the Invention] However, manufacturing an FET having such a gate electrode with a comb-shaped structure requires complicated steps. That is, since the source electrode 3 and the gate power supply section 2g intersect,
A two-layer wiring 5 is required in this part. Since an increase in the capacitance between the gate and source electrodes causes deterioration of the high frequency characteristics of the FET, an aerial wiring called an air bridge is used for the two-layer wiring 5. This complicates the manufacture of the FET and causes an increase in cost.

本発明の目的は、このような複雑な工程を必要とせず、
望ましい寸法の半導体基板上に作成することができる電
力用(パワー)FETの構造を提供することにある。
The purpose of the present invention is to eliminate the need for such complicated steps,
The object of the present invention is to provide a power FET structure that can be fabricated on a semiconductor substrate of desired dimensions.

【課題を解決するための手段および作用1本発明による
電界効果トランジスタは、化合物半導体層、該化合物半
導体層とショットキー接合を形成し、所定幅のジグザグ
状または蛇行した曲線状の平面構造を有するゲート電極
、および、該ゲート電極とそれぞれ所定間隔をおいて設
けられ、前記化合物半導体層とオーミック接合を形成す
るドレイン電極およびソース電極とを含むことを特徴と
したものである。
[Means and effects for solving the problems 1] A field effect transistor according to the present invention has a compound semiconductor layer, a Schottky junction formed with the compound semiconductor layer, and a zigzag or meandering curved planar structure with a predetermined width. The device is characterized in that it includes a gate electrode, and a drain electrode and a source electrode that are respectively provided at a predetermined interval from the gate electrode and form an ohmic contact with the compound semiconductor layer.

本発明によれば、ゲートを繍は、ゲート電極への給電部
を除いて枝分かれのないジグザグ状または蛇行した曲線
状であるので、ソース電極(または、ドレイン電極)を
横切ることなく取り出すことができる。
According to the present invention, since the gate electrode has a zigzag shape or a meandering curve shape with no branches except for the power supply part to the gate electrode, it can be taken out without crossing the source electrode (or drain electrode). .

(実施例] 以下、本発明を実施例により詳細に説明する。(Example] Hereinafter, the present invention will be explained in detail with reference to Examples.

一実施例であるG a A s F E Tの主要部の
平面図を第1図に示す。
FIG. 1 shows a plan view of the main parts of the GaAsFET, which is one embodiment.

半絶縁性のGaAs半導体からなる基板1には、エピタ
キシャル成長法等の公知の方法により能動層が形成され
ている。この能動層上にはショットキー接合を形成する
幅1μmのゲート電極2(ゲート長:1μm)が設けら
れている。ゲート電極2は、6本の平行な長さ150μ
mの電極フィンガー28とその電極フィンガー2aの端
部を交互に接続する5本の長さ100μmの電極フィン
ガ=2bから構成され、ゲート幅は1400μmである
An active layer is formed on a substrate 1 made of a semi-insulating GaAs semiconductor by a known method such as epitaxial growth. A gate electrode 2 with a width of 1 μm (gate length: 1 μm) forming a Schottky junction is provided on this active layer. The gate electrode 2 has six parallel lines with a length of 150μ.
It is composed of m electrode fingers 28 and five 100 μm long electrode fingers 2b which alternately connect the ends of the electrode fingers 2a, and the gate width is 1400 μm.

ソース電極3およびドレイン電極4は、ゲート電極2か
らそれぞれ1.5μmおよび2.0μmの間隔を保って
設けられている。ゲート電極の電極フィンガー2aの間
にそれぞれソース電極3およびドレイン電極4が交互に
設けられている。したがって、ゲート電極2への給電は
、ソース電極3を横切ることなく、行うことができる。
The source electrode 3 and the drain electrode 4 are provided at intervals of 1.5 μm and 2.0 μm from the gate electrode 2, respectively. Source electrodes 3 and drain electrodes 4 are alternately provided between the electrode fingers 2a of the gate electrodes. Therefore, power can be supplied to the gate electrode 2 without crossing the source electrode 3.

他の実施例として、ゲート電極2を蛇行した曲線状とす
ることができる。このような曲線としては、基板l上に
直行するX−Y座標を想定した場合、Y=As i n
 (B −X)の三角関数で表される(A、Bは定数)
形状を用いることができる。
As another embodiment, the gate electrode 2 can have a meandering curved shape. Assuming an X-Y coordinate perpendicular to the substrate l, such a curve is Y=As i n
Represented by the trigonometric function of (B - X) (A and B are constants)
Shapes can be used.

直線状の電極フィンガーを接続した形状のゲート電極を
用いた場合、直交する電極フィンガーの接続部分では、
ゲート電極とソース電極およびドレイン電極との距離が
他のゲート電極部分に比べて不均一となる。しかし、ゲ
ート電極2を蛇行した曲線状とすることによりこのよう
な距離の不均一を防ぐことができ、形成されたゲート電
極2のすべての部分を有効に利用でき、FETの性能を
向上することができる。
When using a gate electrode with a shape in which straight electrode fingers are connected, at the connection part of orthogonal electrode fingers,
The distances between the gate electrode and the source and drain electrodes are non-uniform compared to other gate electrode portions. However, by forming the gate electrode 2 in a meandering curved shape, such unevenness in distance can be prevented, and all parts of the formed gate electrode 2 can be used effectively, improving the performance of the FET. I can do it.

(発明の効果1 以上説明したように、本発明による電界効果トランジス
タは、化合物半導体層、該化合物半導体層とショットキ
ー接合を形成し、所定幅のジグザグ状または蛇行した曲
線状の平面構造を有するゲート電極、および、該ゲート
電極とそれぞれ所定間隔をおいて設けられ、前記化合物
半導体層とオーミック接合を形成するドレイン電極およ
びソース電極とを含むことを特徴としたものである。
(Effect of the Invention 1 As explained above, the field effect transistor according to the present invention has a compound semiconductor layer, a Schottky junction with the compound semiconductor layer, and a zigzag or meandering curved planar structure with a predetermined width. The device is characterized in that it includes a gate electrode, and a drain electrode and a source electrode that are respectively provided at a predetermined interval from the gate electrode and form an ohmic contact with the compound semiconductor layer.

本発明によれば、ゲート電極は、ゲート電極への給電部
を除いて枝だ分かれのないジグザグ状または蛇行した曲
線状であるので、ソース電極(または、ドレイン電極)
を横切ることなく取り出すことができる。
According to the present invention, since the gate electrode has a zigzag shape or a meandering curve shape with no branches except for the power supply portion to the gate electrode, the source electrode (or drain electrode)
You can take it out without having to cross it.

このため、2層配線などの複雑な工程を必要とせず、望
ましい寸法の半導体基板上に作成することが可能となる
Therefore, it is possible to fabricate on a semiconductor substrate of desired dimensions without requiring complicated processes such as two-layer wiring.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の詳細な説明するためのFETの平面
図、 第2図は従来技術を説明するためのFETの平面図であ
る。 図において、
FIG. 1 is a plan view of an FET for explaining the present invention in detail, and FIG. 2 is a plan view of an FET for explaining the prior art. In the figure,

Claims (1)

【特許請求の範囲】 化合物半導体層; 該化合物半導体層とショットキー接合を形成し、所定幅
のジグザグ状または蛇行した曲線状の平面構造を有する
ゲート電極;および 該ゲート電極とそれぞれ所定間隔をおいて設けられ、前
記化合物半導体層とオーミック接合を形成するドレイン
電極およびソース電極; とを含むことを特徴とした電界効果トランジタ。
[Scope of Claims] A compound semiconductor layer; a gate electrode forming a Schottky junction with the compound semiconductor layer and having a zigzag or meandering curved planar structure with a predetermined width; and a gate electrode separated from the gate electrode by a predetermined distance, respectively. A field effect transistor comprising: a drain electrode and a source electrode, which are provided in the compound semiconductor layer and form an ohmic contact with the compound semiconductor layer.
JP21028090A 1990-08-10 1990-08-10 Field effect transistor Pending JPH0494137A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21028090A JPH0494137A (en) 1990-08-10 1990-08-10 Field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21028090A JPH0494137A (en) 1990-08-10 1990-08-10 Field effect transistor

Publications (1)

Publication Number Publication Date
JPH0494137A true JPH0494137A (en) 1992-03-26

Family

ID=16586782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21028090A Pending JPH0494137A (en) 1990-08-10 1990-08-10 Field effect transistor

Country Status (1)

Country Link
JP (1) JPH0494137A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005159157A (en) * 2003-11-27 2005-06-16 Renesas Technology Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005159157A (en) * 2003-11-27 2005-06-16 Renesas Technology Corp Semiconductor device
US7838914B2 (en) 2003-11-27 2010-11-23 Renesas Electronics Corporation Semiconductor device
US8169008B2 (en) 2003-11-27 2012-05-01 Murata Manufacturing Co., Ltd. Semiconductor device

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