JPH0492932A - Emulation microcomputer - Google Patents

Abstract

PURPOSE:To securely evaluate an objective system by loading an emulation memory and a memory mapping control means on the same semiconductor substrate as a processing core unit. CONSTITUTION:The emulation (Em) memory 38 and the map control circuit 36, which are loaded on the same semiconductor substrate as the processing core unit 12 are connected to the unit 12 only by an internal bus 50 as an intra- chip wiring without passing through a wiring whose capacity component and a resistance are as large as an external bus and a cable. Thus, the unit 12 can access the memory 38 without being delayed to memory access in the internal part of a target system 4 operating Em. Even a system whose operation frequency is high can execute Em by using the memory 38 without inserting a wait cycle. Thus, the objective system can securely evaluated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an emulation microcomputer used in an emulator device for evaluating a microcomputer application system.

[Prior art]

In the development of microcomputer application equipment (hereinafter simply referred to as target system), an emulator device for system debugging and system evaluation is connected to the target system and is used to control the microcomputer included in the target system (target microcomputer). While it performs functions on behalf of others, it also functions as a debugger.

FIG. 8 shows a general configuration of an emulator device, and the host system 1 is an engineering workstation or a personal computer, and is used to input emulation commands and display emulation results.

The emulator body 2 connected to the host system 1 is
It performs acquisition of emulation information, break control, and interface control with the host system 1 and emulator box 3. The emulator box 3 is equipped with an evaluation chip having functions and performance equivalent to those of the microcomputer of the target system 4, and this evaluation chip executes an operation program of the target system (hereinafter also simply referred to as a target program). The emulator box 3 is connected to the target system 4 by a target system side interface cable 5, and in particular, the tip end of the cable 5 is attached to the microcomputer mounting socket 7 of the target system 4.

When performing software debugging or hardware debugging of the target system 4 using this emulator device, information for tracing the execution state of the target program by the evaluation chip is stored in the trace memory in units of pass cycles, for example. The information stored therein can be displayed on the display of the host system 1 using a trace information display command. Conventionally, this trace information is stored in a trace memory prepared in the emulator main body 2 connected from the emulator box 3 through an interface cable 8 on the emulator system side.

In addition, in order to stop the execution of the target program after the emulation operation has started, the address, data, and state of various control signals, that is, the break conditions at which you want to stop the emulation operation, are set in the break memory in advance. A state comparison circuit monitors whether or not the same state as the set state of the break memory occurs during operation, and when a match occurs, an interrupt is generated to stop execution of the user program by the evaluation chip. These emulation memories and status comparison circuits are also arranged in the emulator body, as is the trace memory.

Furthermore, in case the target system's hardware is not completed and there is not enough memory when performing evaluation using an emulator device, emulation memory that can be lent to the target system may be prepared. Conventionally, this engineering memory was also located on the emulator main body side.

An example of a document describing an emulator is "Hitachi Microcomputer System HMC86800".
ASE User's Manual (published by Hitachi, Ltd. in March 1978).

Regarding an emulator integrated into an integrated circuit, there is US Patent Application No. 723739 (corresponding Japanese Patent Application No. 61-241841) filed by Intel Corporation on April 16, 1985.

[Problem to be solved by the invention]

However, in the conventional configuration, the circuits for trace, break, and memory lending are configured in a semiconductor integrated circuit separate from the evaluation chip, and cables and printed circuit board wiring are interposed between them. Signal propagation delays occur due to the wiring capacitance and resistance components before the various input/output information is received by the trace memory and condition comparison circuit. For example, assuming a microcomputer operating at 50 MHz that executes one instruction in one bus cycle, the time for one bus cycle is 20 nsec. However, due to signal delays caused by cables and printed wiring patterns, and delay time required for bus drive control, various information input and output by the evaluation chip cannot be written to the trace memory in bus cycle units. It becomes impossible to stop the execution of the target program. Furthermore, access to the loaned memory is undesirably delayed, making it impossible to guarantee memory access at normal timing.

Furthermore, if the trace, break, and memory lending circuits are constructed from a semiconductor integrated circuit separate from the evaluation chip, the emulator device becomes larger accordingly.

An object of the present invention is to provide an emulation microcomputer that can perform information tracing and breakpoint control for evaluation even in a microcomputer-based system with high operating speed.

Another object of the present invention is to provide an emulation microcomputer that can guarantee the reliability of memory operations lent to a system to be evaluated, even when evaluating a system using a microcomputer with a high operating speed. It is about providing.

Still another object of the present invention is to provide an emulation microcomputer that can contribute to miniaturization of emulator devices.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a microcomputer equivalent to the microcomputer of the evaluation target system is used as a processing core unit for proxy control, and on the same semiconductor substrate on which this is formed, there is an emulation memory that can be lent to the evaluation target system, and the emulation memory is attached to the evaluation target system. A control means is provided for programmably mapping the side space and making it usable.

Further, the semiconductor substrate can be equipped with means for tracing the control state by the processing core unit and breakpoint control means.

In order to make the processing core unit included in the single-chip emulation microcomputer usable for both control operations from the emulator system side and proxy control for the evaluation target system, an interface means with the evaluation target system, an emulator It is preferable to include means for interfacing with the system, and means for exclusively switching and controlling predetermined signal input/output functions of both of the interface means.

If the processing core unit supports system evaluation by executing a control program on the emulator system side in addition to the operating program for the evaluation target system, the processing core unit may execute the predetermined signal input in response to the occurrence of a break interrupt. If the breakpoint control means generates a control signal for controlling the switching of the output function from the evaluation target system interface circuit side to the emulator system interface circuit side, switching of the operating space of the processing core unit becomes easy.

In order to notify the emulator system of this operating space switching state, the breakpoint control circuit transfers a predetermined signal input/output function from the evaluation target system interface circuit side to the emulator system interface circuit side in response to the occurrence of a break interrupt. It is sufficient to generate a signal to notify the outside that switching is to be performed.

[For production]

According to the above-mentioned means, the emulation memory and memory mapping control means mounted on the same semiconductor substrate as the processing core unit are routed through wiring with relatively large undesired capacitance components and resistances, such as external buses and cables. It is connected to the processing core unit only without internal wiring on the chip.

As a result, the processing core unit can access the emulation memory during emulation operation (proxy control operation) without any delay compared to memory access inside the evaluation target system, and even during high-speed operation, wait cycles are specially inserted. This enables the use of emulation memory without having to do so.

The trace means and breakpoint control means, which are connected to the processing core unit only through internal wiring without going through external wiring, provide the information necessary to perform trace and breakpoint control.

In other words, information corresponding to the emulation operation control status by the processing core unit can be reliably captured within each bus cycle without delay, making it possible to evaluate even high-speed microcomputer-based systems. Achieve information tracing and breakpoint control.

〔Example〕

FIG. 1 shows an emulation microcomputer according to an embodiment of the present invention. The emulation microcomputer 10 shown in the figure includes a processing core unit 12 including a CPU (central processing unit), a target system interface circuit 14, an emulator system interface circuit 16, a trace circuit 20 . It includes a break register 30, a comparison circuit 31, a break control circuit 32, an operation switching circuit 34, a map control circuit 36, and an emulation memory 38, which are fabricated on one semiconductor substrate such as silicon by an appropriate semiconductor integrated circuit manufacturing technology. It is formed from one chip.

This one-chip emulation microcomputer 10 is actually used after being packaged in an appropriate structure. For example, if a pin grid array type package as shown in FIG. 2 is adopted,
A one-chip emulation microcomputer 10 is mounted on a ceramic base 40 and sealed with a metal cap 42 from above. A large number of external lead terminals GP connected to external connection electrodes such as electrode pads of the chip 10 are protruded from the bottom side of the ceramic base 40, and are designated by reference numeral 4.
A part of the external lead terminal GP group indicated by 3 is assigned as a terminal on the target system interface circuit 14 side, and a part of the external lead terminal GP group indicated by 44 is assigned as a terminal on the emulator system interface circuit 16 side.

The external lead terminal GP group 43 assigned as the target system interface circuit 14 side terminal is connected to the target system side interface cable 5 as shown in FIG.
An external lead terminal group 44 connected to the target system 4 via the emulator system interface 16 and assigned as a terminal on the emulator system interface 16 is connected to the emulator main body 2 or the like via an interface cable 8 on the emulator system side. The emulator system indicated by 18 in FIG. 1 is a general term for the circuit portions of the emulator box 3 excluding the emulation microcomputer 10, the emulator main body 2, and the like.

The processing core unit has functions and performance equivalent to those of a microcomputer that originally controls the target system, and is capable of at least fetching instructions, decoding the fetched instructions, performing calculations according to the decoded results, and controlling functions therefor. In addition to the CPU, the microcomputer also includes peripheral circuits corresponding to the target microcomputer. For example, the CPU includes a program counter, an instruction register, an instruction decoder, a sequence control circuit, an arithmetic unit, a general-purpose register, an address register, a stack register, and the like.

The processing core unit 12 is connected to a target system interface circuit 14, an emulator system interface circuit 16, a trace circuit 20, a break register 30, a comparison circuit 31, a map control circuit 36, and an emulation memory 38 via one or more internal buses 50. It is connected.

The operation switching circuit 34 exclusively controls the connection between the internal bus 50 and the target system 4 and the connection between the internal bus 50 and the emulator system 16. That is, the external input/output functions for predetermined signals such as data, addresses, and control signals assigned to the internal bus 50 are exclusively provided to the target system interface circuit 1.
4 or the emulator system interface circuit 16. Note that there is also a signal terminal on the emulator system interface circuit 16 side that is always interfaced with the emulator system side. This signal terminal is a terminal for emulation-specific control signals.

When the processing core unit 12 executes a target program for the target system to perform emulation, the processing core unit 12 controls the target system 4 via the target system interface circuit 14 . On the other hand, when the processing core unit 12 fetches the control program on the emulator system side, executes its instructions to set break conditions, controls the emulation memory map, or transfers information stored in the trace circuit 20. is connected to the processing core unit 1 via the emulator system interface circuit 16.
2 and the emulator system 16.

This exclusive connection control is performed by one, for example, a space switching signal φAS.
When C is set to high level, the operation switching circuit 34 activates the control signal φETS I, and the target system interface circuit 14 receiving this activates the internal bus 50 to the target system 4. Further, when the space switching signal φASC is set to low level, the operation switching circuit 34
activates the control signal φEESI, and in response, the emulator system interface circuit 16 connects the internal bus 50 to the emulator system 18.

The interface circuits 14 and 16, which are subject to such exclusive selection control, are provided with a tri-state buffer 6o that can take a three-value output state on each signal line, as shown in FIG. Control signal φETSI
, given φEESI.

It is only necessary to adopt a high output impedance state when the signal is at a disable level.

The trace circuit 20, as shown in FIG. 5, for example, includes a trace memory 21 constituted by a rewritable RAM (random access memory), an address counter 22, an address multiplexer 23, a data multiplexer 24, and a selector 25. including.

The address counter 22 sequentially updates and outputs the memory address of the trace memory 21 every bus cycle, and the output address is used as the write address of the trace information.

One address update operation is performed in synchronization with a change in the assertion of a strobe signal, such as an address strobe signal AS, which is asserted (activated) in synchronization with a bus cycle. The read address of the trace information written in the trace memory 21 is the output address of the processing core unit 12 operated by the control program at that time. The address multiplexer 23 selects the write address and read address and applies them to the address input terminal A O = A n of the trace memory 21 .

Information to be traced to the trace memory 21 includes data, addresses, control signals, etc. appearing on the internal bus 50 during emulation operation. The output address of the processing core unit 12 is given to the trace information write path 26 during emulation, and data exchanged between the processing core unit 12 and the target system 14 is given via the selector 25. The trace information readout path 27 is the selector 25
Data signal line group 50D included in internal bus 50 via
connected to. The data multiplexer 24 selectively controls the connection of the trace information write path 26 and read path 27 to the data input/output terminals DO to Dn of the trace memory 21.

Selection control of the selector 25, data multiplexer 24 and address multiplexer 23, and operation of the address counter 22 are controlled by the space switching control signal φASC.
controlled by Processing core unit 12
The trace memory 21 is made writable in a state where the basic operating space is selected on the target system 14 side.

In other words, the address counter 22 is enabled to operate, the address multiplexer 23 is enabled to supply the output address of the address counter 22 as a write address to the trace memory 21, and the data multiplexer 24 connects the write path 26 to the trace memory 21. Connect to. As a result, bus information and the like obtained when the target program is executed are sequentially stored in the trace memory 21.

When the basic operating space of the processing core unit 12 is selected by the emulation system 18, the trace memory 21 is made readable. That is, the address counter 22 is not operated, the address multiplexer 23 enables the address output by the processing core unit 12 to be supplied to the trace memory 21, and the data multiplexer 24 connects the read path 27 to the trace memory 21. As a result, the processing core unit 12 executes the control program on the emulator system side, and the trace information held in the trace memory 21 is provided to the emulator system 18 side.

FIG. 6 shows the break register 30 and the comparison circuit 3.
An example of No. 1 is shown below. The figure typically shows three registers 30A, 30B, and 30C.

Data input terminals of each of the registers 30A to 30C are coupled to a data signal line group 50D included in the internal bus 5o, and address input terminals are commonly connected to an address signal line group 50A included in the internal bus 50.

Break conditions given from the emulator system 18 are set in these registers 30A-30C. The comparison circuit 31 inputs the information exchanged by the processing core unit 12 with the target system 4 during emulation operation, compares it with the set values of the registers 30A to 30C, and when a match is detected, generates a break interrupt signal BREA.
Activate K. Note that the comparison circuit 31 is supplied with a space switching control signal φASC, which enables the comparison operation only when the target system 4 is connected to the internal bus, that is, when emulation is possible.

The break control circuit 32 is supplied with a break interrupt signal BREAK output from the comparison circuit 31. When the processing core unit 12 detects that the break interrupt signal BREAK is activated at the interrupt sampling timing, it accepts the break interrupt and first stops execution of the target program.

When processing core unit 12 accepts a break interrupt, it provides information indicating that the interrupt has been accepted to break control circuit 32. As a result, the break control circuit 32 inverts the space switching signal φASC to a low level and connects the processing core unit 12 to the emulator system 18 via the emulator system interface circuit 16. The space switching control signal φASC is the emulator system interface 1.
6, the pre-acknowledge signal BRKA
The pre-acknowledge signal BRKACK is applied to the emulator system 18 as CK, and is activated in response to the low level inversion of the signal φASC, whereby the emulator system 18 switches the operating space of the processing core unit 12 to the emulator system 18 side. Recognize what happened.

When this state is achieved, the processing core unit 12 saves (stacks) the state before the break occurs, performs vectoring, and branches to processing according to the control program on the emulator system 18 side. In this embodiment, the vector interrupt is set as a dedicated interrupt, and uses the vector address set in the processing core unit 12 itself after switching the operating space.

Furthermore, the emulator system 18 has a function of outputting a signal ○BREAK that directly instructs a break.

The break control circuit 32 performs the same processing on the signal 0BREAK as it does on the break interrupt signal BREAK.

The emulation memory 38 is a rewritable RA that can be lent to the target system 4 during emulation operations by the processing core unit 12.
M, and is used as a temporary storage area for data and a storage area for user programs. Map control circuit 3
6 is capable of programmably mapping the emulation memory 38 in the memory space managed by the processing core unit 12, and switches and controls memory access of the mapped address from the target system 4 side to the emulation memory 38. This map control circuit 36 is capable of managing memory space, for example, in units of several kilobytes, although this is not particularly limited. Therefore, the address area to be mapped to the emulation memory 38 can be set in units of management, and this setting operation is performed by the processing core unit 12 according to the control program.

FIG. 7 shows the operation flow of the processing core unit 12.

When the emulator system is started, in its initialization state, the processing core unit 12 is connected to the emulator system 18 via the emulator system interface circuit 16, and is brought into a state equivalent to a break state. In this state, the processing core unit 12 receives a command to start emulation from the emulator system 18, and performs the corresponding processing. For example, setting a break condition for the break register 3o, setting a lending address for the map control circuit 36, or setting an execution start address of the target program. Note that the execution start address of the target program can be set in the stack area where the value of the program counter is saved at the time of a break.

When a command to start a target program is given from the emulator system 18 side, the processing core unit 12 executes, for example, an RFB (return from break) command to start the user program. Although not particularly limited, the RFB instruction includes processing for restoring or setting initial setting information such as the execution start address of the target program, and information saved in the stack area due to the occurrence of a previous break.

When the processing core unit 12 executes the user program in this way, the trace circuit 20 sequentially stores various information exchanged between the target system 4 and the processing core unit 12 in the trace memory 21 in pass cycles. Trace circuit 20
and the processing core unit 12 are connected by an internal bus 50, which is internal wiring of the emulation microcomputer 1o. Therefore, the signal transmission delay via the internal bus 50 is practically negligible, and even if the bus cycle is relatively short in response to the high-speed operation of the processing core unit 12, information tracing in bus cycle units is ensured. This can be done in real time or in real time.

Also, during execution of the target program, the map control circuit 36 transfers the address signal output from the processing core unit 50 to the internal bus 50 as intra-chip wiring.
While importing data via the target system 4, the initially set lending address of the emulation memory 38 is monitored, and when the lending address is detected, the access target is switched from the memory of the target system 4 to the emulation memory 38. Since the transmission delay of the address signal taken in via the internal bus 50 for monitoring the lending address is so small as to be virtually negligible, the bus cycle is relatively short in accordance with the high-speed operation of the processing core unit 12. It is also possible to switch between the memory in the target system 4 and the emulation memory 38 without inserting a special wait cycle, and it is possible to perform emulation in real time using loaned memory for a target system that operates at high speed. It can be carried out.

Also, during execution of the target program, the comparison circuit 31 connects the target system 4 and the processing core unit 1.
The various information exchanged by the CPU 2 is fetched via an internal bus 50 as wiring within the chip, and compared with the break conditions of the break register 30. Even in this comparison operation, the transmission delay of the signal taken in via the internal bus 50 is so small that it can be ignored, so even if the bus cycle is relatively short in response to the high-speed operation of the processing core unit 12, Conditions can be compared without causing undesired timing shifts in data, addresses, and various control signals such as strobe signals that are compared for break conditions, and the establishment of break conditions can be immediately reflected in the execution state of the target program. can be detected reliably and in real time.

When the comparison circuit 31 detects a match with the break condition and activates the break interrupt signal BREAK, the processing core unit 12 accepts the break interrupt at a predetermined timing, thereby stopping execution of the target program. In response to this, the break control circuit 32
inverts the space switching signal φASC and controls the connection of the processing core unit 12 to the emulator system interface circuit 16. This state is notified to the emulator system 18 by the pre-acknowledge signal BRKACK which is activated in response to the level inversion of the space switching signal φASC.

In this way, emulation microcomputer 10
has a break-specific interrupt function that can be positioned as an internal interrupt, so by positioning the break interrupt as an interrupt with the highest priority or an interrupt level such as a non-maskable interrupt, external interrupts from the target system side can be ignored. It is possible to reliably avoid break mistakes due to conflicts with Conventionally, when the breakpoint control circuit is located outside the microcomputer chip, the microcomputer's general external interrupt function is used to initiate a break. In addition, depending on the content of the target program to be emulated, there is a possibility that conflict avoidance may not be possible.

When a break occurs, the processing core unit 12 changes to the processing core unit 1 before the break occurs.
After stacking the state of 2, vectoring is performed, and then data transfer for displaying the saved stack information is performed according to the control program on the emulator system 18 side. This display of stack information is used to check which of multiple break conditions was met to cause a break. If a command for performing evaluation using the engineering results is accepted, it is executed, and, for example, data transfer is performed to display trace information accumulated up to the break. If emulation is to be continued, new break conditions are set if necessary, the target program is started, and emulation is restarted.

According to the above embodiment, the following effects can be obtained.

(1) The emulation memory 38 and map control circuit 36, which are mounted on the same semiconductor substrate as the processing core unit 12, are installed on the chip without going through wiring with relatively large undesired capacitance and resistance, such as an external bus or cable. The processing core unit 12 is connected to the processing core unit 12 only by the internal bus 50 as an internal wiring, so that the processing core unit 12 can access the emulation memory 38 during emulation operation without any delay compared to memory access inside the target system 4.
Even in systems with relatively high operating frequencies, emulation can be performed using the emulation memory 38 without inserting special wait cycles.

(2) The trace circuit 20, the break register 30, and the comparison circuit 31 for determining break conditions are connected to the processing core unit 12 only by internal wiring without going through external wiring.

Information necessary for trace and breakpoint control, that is, various information indicating the execution status of the target program by the processing core unit 12, can be reliably captured within each bus cycle without delay.
This makes it possible to reliably perform information tracing and breakpoint control for evaluation even in systems using microcomputers that operate at high speeds.

(3) An operation switching circuit 34 that exclusively switches and controls the connection state between the target system interface circuit 14, the emulator system interface circuit 16, and the internal bus 50 connection circuit portion of both interface circuits 14.16 and the processing core unit 12. By incorporating a processing core unit 12 included in a single-chip emulation microcomputer, it is possible to use the processing core unit 12 for both control operations from the emulator system 18 side and proxy control for the target system 4.

(4) When the processing core unit 12 executes a control program on the emulator system 18 side in addition to the operating program for the target system 4 to support system evaluation, the break control circuit 32 generates a break interrupt. The operation space of the processing core unit 12 can be changed by generating a control signal φASC for switching the operation switching circuit 34 from the target system interface circuit 14 side to the emulator system interface circuit 16 side in response to the occurrence of Switching can be done easily.

(5) The control signal φ
By forming it based on the ASC, the switching state can be easily notified to the emulator system 18.

(6) Since the trace, breakpoint control, and memory lending functions are built into the one-chip microcomputer 10, there is no need to add circuits for these on the emulator system side, thereby reducing the size of the emulator device. can be achieved.

Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof. .

For example, the connection of the trace means, breakpoint control means, and map control means to the processing core unit is not limited to the common connection mode using the internal bus as in the above embodiment, but it is possible to connect each circuit unit to the target system interface circuit and the emulator system interface. A bus that is individually connected to a circuit may be connected to a bus of a processing core unit via a selector. The bus of the processing core unit is also connected to the target system interface circuit and the emulator system interface circuit via the selector. At this time, the operation switching circuit controls the selector and connects the target system interface circuit and the emulator system interface circuit. In principle, the circuit does not need to have tristate gates for all signal lines.

Further, it is also possible to avoid using the processing core unit for controlling trace means, breakpoint control means, etc. from the emulator side. In that case, a control microcomputer placed on the emulator system side will directly access the internals of the emulation microcomputer.

Furthermore, built-in circuits such as memory and peripheral controllers can be added to the emulation microcomputer depending on the type of microcomputer it is to replace. Furthermore, a general function as an interrupt control circuit may be added to the break control circuit 32 of the above embodiment, so that it can also process external interrupt signals.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, (1) By mounting emulation memory and memory mapping control means on the same semiconductor substrate as the processing core unit, emulation memory can be used without special insertion of wait cycles even in systems with relatively high operating frequencies. This has the effect of making it possible to reliably evaluate the target system.

(2) By installing trace and breakpoint control means on the same semiconductor substrate as the processing core unit, information tracing and breakpoint control are ensured for evaluation even in high-speed microcomputer-based systems. The effect is that it can be done.

(3) By incorporating operation switching means that exclusively switches and controls predetermined signal input/output functions between the target system side and the emulator system side, the processing core unit included in the emulation microcomputer integrated into one chip can be It can be used for both control operations from the emulator system side and proxy control for the target system.

(4) If the processing core unit supports system evaluation by running a control program on the emulator system side in addition to the operation program for the target system, stopping the execution of the target program by controlling breakpoints In conjunction,
By incorporating a function to generate a control signal for switching and controlling a predetermined signal input/output function to the emulator system side, it is possible to easily switch the operating space of the processing core unit.

(5) By having a function to form a signal to notify the emulator system of the state in which a predetermined signal input/output function has been switched to the emulator system based on the control signal for the switch, and output it to the outside. The switching state can be easily notified to the emulator system, and the emulator system can start necessary processing or immediately respond to the operation of the emulation microcomputer in accordance with this notification.

(6) By incorporating one or more functions selected from trace, breakpoint control, and memory lending functions into a single-chip microcomputer, there is no need to add circuits for these functions on the emulator system side. This makes it possible to downsize the emulator device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an emulation microcomputer according to an embodiment of the present invention, FIG. 2 is a perspective view showing a packaged emulation microcomputer chip, and FIG. 3 is a bottom view of the packaged emulation microcomputer chip. figure. FIG. 4 is a logic circuit diagram of a partial example of an emulation system interface circuit and a target system interface circuit, FIG. 5 is a block diagram of an example of a trace circuit, FIG. 6 is a block diagram of an example of a break register and a comparator, and FIG. The figure is an example operation flowchart of the operation of the processing core unit included in the emulation microcomputer, and FIG. 8 is an overall configuration diagram of an example of the emulator device. 2... Emulator body, 3... Emulator box, 4... Target system, 10... Emulation microcomputer, 12... Processing core unit, 14... Target system interface circuit, 16... emulator system interface circuit, 18... emulator system,
20...Trace circuit, 21...Trace memory,
23.24... Multiplexer, 25... Selector, 30... Break register, 31... Comparator,
32... Break control circuit, 34... Operation switching circuit, 36... Map control circuit, 38... Emulation memory, 50... Internal bus, BREA
K...Break interrupt signal, BRKACK...Break acknowledge signal. Figure 1 Figure 2 Figure 3 Figure Figure Figure Figure 0C

Claims (1)

[Scope of Claims] 1. An emulation microcomputer including a processing core unit connected to an evaluation target system and an emulator system, and capable of performing microcomputer control of the evaluation target system according to instructions from the emulator system, comprising: An emulation memory that can be lent to the evaluation target system during delegated control of the system by a core unit, and a programmable mapping of the emulation memory in a memory space managed by the processing core unit, and an address mapped to the emulation memory that can be mapped programmably to the system. An emulation microcomputer comprising: memory mapping control means for switching and controlling memory access from a system to be evaluated to the emulation memory; and a semiconductor integrated circuit. 2. Tracing means including a storage means for holding information generated by proxy control of the evaluation target system by the processing core unit and an information storage control means for the storage means; A comparison means for comparing information generated by the delegated control of the evaluation target system, and a break interrupt generated to stop the delegated control operation of the evaluation target system by the processing core unit based on a match between the comparison results by the comparison means. 2. The emulation microcomputer according to claim 1, further comprising break control means. 3. An evaluation target system interface circuit connected to the evaluation target system; an emulator system interface circuit connected to the emulator system; and a section for connecting the evaluation target system interface circuit and the emulator system interface circuit to the processing core unit. a bus; and switching means for exclusively switching and controlling predetermined signal input/output functions in the evaluation target system interface circuit and the emulator system interface circuit between the evaluation target system interface circuit and the emulator system interface circuit. An emulation microcomputer according to claim 1 or 2, characterized in that: 4. The break control means generates a control signal to the switching means, and the control signal instructs switching of a predetermined signal input/output function from the evaluation target system interface side to the emulator system interface side based on the occurrence of a break interrupt. 4. The emulation microcomputer according to claim 3, wherein the emulation microcomputer is an emulation microcomputer. 5. The break control circuit generates a signal for notifying the outside that a predetermined signal input/output function is to be switched from the evaluation target system interface circuit side to the emulator system interface circuit side based on the occurrence of a break interrupt. 5. The emulation microcomputer according to claim 4, characterized in that: 6. An evaluation target system interface circuit connected to the evaluation target system, an emulator system interface circuit connected to the emulator system, a processing core unit that performs microcomputer control of the evaluation target system, and a processing core unit that is connected to the evaluation target system. an internal bus that connects to the target system interface circuit and the emulator system interface circuit, and a predetermined signal input/output function in the target system interface circuit and the emulator system interface circuit on the evaluation target system interface circuit side and the emulator system interface circuit side. A switching means for exclusive switching control; a tracing means including a storage means for holding information generated by proxy control of the evaluation target system by the processing core unit; and an information storage control means for the storage means; and an emulator system interface circuit. a comparison means for comparing the information given through the processing core unit with information generated by proxy control of the evaluation target system by the processing core unit, and a proxy control operation of the evaluation target system by the processing core unit based on a match between the comparison results by the comparison means. An emulation microcomputer comprising: a break control means for generating a break interrupt for stopping the computer; and a semiconductor integrated circuit. 7. The break control means generates a control signal to the switching means, and the signal instructs switching of a predetermined signal input/output function from the evaluation target system interface circuit side to the emulator system interface circuit side based on the occurrence of a break interrupt. Claim 6 characterized in that
The emulation microcomputer described. 8. The break control circuit generates a signal for notifying the outside that a predetermined signal input/output function is to be switched from the evaluation target system interface circuit side to the emulator system interface circuit side based on the occurrence of a break interrupt. 8. The emulation microcomputer according to claim 7, characterized in that: 9. An emulation memory that can be lent to the evaluation target system during proxy control of the system by the processing core unit; and a programmable mapping of the emulation memory in a memory space managed by the processing core unit; 9. The emulation microcomputer according to claim 8, further comprising: memory mapping control means for switching and controlling memory access of the address from the evaluation target system to the emulation memory. 10, including an external terminal group connected to the evaluation target system and an external terminal group connected to the emulator system,
An emulation microcomputer configured as a semiconductor integrated circuit in which a built-in processing core unit can be interfaced with the outside by exclusively switching predetermined signal input/output functions to both external terminal groups, An emulation microcomputer characterized by comprising an output terminal for a signal indicating whether a predetermined signal can be input/output to/from an external terminal group.