JPH0492461A - Hybrid ic - Google Patents

Hybrid ic

Info

Publication number
JPH0492461A
JPH0492461A JP21116090A JP21116090A JPH0492461A JP H0492461 A JPH0492461 A JP H0492461A JP 21116090 A JP21116090 A JP 21116090A JP 21116090 A JP21116090 A JP 21116090A JP H0492461 A JPH0492461 A JP H0492461A
Authority
JP
Japan
Prior art keywords
cap
semiconductor chip
coating
heat dissipation
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21116090A
Other languages
Japanese (ja)
Inventor
Susumu Sakamoto
進 阪本
Hideaki Katayama
秀昭 片山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP21116090A priority Critical patent/JPH0492461A/en
Publication of JPH0492461A publication Critical patent/JPH0492461A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Abstract

PURPOSE:To reduce possibility of break of bonding wire due to strain of outer power of a cap by extending part of a radiation block on which a semiconductor chip is mounted from a semiconductor chip mounting face to the inside of the cap. CONSTITUTION:A hybrid IC is such that both end parts of a radiation block 10 are provided with the parts (extension parts) raised in the vertical direction, and then the block 10 has a U-shaped section. Even if an external force is applied form a cap 8 to strain the cap 8 to the side of a substrate 1, the force is conducted to the radiation block 10 due to the existing extention part 10a of the radiation block 10 to be received here so as to extremely lessen stress to a coating 7 and in its turn to a bonding wire 6 thus to reduce a fear of break of the bonding wire 6. Further, the coating 7 does not spread in the direction of the extension parts 10a of the radiation block so as to enable electronic parts to be arranged near the radiation block 10.

Description

【発明の詳細な説明】 [産業上の利用分野〕 この発明は混成集積回路に関し、特にその半導体チップ
が取り付けられる放熱ブロックの改良に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit, and particularly to an improvement in a heat dissipation block to which a semiconductor chip thereof is attached.

〔従来の技術〕[Conventional technology]

第3図は従来の混成集積回路の放熱ブロック上に半導体
チップを組み立てた部分の斜視図であり、第4図は第3
図中B−B ’線でのキャップを含んだ断面図を示し、
図において、1はその上面に回路パターンを、下面に接
地パターンを有し、混成集積回路の構成のもととなる基
板、2は基板1の上面の回路パターン、3は基板1の下
面の接地パターン、4は上記回路パターン2上に取付け
られた放熱ブロック、5は放熱ブロック上4に取付けら
れた半導体チップ、6は半導体チップ5と回路パターン
2とを電気的に接続するボンディングワイヤ、7は半導
体チップ5とボンディングワイヤ6を保護するコーティ
ング、8は基板1の回路パターン側の全体を保護するキ
ャップ、9は前記接地パターン3に取付けられた放熱フ
ィンである。
FIG. 3 is a perspective view of a semiconductor chip assembled on a heat dissipation block of a conventional hybrid integrated circuit, and FIG.
A sectional view including the cap taken along line BB' in the figure is shown,
In the figure, 1 has a circuit pattern on its top surface and a ground pattern on its bottom surface, and is the basis of the configuration of the hybrid integrated circuit, 2 is a circuit pattern on the top surface of the substrate 1, and 3 is a ground pattern on the bottom surface of the substrate 1. 4 is a heat dissipation block mounted on the circuit pattern 2, 5 is a semiconductor chip mounted on the heat dissipation block 4, 6 is a bonding wire that electrically connects the semiconductor chip 5 and the circuit pattern 2, and 7 is a A coating protects the semiconductor chip 5 and bonding wires 6, a cap 8 protects the entire circuit pattern side of the substrate 1, and a heat radiation fin 9 attached to the ground pattern 3.

次に動作について説明する。半導体チップ5はボンディ
ングワイヤ6により回路パターン2と接続され動作する
。このとき発生する熱は、放熱ブロック4により、熱伝
導の断面積を拡大され、基板1及び放熱フィン9を通じ
放熱されるため、低熱抵抗を得ている。
Next, the operation will be explained. The semiconductor chip 5 is connected to the circuit pattern 2 by bonding wires 6 and operates. The heat generated at this time has a cross-sectional area for heat conduction expanded by the heat radiation block 4, and is radiated through the substrate 1 and the heat radiation fins 9, thereby obtaining low thermal resistance.

なおコーティング7は半導体チップ5及びボンディング
ワイヤ6を保護し、デバイスの精度を維持するためのも
のであり、キャップ8は回路パターン2及び該回路パタ
ーン2上に取り付けられる半導体チップ5及びその他の
電子部品を外的衝撃等から保護する役割を果たす。
The coating 7 is for protecting the semiconductor chip 5 and the bonding wires 6 and maintaining the precision of the device, and the cap 8 is for protecting the circuit pattern 2 and the semiconductor chip 5 and other electronic components mounted on the circuit pattern 2. It plays the role of protecting the equipment from external shocks, etc.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の混成集積回路は以上のように構成されているので
、コーティング7とキャップ8の内面との間隔が小さい
場合、キャップ8へ外力が加わるとキャップ8が歪み、
コーティング7へ接触し、その力がボンディングワイヤ
6へ加わり、ボンディングワイヤ6が切れる恐れがあり
、これを防ぐためキャンプ80強度を上げたり、コーテ
ィング7とキャップ8の内面との間隔を大きく取るとい
う方法がとられており、装置の小型化が困難であった。
Since the conventional hybrid integrated circuit is configured as described above, when the distance between the coating 7 and the inner surface of the cap 8 is small, when an external force is applied to the cap 8, the cap 8 is distorted.
There is a risk that the bonding wire 6 will come into contact with the coating 7 and the force will be applied to the bonding wire 6, causing the bonding wire 6 to break.In order to prevent this, the strength of the camp 80 is increased or the distance between the coating 7 and the inner surface of the cap 8 is increased. This makes it difficult to downsize the device.

またコーティング7が横に広がるため、回路パターン2
上に抵抗やコンデンサ等の他の電子部品を取り付ける場
合にコーティング7に接触すると、その接触力がもとで
上記の場合と同様にボンディングワイヤ6切れが起こる
恐れがあり、それゆえ基板1の回路パターン2側でコー
ティング7の回りに十分な広さを取る必要があり、前記
と同様小型化の妨げとなっていた。
Also, since the coating 7 spreads laterally, the circuit pattern 2
If the coating 7 is contacted when other electronic components such as resistors and capacitors are mounted on it, the contact force may cause the bonding wire 6 to break as in the above case, and therefore the circuit on the board 1 may be damaged. It is necessary to provide a sufficient space around the coating 7 on the pattern 2 side, which is an obstacle to miniaturization as described above.

この発明は上記のような問題点を解消するためになされ
たもので、コーティングとキャップの内面との間隔が大
きくならず、またキャップの強度を上げることなく、キ
ャップの外力による歪みによってボンディングワイヤが
切れる可能性を小さくし、かつ、コーティング部分の回
りに他の電子部品との接触防止のための場所を設ける必
要のない混成集積回路を得ることを目的とする。
This invention was made to solve the above-mentioned problems, and does not increase the distance between the coating and the inner surface of the cap, and does not increase the strength of the cap. It is an object of the present invention to obtain a hybrid integrated circuit which reduces the possibility of breakage and which does not require providing a place around the coating part to prevent contact with other electronic parts.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る混成集積回路は、半導体チップを搭載し
た放熱ブロックの一部を、半導体チップ取付は面からキ
ャップの内側のまで延長したものである。
In the hybrid integrated circuit according to the present invention, a part of the heat dissipation block on which the semiconductor chip is mounted is extended from the surface where the semiconductor chip is mounted to the inside of the cap.

〔作用〕[Effect]

この発明においては、半導体チップを搭載した放熱ブロ
ックの一部を、半導体チップ取付は面からキャップの内
側まで延長したので、キャップからの外力は、放熱ブロ
ックに伝わるようになりコーティング部へ直接力が伝わ
らず、ボンディングワイヤが切れることがなく、その結
果、キャップの強度をあげたり、キャップとコーティン
グ部との間隔を太き(とる必要がなくなる。
In this invention, a part of the heat dissipation block on which the semiconductor chip is mounted is extended from the semiconductor chip mounting surface to the inside of the cap, so that the external force from the cap is transmitted to the heat dissipation block and the force is directly applied to the coating part. As a result, the strength of the cap can be increased and there is no need to increase the distance between the cap and the coating part.

また放熱ブロックの一部が高くなっているため、高くな
っている方向へはコーティングが広がらず、放熱ブロッ
クの近くに電子部品を設けることができる。
Further, since a part of the heat radiation block is raised, the coating does not spread in the direction of the height, and electronic components can be provided near the heat radiation block.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例による混成集積回路の放熱ブ
ロック上に半導体チップを組み立てた部分の斜視図であ
り、第2図は第1図中A−A ′線でのキャップを含め
た断面図であり、第3図及び第4図と同一符号は同一ま
たは相当部分を示し、10は放熱ブロックで、その両端
部に鉛直方向に高くした部分10a(延長部)を設け、
断面コ字状としたものである。電気的動作及び放熱につ
いては従来例と同様であるのでここではその説明を省略
し、上記放熱ブロック10の延長部10aの作用効果に
ついて説明する。
FIG. 1 is a perspective view of a part where a semiconductor chip is assembled on a heat dissipation block of a hybrid integrated circuit according to an embodiment of the present invention, and FIG. It is a sectional view, and the same reference numerals as in FIGS. 3 and 4 indicate the same or corresponding parts, and 10 is a heat dissipation block, with vertically elevated portions 10a (extension portions) provided at both ends thereof,
It has a U-shaped cross section. Since the electrical operation and heat radiation are the same as in the conventional example, their explanation will be omitted here, and the effects of the extension portion 10a of the heat radiation block 10 will be explained.

キャップ8より外力が加わり、キャップ8が基板l側に
歪んでも、放熱ブロック10の延長部10aがあるため
、その力は放熱ブロック10に伝わり、ここで受は止め
られ、コーティング7ひいてはボンディングワイヤ6へ
のストレスが非常に小さくなり、ボンディングワイヤ6
の切れる心配が小さくなる。また放熱ブロックの延長部
10aの方向にはコーティング7が広がらず放熱ブロッ
ク10の近くに電子部品を配置することが可能となる。
Even if an external force is applied from the cap 8 and the cap 8 is distorted toward the substrate l, the extended portion 10a of the heat radiation block 10 causes the force to be transmitted to the heat radiation block 10, where the receiving force is stopped, and the coating 7 and the bonding wire 6 The stress on the bonding wire 6 becomes extremely small.
There is less worry about it breaking. Furthermore, the coating 7 does not spread in the direction of the extension 10a of the heat radiation block, making it possible to arrange electronic components near the heat radiation block 10.

このように本実施例によれば、半導体チップ5が搭載さ
れた放熱ブロック10の両端部を鉛直方向に延長し断面
コ字状としたので、キャップ8が外的応力により歪んだ
場合、外力は放熱ブロック10の延長部10aで受は止
められ、コーティング7やボンディングワイヤ6に直接
作用せず、このためキャップ8とコーティング7との間
に接触防止のための大きな間隔を設ける必要がなく、ま
た上記断面コ字状の放熱ブロック10の構造により、コ
ーティング7が延長部4aの方向へ広がらず、該放熱ブ
ロック10近傍に他の電子部品を設けることができ、混
成集積回路の小型化を図ることができる。
According to this embodiment, both ends of the heat dissipation block 10 on which the semiconductor chip 5 is mounted are extended in the vertical direction to form a U-shaped cross section, so that when the cap 8 is distorted due to external stress, the external force is reduced. The receiving part is stopped by the extension part 10a of the heat dissipation block 10 and does not act directly on the coating 7 or the bonding wire 6. Therefore, there is no need to provide a large gap between the cap 8 and the coating 7 to prevent contact. Due to the structure of the heat dissipation block 10 having a U-shaped cross section, the coating 7 does not spread in the direction of the extension portion 4a, and other electronic components can be provided near the heat dissipation block 10, thereby reducing the size of the hybrid integrated circuit. I can do it.

なお、上記実施例では放熱ブロック10をコ字形とした
ものを用いて説明したが、放熱ブロックを回路基板の端
部に設置する場合はコーティングの広がりは基板中央方
向のみを考慮すればよく、この場合、放熱ブロックをL
字形とすることで、上記実施例と同様の効果を奏するこ
とができる。
Note that in the above embodiment, the heat dissipation block 10 was explained using a U-shaped heat dissipation block 10, but when the heat dissipation block is installed at the edge of the circuit board, the spread of the coating only needs to be considered in the direction toward the center of the board; In this case, set the heat dissipation block to L.
By using the letter shape, the same effects as in the above embodiment can be achieved.

また、放熱ブロック10の延長部の構造としては上記実
施例以外に、例えば第5図(a)に示すように、半導体
チップ搭載面の幅よりも広い幅を有する延長部10bと
したものや、同図(b)に示すよに半導体チップ搭載面
の幅よりも狭い幅を有する延長部10cとしたものを用
いてもよく上記と同様の効果が得られる。
Further, as the structure of the extension part of the heat dissipation block 10, in addition to the above embodiments, for example, as shown in FIG. 5(a), an extension part 10b having a width wider than the width of the semiconductor chip mounting surface may be used. As shown in FIG. 3B, an extension 10c having a width narrower than the width of the semiconductor chip mounting surface may be used, and the same effect as described above can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明に係る混成集積回路装置によれ
ば、半導体チップが搭載される放熱ブロックの一部を半
導体チップ取付は面からキャップの内側まで延長したの
で、外的応力が直接コーティングやボンディングワイヤ
に加わることがなく、その結果ボンディングワイヤ切れ
の心配がなく、またコーティングとキャップとの間に接
触防止用の大きな間隔を設ける必要がなく、さらにコー
ティングが放熱ブロック周囲に広がらず、放熱ブロック
近傍に他の電子部品を配置することができ、ひいては装
置の小型化を図ることができるという効果がある。
As described above, according to the hybrid integrated circuit device of the present invention, the part of the heat dissipation block on which the semiconductor chip is mounted is extended from the semiconductor chip mounting surface to the inside of the cap, so that external stress is not directly applied to the coating or the heat dissipation block. It does not touch the bonding wire, so there is no need to worry about the bonding wire breaking, there is no need to provide a large gap between the coating and the cap to prevent contact, and the coating does not spread around the heat dissipation block. This has the effect that other electronic components can be placed nearby, and that the device can be downsized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例による混成集積回路の放熱ブ
ロック上に半導体チップを組み立てた部分の斜視図、第
2図は第1図中A−A ”線でのキャンプを含めた断面
図、第3図は従来例の混成集積回路の放熱ブロックに半
導体チップを組み立てた部分の斜視図、第4図は第3図
中B−B ’線でのキャップを含めた断面図、第5図は
本発明の他の実施例による混成集積回路の放熱ブロック
を示す図である。 1は基板、2は回路パターン、3は接地パターン、5は
半導体チップ、6はボンディングワイヤ、7はコーティ
ング、8はキャップ、9は放熱フィン、10は放熱ブロ
ック、10a、10bは放熱ブロック10の高くなった
部分(延長部)である。 なお図中同一符号は同−又は相当部分を示す。 第1図 71〃 2 、’ Q!2;、’/’9−ン 10 : 47r フo、、、:) 5 ニー1−#Jメノー−7゛ 6 友ンフ7ユ、2′、7.)/;・
FIG. 1 is a perspective view of a semiconductor chip assembled on a heat dissipation block of a hybrid integrated circuit according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line A-A'' in FIG. 1, including a camp. , FIG. 3 is a perspective view of a semiconductor chip assembled into a heat dissipation block of a conventional hybrid integrated circuit, FIG. 4 is a cross-sectional view taken along line B-B' in FIG. 3, including the cap, and FIG. 1 is a diagram showing a heat dissipation block of a hybrid integrated circuit according to another embodiment of the present invention. 1 is a substrate, 2 is a circuit pattern, 3 is a ground pattern, 5 is a semiconductor chip, 6 is a bonding wire, 7 is a coating, 8 1 is a cap, 9 is a heat radiation fin, 10 is a heat radiation block, and 10a and 10b are raised parts (extension parts) of the heat radiation block 10. Note that the same reference numerals in the figures indicate the same or equivalent parts. 〃 2,'Q!2;,'/'9-n10: 47r fo,,:) 5 Knee 1-#J Meno-7゛6 Friend's 7yu, 2', 7.)/;・

Claims (1)

【特許請求の範囲】[Claims] (1)その上面に回路パターンを、裏面に接地パターン
を有する基板と、 上記回路パターン上に取付けられた放熱ブロックと、 該放熱ブロック上に取付けられた半導体チップと、 上記基板の回路パターン側をカバーするキャップとを備
えた混成集積回路において、 上記放熱ブロックの一部を、半導体チップ取付け面から
キャップの内側まで延長したことを特徴とする混成集積
回路。
(1) A board having a circuit pattern on its top surface and a ground pattern on its back surface, a heat dissipation block mounted on the circuit pattern, a semiconductor chip mounted on the heat dissipation block, and a circuit pattern side of the board A hybrid integrated circuit comprising: a covering cap; wherein a part of the heat dissipation block extends from the semiconductor chip mounting surface to the inside of the cap.
JP21116090A 1990-08-07 1990-08-07 Hybrid ic Pending JPH0492461A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21116090A JPH0492461A (en) 1990-08-07 1990-08-07 Hybrid ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21116090A JPH0492461A (en) 1990-08-07 1990-08-07 Hybrid ic

Publications (1)

Publication Number Publication Date
JPH0492461A true JPH0492461A (en) 1992-03-25

Family

ID=16601392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21116090A Pending JPH0492461A (en) 1990-08-07 1990-08-07 Hybrid ic

Country Status (1)

Country Link
JP (1) JPH0492461A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0630175A1 (en) * 1993-06-14 1994-12-21 Blaupunkt-Werke GmbH Electrical assembly cooling device
US5574314A (en) * 1994-07-28 1996-11-12 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor device including shielded inner walls

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0630175A1 (en) * 1993-06-14 1994-12-21 Blaupunkt-Werke GmbH Electrical assembly cooling device
US5574314A (en) * 1994-07-28 1996-11-12 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor device including shielded inner walls

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