JPH048600U - - Google Patents

Info

Publication number
JPH048600U
JPH048600U JP1990047699U JP4769990U JPH048600U JP H048600 U JPH048600 U JP H048600U JP 1990047699 U JP1990047699 U JP 1990047699U JP 4769990 U JP4769990 U JP 4769990U JP H048600 U JPH048600 U JP H048600U
Authority
JP
Japan
Prior art keywords
signal
clear
oscillator
circuit
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990047699U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990047699U priority Critical patent/JPH048600U/ja
Publication of JPH048600U publication Critical patent/JPH048600U/ja
Pending legal-status Critical Current

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  • Monitoring And Testing Of Transmission In General (AREA)
  • Tests Of Electronic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案実施例の使用状態を示すブロツ
ク図、第2図は従来の信号発生回路の使用状態を
示すブロツク図、第3図はカウンタから出力され
る信号の波形図である。 1……発振器、3……パワーオンクリア回路、
11……カウンタ、12……マルチプレクサ。
FIG. 1 is a block diagram showing how the embodiment of the present invention is used, FIG. 2 is a block diagram showing how a conventional signal generating circuit is used, and FIG. 3 is a waveform diagram of the signal output from the counter. 1... Oscillator, 3... Power-on clear circuit,
11...Counter, 12...Multiplexer.

Claims (1)

【実用新案登録請求の範囲】 電源電圧が印加されるとクリア信号を出力する
パワーオンクリア回路と、 所定の周波数の信号を発振する発振回路と、 パワーオンクリア回路のクリア信号を受けて発
振器から出力された信号を高域から低域に亘る複
数の周波数信号に分周して出力し、且つチヤネル
選択信号及び発振器停止用の信号を出力するカウ
ンタと、 カウンタから出力された複数の周波数信号が入
力され、チヤネル選択信号の入力によつて複数の
周波数信号を時系列的に順次出力するマルチプレ
クサとを備えるとともに前記カウンタの出力を受
けて前記発振器が停止するようになしたことを特
徴とする信号発生回路。
[Scope of claim for utility model registration] A power-on clear circuit that outputs a clear signal when a power supply voltage is applied, an oscillation circuit that oscillates a signal at a predetermined frequency, and an oscillator that receives the clear signal from the power-on clear circuit. A counter that divides the output signal into multiple frequency signals ranging from high to low frequencies and outputs a channel selection signal and a signal for stopping the oscillator; and a multiplexer that sequentially outputs a plurality of frequency signals in time series in response to input of a channel selection signal, and the oscillator is configured to stop upon receiving an output of the counter. generation circuit.
JP1990047699U 1990-05-09 1990-05-09 Pending JPH048600U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990047699U JPH048600U (en) 1990-05-09 1990-05-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990047699U JPH048600U (en) 1990-05-09 1990-05-09

Publications (1)

Publication Number Publication Date
JPH048600U true JPH048600U (en) 1992-01-27

Family

ID=31563861

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990047699U Pending JPH048600U (en) 1990-05-09 1990-05-09

Country Status (1)

Country Link
JP (1) JPH048600U (en)

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