JPH0485967A - Passivating method for semiconductor device - Google Patents

Passivating method for semiconductor device

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Publication number
JPH0485967A
JPH0485967A JP20195390A JP20195390A JPH0485967A JP H0485967 A JPH0485967 A JP H0485967A JP 20195390 A JP20195390 A JP 20195390A JP 20195390 A JP20195390 A JP 20195390A JP H0485967 A JPH0485967 A JP H0485967A
Authority
JP
Japan
Prior art keywords
passivation
rubber
cylindrical member
semiconductor element
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20195390A
Other languages
Japanese (ja)
Other versions
JP2811931B2 (en
Inventor
Mitsuru Hanakura
満 花倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp, Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Corp
Priority to JP20195390A priority Critical patent/JP2811931B2/en
Publication of JPH0485967A publication Critical patent/JPH0485967A/en
Application granted granted Critical
Publication of JP2811931B2 publication Critical patent/JP2811931B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Thyristors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To facilitate a passivation by coating the inner surface of a collar of a cylindrical member having the collar at one opening with nonfluidized passivation rubber, then inserting a semiconductor element into the member, and supplying fluidized passivation rubber into a gap between both. CONSTITUTION:A cylindrical member 12 having a collar 12a is prepared therein, and the collar 12a of the member 12 is coated with nonfluidized passivation material 13 inside an opening end. Then, a semiconductor element S which is beveled and in which its working distortion is removed, is inserted into the member 12, and placed on the coated material 13, fluidized passivation material 9 is fed to a gap formed between the element S and the member 12 and cured. In this case, the material 9 is blocked by the material 13, and entirely covered with the passivation material having sufficient thickness.

Description

【発明の詳細な説明】 A、産業上の利用分野 本発明は、電力用等の半導体素子のパッシベーション方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a passivation method for semiconductor devices for power use and the like.

B9発明の概要 本発明は、アロイ・フリー法を用いた半導体素子を用意
し、この筒状部材の鍔部の内側に非流動性のパッシベー
ション材を塗布してこのパッシベーション材の上に前記
の半導体素子を載置して両者間に形成される間隙部に流
動性のパッシベーション材を注入して硬化させることに
より、アロイ・フリー法におけるパッシベーション加工
を容易にし、かつパッシベーション効果を高めたもので
ある。
B9 Summary of the Invention The present invention involves preparing a semiconductor element using the alloy-free method, applying a non-flowing passivation material to the inside of the flange of this cylindrical member, and applying the above-described semiconductor onto the passivation material. By placing the element and injecting a fluid passivation material into the gap formed between the two and curing it, the passivation process in the alloy-free method is facilitated and the passivation effect is enhanced.

C0従来の技術 電力用半導体素子、例えば一般にGTOと略されるゲー
トターンオフサイリスタ等は、自己消弧素子として高耐
電圧で大電流の分野においてますます特徴を発揮しつつ
ある。
BACKGROUND OF THE INVENTION C0 Conventional Technology Power semiconductor devices, such as gate turn-off thyristors, generally abbreviated as GTO, are increasingly exhibiting their characteristics as self-extinguishing devices in the field of high withstand voltages and large currents.

第2図は、この従来例のGTO素子の構成図を示し、基
本的にはPNPNの4層構造をなしている。通常熱緩衝
板8にはSiと熱膨張係数の近いタングステン円板又は
モリブデン円板が用いられている。即ち、 ■はNエミツタ層、2はPベース層、3はNベース層、
4はPエミッタ層で半導体素子が構成されている。尚、
第2図において5はNバッファ層、6はNショート層、
7bはアノード電極、8は熱緩衝板を示し、この熱緩衝
板8は通常はSiと熱膨張係数の近いタングステン円板
もしくはモリブデン円板が用いられる。
FIG. 2 shows a configuration diagram of this conventional GTO element, which basically has a four-layer structure of PNPN. Usually, the thermal buffer plate 8 is made of a tungsten disk or a molybdenum disk, which has a coefficient of thermal expansion similar to that of Si. That is, ① is the N emitter layer, 2 is the P base layer, 3 is the N base layer,
4 is a P emitter layer that constitutes a semiconductor element. still,
In FIG. 2, 5 is an N buffer layer, 6 is an N short layer,
7b is an anode electrode, and 8 is a thermal buffer plate. The thermal buffer plate 8 is usually a tungsten disk or a molybdenum disk having a coefficient of thermal expansion similar to that of Si.

またアノード電極7bは、2〜20重量%ノSi含有の
Al−8i薄膜のロー材を熱緩衝板8にSi半導体ペレ
ットか合金されることによって形成される。また、Kは
カソード端子、Aはアノード端子、Gはゲート端子を示
している。
The anode electrode 7b is formed by alloying an Al-8i thin film brazing material containing 2 to 20% by weight of Si to the thermal buffer plate 8 with Si semiconductor pellets. Further, K indicates a cathode terminal, A indicates an anode terminal, and G indicates a gate terminal.

この種の半導体素子は、その端面に電界か集中するため
、電界集中を緩和して高耐電圧とするために、半導体素
子の端面を傾斜させるベベル加工を施し、その端面を絶
縁性の高い誘導体で覆う所謂パッシベーション加工が行
われている。
In this type of semiconductor element, the electric field concentrates on the end face, so in order to alleviate the electric field concentration and achieve a high withstand voltage, the end face of the semiconductor element is beveled and the end face is covered with a highly insulating dielectric. A so-called passivation process is performed.

このパッシベーション加工は、第2図に示すように半導
体素子ベベル加工を行った後、工・ソチングにより加工
歪みを除去してベベル加工面に間隙をつくり、そこにパ
ッシベーションゴム9を流し込んで硬化させる。
In this passivation process, as shown in FIG. 2, after the semiconductor element is beveled, processing distortion is removed by machining and sawching to create a gap in the beveled surface, and passivation rubber 9 is poured into the gap and hardened.

この流し込んだパッシベーションゴムは熱緩衝板8によ
りせき止められてベベル面を十分な厚みで覆うようにし
ている。
The poured passivation rubber is blocked by the thermal buffer plate 8 so as to cover the beveled surface with a sufficient thickness.

しかし、上記合金法によるアノード電極形成方法では、
半導体素子と熱緩衝板との熱膨張係数の差により素子の
反り及びカソード電極の熱疲労が生じるという問題点が
あり、このため熱緩衝板を厚くし、またカソードエミッ
タを放射状に配置する等の処置が必要となっていた。
However, in the anode electrode formation method using the above alloy method,
There is a problem in that the difference in thermal expansion coefficient between the semiconductor element and the thermal buffer plate causes warpage of the element and thermal fatigue of the cathode electrode, so it is necessary to make the thermal buffer plate thicker and arrange the cathode emitters radially. Treatment was required.

その結果、合金法においては高価な熱緩衝板の使用量が
増えてコストアップの大きな原因となっており、更にカ
ソードエミッタの放射状配置は幾何学的に素子の面積効
率が悪いため、素子の大電流化に不利な構成となってい
る。
As a result, in the alloy method, the amount of expensive thermal buffer plates used increases, which is a major cause of cost increase.Furthermore, the radial arrangement of cathode emitters has geometrical inefficiencies in the area of the element, resulting in an increase in the size of the element. It has a configuration that is disadvantageous to electric current.

更に、合金の使用により半導体素子のアノードエミッタ
側である合金面側が10μm以上侵食されるため、素子
の特性が不均一になったり、又アノードエミッタ側の拡
散層を過剰に深く形成しなければならないという問題点
も生じている。
Furthermore, due to the use of an alloy, the alloy surface side, which is the anode emitter side of the semiconductor device, is eroded by 10 μm or more, resulting in nonuniform device characteristics and the need to form an excessively deep diffusion layer on the anode emitter side. This problem also arises.

上記のような問題点を解決するために、アノード電極を
合金によらずに形成する所謂アロイ・フリー法が提案さ
れており、この製法による半導体素子が一部製品化され
ている。
In order to solve the above problems, a so-called alloy-free method has been proposed in which the anode electrode is formed without using an alloy, and some semiconductor devices have been commercialized using this manufacturing method.

第3図はこのアロイ・フリー法による半導体素子の説明
図を示す。
FIG. 3 shows an explanatory diagram of a semiconductor device produced by this alloy-free method.

同図において78はアノード電極を示し、半導体素子S
を構成している 第3図を第2図と比較すると、熱緩衝板8がなく、また
アノード電極1は合金により形成せずに圧接により形成
している点が異なっている。
In the figure, 78 indicates an anode electrode, and the semiconductor element S
Comparing FIG. 3 with FIG. 2, the differences are that there is no thermal buffer plate 8 and that the anode electrode 1 is not formed of an alloy but is formed by pressure welding.

このアロイ・フリー法による半導体素子のパッシベーシ
ョン加工は、ベベル加工後、エツチングにより加工歪み
を除去してベベル面にポリイミド10を塗布し、次にそ
の上からシリコン樹脂11をトランスファ成形すること
により行っている。
Passivation processing of semiconductor elements by this alloy-free method is performed by removing processing distortion by etching after bevel processing, applying polyimide 10 to the beveled surface, and then transfer-molding silicone resin 11 on top of it. There is.

D1発明が解決しようとする課題 しかし、上記のアロイ・フリー法においては、熱緩衝板
8が無く、従って流動性のパッシベーションゴムを流し
込んだ際にこれをせき止める部材がなくなっている。
D1 Problems to be Solved by the Invention However, in the above-mentioned alloy-free method, there is no thermal buffer plate 8, and therefore there is no member to stop the flowable passivation rubber when it is poured.

このため、ベベル面にポリイミドを塗布し、更にその上
にシリコン樹脂をトランスファ成形せねばならない。
For this reason, it is necessary to apply polyimide to the beveled surface and transfer-mold silicone resin thereon.

従って、合金法においてはパッシベーションゴムを塗布
して熱処理(キュアー)を行う一連の作業であったパッ
シベーション加工が、アロイ・フリー法においては上記
のようにポリイミドを塗布して熱処理を施した後、シリ
コン樹脂のトランスファ成形を行うという二連の作業を
必要として工程が複雑になっている。
Therefore, in the alloy method, passivation processing is a series of operations in which passivation rubber is applied and heat treated (cured), but in the alloy free method, polyimide is applied and heat treated as described above, and then silicone The process is complicated because it requires two steps: resin transfer molding.

また、ベベル表面にポリイミドを塗布する際にベベル表
面でポリイミドが弾かれてしまったり、気泡が形成され
たり、また塗布したポリイミドとシリコン樹脂間にも気
泡や空隙が発しやすい等の問題点があり、良好なパッシ
ベーション効果が得られ難いという問題点がある。
Furthermore, when applying polyimide to the bevel surface, there are problems such as the polyimide being repelled by the bevel surface, air bubbles being formed, and air bubbles and voids easily forming between the applied polyimide and silicone resin. However, there is a problem in that it is difficult to obtain a good passivation effect.

本発明はこのような背景の下になされたものであり、ア
ロイ・フリー法を用いて、従来の合金法ト同様に簡便で
パッシベーション効果の高いパッシベーション加工方法
を提供することを目的とする。
The present invention was made against this background, and an object of the present invention is to provide a passivation processing method using an alloy-free method that is as simple as the conventional alloy method and has a high passivation effect.

E1課題を解決するための手段 本発明における上記の課題を解決するための手段は、半
導体素子のアロイ・フリー法を用いたパッシベーション
加工方法において、内部に鍔部を有する筒状部材を用意
し、この筒状部材の前記鍔部の開口端部の内側に非流動
性のパッシベーション材を塗布し、次に、ベベル加工し
加工歪みを除去した半導体素子を、前記筒状部材の中に
挿入して塗布したパッシベーション材上に載置すると共
に、これら半導体素子と筒状部材との間に形成された間
隙に、流動性のパッシベーション材を流し込んで硬化さ
せる。
E1 Means for Solving the Problem The means for solving the above problem in the present invention is to provide a cylindrical member having a flange inside in a passivation processing method using an alloy-free method for a semiconductor element, A non-flowing passivation material is applied to the inside of the open end of the flange of this cylindrical member, and then a semiconductor element that has been beveled to remove processing distortion is inserted into the cylindrical member. It is placed on the applied passivation material, and a fluid passivation material is poured into the gap formed between the semiconductor element and the cylindrical member and hardened.

F0作用 上記のように、内部に鍔部を有する筒状部材の鍔部の開
口端部の内側に非流動性のパッシベーション材を塗布し
、その上に半導体素子を載置したので、半導体素子のベ
ベル面と筒状部材の間隙に流動性のパッシベーション材
を流し込む際このパッシベーション材は非流動性のパッ
シベーション材によりせき止められ、全体的に十分な厚
みのパッシベーション材で覆われる。
F0 effect As described above, a non-flowable passivation material is applied to the inside of the open end of the flange of a cylindrical member having a flange inside, and a semiconductor element is placed on top of the non-flowable passivation material. When a fluid passivation material is poured into the gap between the beveled surface and the cylindrical member, this passivation material is dammed up by a non-flowable passivation material, and the entire surface is covered with a sufficiently thick passivation material.

G、実施例 以下、第1図を用いて本実施例に係る半導体のパッシベ
ーション加工方法を説明する。
G. Example A semiconductor passivation processing method according to this example will be described below with reference to FIG.

第1図において、半導体素子Sの基本構成は第3図のも
のと同様なので説明を省略する。
In FIG. 1, the basic configuration of the semiconductor element S is the same as that in FIG. 3, so a description thereof will be omitted.

12は好ましくはテフロンまたはシリコン樹脂等で形成
された、好ましくは円筒状の筒状部材で、その一端側に
、鍔部12aと、これにより形成される開口部が設けら
れている。
Reference numeral 12 denotes a preferably cylindrical member made of Teflon or silicone resin, and has a flange 12a and an opening formed by the flange 12a at one end thereof.

13は鍔部12aの開口部に近い開口端部の内側に塗布
した非流動性のパッシベーションゴム、14は半導体素
子Sの上面の縁側に塗布した非流動性のパッシベーショ
ンゴムを示し、9は流動性パッシベーションゴムを示し
ている。
Reference numeral 13 indicates a non-flowable passivation rubber applied to the inside of the opening end near the opening of the flange 12a, 14 indicates a non-flowable passivation rubber applied to the edge of the upper surface of the semiconductor element S, and 9 indicates a flowable passivation rubber. Showing passivation rubber.

以下、本実施例に係るパッシベーション加工の工程を説
明する。
The passivation process according to this embodiment will be described below.

まず、筒状部材12を用意する。次にこの筒状部材12
の鍔部12aの開口部側の内側に非流動性パッシベーシ
ョンゴム13を半導体素子Sの下面の径よりやや小径の
リング状に均一に塗布し、適宜の高さに盛り上げる。
First, the cylindrical member 12 is prepared. Next, this cylindrical member 12
A non-flowable passivation rubber 13 is uniformly applied to the inside of the opening side of the flange 12a in a ring shape having a diameter slightly smaller than the diameter of the lower surface of the semiconductor element S, and raised to an appropriate height.

その後、予めベベル加工及びエツチングによる加工歪み
の除去を行った半導体素子Sを、第1図に示されるよう
に前記筒状樹脂12内部に挿入して上記非流動性パッシ
ベーションゴム13の上に固定する。
Thereafter, the semiconductor element S, which has been subjected to bevel processing and etching to remove processing distortion, is inserted into the cylindrical resin 12 and fixed onto the non-flowable passivation rubber 13, as shown in FIG. .

また、半導体素子Sの上面の縁近くにも、非流動性パッ
シベーションゴム14をリング状に塗布しておく。この
ようにして半導体素子Sと筒状部材間に流動性パッシベ
ーションゴムを流入し得る間隙が形成される。
In addition, non-flowable passivation rubber 14 is also applied in a ring shape near the edge of the upper surface of the semiconductor element S. In this way, a gap is formed between the semiconductor element S and the cylindrical member into which the fluid passivation rubber can flow.

次にこの間隙に流動性パッシベーションゴム9を流し込
む。このとき、非流動性パッシベーションゴム13がパ
ッシベーションゴム9の流出をせき止め、また非流動性
パッシベーションゴム14がカソード電極側への流れ込
みを防止する。
Next, fluid passivation rubber 9 is poured into this gap. At this time, the non-flowable passivation rubber 13 blocks the outflow of the passivation rubber 9, and the non-flowable passivation rubber 14 prevents it from flowing into the cathode electrode side.

この作業の終了後、従来の方法で流動性パッシベーショ
ンゴム9を硬化させる。
After this operation is completed, the flowable passivation rubber 9 is cured in a conventional manner.

本発明は以上のように筒状部材12と半導体素子Sを上
記のように構成したことにより、従来の合金法のパッシ
ベーション加工と同様に上記の間隙部に流動性パッシベ
ーションゴム9を流入して硬化させることができ、従来
の合金法と同様に一連の作業でパッシベーション加工を
行うことができる。
By configuring the cylindrical member 12 and the semiconductor element S as described above, the present invention allows fluid passivation rubber 9 to flow into the gap and harden, similar to the conventional alloy method passivation process. The passivation process can be performed in a series of operations similar to the conventional alloy method.

本実施例においては、筒状部材と半導体素子Sとを非流
動性パッシベーションゴム13により接着し、上記間隙
部からの流動性パッシベーションゴム9の漏れを防いで
いるが、他の接着手段を用いるか、もしくは接着手段を
用いずに流動性の小さいパッシベーションゴムをこの加
工に用いる等により上記間隙部からのパッシベーション
ゴムの漏れを防ぐ構成にしても良い。
In this embodiment, the cylindrical member and the semiconductor element S are bonded together using the non-flowable passivation rubber 13 to prevent the flowable passivation rubber 9 from leaking from the gap, but other bonding means may be used. Alternatively, a configuration may be adopted in which leakage of the passivation rubber from the above-mentioned gap is prevented by using a passivation rubber with low fluidity for this processing without using an adhesive means.

また、上記の実施例においては流動性パッンベションゴ
ム9のカソード電極への流入を防止するため、カソード
電極の上面に非流動性パッシベーションゴム14を塗布
してこの侵入を防ぐ構成としたが、他の手段等により流
出を防止すればこの非流動性パッシベーションゴム14
は必ずしも必要ではない。
Further, in the above embodiment, in order to prevent the flowable passivation rubber 9 from flowing into the cathode electrode, a non-flowable passivation rubber 14 is applied to the upper surface of the cathode electrode to prevent this intrusion. If the outflow is prevented by other means, this non-flowable passivation rubber 14
is not necessarily necessary.

H8発明の効果 本発明によれば、一方の開口部に鍔部を有する筒状部材
の鍔部の内面に非流動性のパッシベーションゴムの塗布
を行った後に半導体素子を上記筒状部材内に挿入し、両
者の間に間隙部を形成している。
H8 Effects of the Invention According to the present invention, a non-flowing passivation rubber is applied to the inner surface of the flange of a cylindrical member having a flange at one opening, and then a semiconductor element is inserted into the cylindrical member. However, a gap is formed between the two.

この構成により、合金法と同様に、上記の間隙部に流動
性のパッシベーションゴムを流入することにより、容易
にパッシベーション加工を行うことが出来る。
With this configuration, similarly to the alloy method, passivation processing can be easily performed by flowing the fluid passivation rubber into the above-mentioned gap.

更に、従来のアロイ・フリー法におけるパッシベーショ
ン加工に比して、半導体素子か十分な厚みのゴムで満遍
なく覆われるためにパッシベーション効果が高く、歩留
まり及び信用性に優れたものとなっている。
Furthermore, compared to the passivation process in the conventional alloy-free method, the semiconductor element is evenly covered with a sufficiently thick rubber, so the passivation effect is high and the yield and reliability are excellent.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明におけるパッシベーション加工を行っ
た半導体素子の構成図、第2図は合金法を用いてパッシ
ベーション加工を行った半導体素子の構成図、第3図は
従来のアロイ・フリー法を用いた半導体素子の構成図で
ある。 1・・・Nエミツタ層、2・・・Pベース層、3・・・
Nベース層、4・・・Pエミッタ層、5・・・Nバッフ
ァ層、6・・・Nショート層、7・・・アノード電極、
8・・・熱緩衝板、9・・・流動性パッシベーションゴ
ム、10・・・ポリイミド、11シリコン樹脂、12・
・・筒状部材、12a・・・鍔部13.14・・・非流
動性パッシベーションゴム第1図 本発明における半導体素子の構成図 第2図 従来例における半導休業fの構成図 第3図
Fig. 1 is a block diagram of a semiconductor device that has been passivated using the present invention, Fig. 2 is a block diagram of a semiconductor device that has been passivated using the alloy method, and Fig. 3 is a block diagram of a semiconductor device that has been passivated using the alloy method. It is a block diagram of the semiconductor element used. 1...N emitter layer, 2...P base layer, 3...
N base layer, 4... P emitter layer, 5... N buffer layer, 6... N short layer, 7... anode electrode,
8... Thermal buffer plate, 9... Fluid passivation rubber, 10... Polyimide, 11 Silicone resin, 12...
...Cylindrical member, 12a...Flame portion 13, 14...Non-flowable passivation rubber Fig. 1 A structural diagram of a semiconductor element in the present invention Fig. 2 A structural diagram of a semiconductor element f in a conventional example Fig. 3

Claims (1)

【特許請求の範囲】[Claims] (1)半導体素子のアロイ・フリー法を用いたパッシベ
ーション加工方法において、 内部に鍔部を有する筒状部材を用意し、この筒状部材の
前記鍔部の開口端部の内側に非流動性のパッシベーショ
ン材を塗布し、次に、ベベル加工し加工歪みを除去した
半導体素子を、前記筒状部材の中に挿入して塗布したパ
ッシベーション材上に載置すると共に、これら半導体素
子と筒状部材との間に形成された間隙に、流動性のパッ
シベーション材を流し込んで硬化させるようにしたこと
を特徴とする半導体素子パッシベーション加工方法。
(1) In a passivation processing method using an alloy-free method for semiconductor devices, a cylindrical member having a flange inside is prepared, and a non-flowing material is placed inside the open end of the flange of this cylindrical member. A passivation material is applied, and then the semiconductor element, which has been beveled to remove processing distortion, is inserted into the cylindrical member and placed on the applied passivation material, and the semiconductor elements and the cylindrical member are placed on top of the applied passivation material. A semiconductor device passivation processing method, characterized in that a fluid passivation material is poured into a gap formed between the two and hardened.
JP20195390A 1990-07-30 1990-07-30 Semiconductor element passivation processing method Expired - Lifetime JP2811931B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20195390A JP2811931B2 (en) 1990-07-30 1990-07-30 Semiconductor element passivation processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20195390A JP2811931B2 (en) 1990-07-30 1990-07-30 Semiconductor element passivation processing method

Publications (2)

Publication Number Publication Date
JPH0485967A true JPH0485967A (en) 1992-03-18
JP2811931B2 JP2811931B2 (en) 1998-10-15

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP20195390A Expired - Lifetime JP2811931B2 (en) 1990-07-30 1990-07-30 Semiconductor element passivation processing method

Country Status (1)

Country Link
JP (1) JP2811931B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6423566B1 (en) 1998-07-24 2002-07-23 International Business Machines Corporation Moisture and ion barrier for protection of devices and interconnect structures

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6423566B1 (en) 1998-07-24 2002-07-23 International Business Machines Corporation Moisture and ion barrier for protection of devices and interconnect structures

Also Published As

Publication number Publication date
JP2811931B2 (en) 1998-10-15

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