JPH0483373A - Signal output circuit for checking integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the number of terminals by outputting a single signal to be directly supplied from an inner circuit from an output terminal, and outputting a signal selected by signal selecting means from the output terminal when a plurality of input/output terminals are switched for inputting. CONSTITUTION:A plurality of input/output terminals 121 and l2n are switched for inputting or outputting by a control signal to be input from an input terminal 10. If the control signal is, for example, at a low level, a plurality of signals for observing mutual timing from an inner circuit 13 are output from the plurality of the terminals 121-12n switched for outputting. In this case, one of the plurality of signals for observing the mutual timing is output from an output terminal 15 through output switching means 14. When the control signal is at a high level, a signal selected by signal selecting means 16 from the plurality of the input/output terminals switched from a select signal for inputting is output from the terminal 15. Accordingly, the plurality of the terminals 121-12n can be used for both inputting and outputting, thereby reducing the number of terminals.

Description

[Detailed Description of the Invention] [Summary] Regarding an integrated circuit check signal output circuit that outputs a signal to the outside to check the integrated circuit, the present invention relates to a check signal output circuit for an integrated circuit that outputs a signal to the outside to check the integrated circuit. This is a signal output circuit for checking integrated circuits that is designed to observe a large number of signals, and includes circuits that are checked by simultaneously outputting multiple signals and circuits that are checked by outputting multiple signals individually. , multiple input/output terminals are switched between input and output according to the level of the control signal supplied from the input terminal, and when switched to output, the multiple signals output by the internal circuit are transferred to the multiple input/output terminals. The input/output switching means outputs from the input/output switching means, and the plurality of signals output from the internal circuit in response to the plurality of signals supplied from the input/output switching means or the plurality of input/output terminals switched for input according to the level of the control signal. When the signal selection means selects a single signal and the input/output switching means switches the plurality of input/output terminals for output according to the level of the control signal, the single signal directly supplied from the internal circuit is output to the output terminal. and output switching means for outputting a signal selected by the signal selection means from the output terminal when the plurality of input/output terminals are switched for input.

[Industrial application field]

The present invention relates to a signal output circuit for checking an integrated circuit, which outputs a signal to the outside for checking the integrated circuit.

When checking the output signals of an integrated circuit, there are cases in which the mutual timing of multiple signals is observed at the same time, and cases in which the signal levels are observed individually. For this purpose, external terminals are required to observe signals, but since the number of external terminals for checking integrated circuits is limited, it is necessary to check many signals with a small number of external terminals. be.

[Conventional technology]

When observing the signals of the integrated circuit, it is necessary to simultaneously observe the signals output from the internal circuit 60 from the external terminals 60a to 60(l) and check the switching timing of each signal, as shown in FIG. 5(A). In some cases, and also in Fig. 5 (
As shown in B), the signal output from the internal circuit 61 is connected to the terminal 61.
There are cases where it is sufficient to individually observe the signals output from a to 61h and know their levels. The eight output signals of the internal circuit 61 are input to the select circuit 63 as shown in FIG. terminal 6
Output from 4. This results in one output terminal.

[Problem to be solved by the invention]

For example, when it is desired to observe the output signal in FIG. 5(A), the output of the internal circuit 60 is 4 terminals, and when it is desired to observe the output signal in FIG. 5(B), the output of the internal circuit 61 is 8 terminals. As a result, 12 terminals are required to perform the observation shown in FIG. 5(A), in which signals are observed at the same timing, and the observation shown in FIG. 5(B), in which signal levels are observed individually. Furthermore, as shown in FIG. 5(C), when observing the signal level individually, the select signal is input from three terminals, and even when selecting the signal to be observed from the internal circuit 62, four terminals are required. Combined with the observation in Figure 5 (A), 8
A terminal is required.

Therefore, even if a certain number of external terminals are set for checking, a large number of terminals are required when observing the mutual timing of internal circuit signals or when individually observing the level of output signals, resulting in a shortage of terminals. There was a problem.

The present invention has been made in view of the above points, and it is an object of the present invention to observe many signals output from internal circuits of an integrated circuit using a small number of external terminals for checking.

[Means to solve the problem]

FIG. 1 shows a diagram explaining the principle of the present invention. The input/output switching means 11 has a plurality of input/output terminals 121 to 12 . is switched between input and output, and a plurality of signals outputted by the internal circuit 18 when switched to output are transmitted to the plurality of input/output terminals 121 to 12. Output from

The signal selection means 16 selects the input/output terminal 12 which is switched for input by the input/output switching means 11 according to the control signal.
．． ~12. A single signal is selected from the plurality of signals output by the internal circuit 13 in accordance with the plurality of signals supplied from the internal circuit 13.

The output switching means 14 switches the input/output switching means 11 to a plurality of input/output terminals 121 to 121 according to the control signal.
When switched to output, a single signal directly supplied from internal circuit 13 is output from output terminal 15, and when multiple input/output terminals 12° to 126 are switched to input, output switching means 14 outputs a single signal directly supplied from internal circuit 13. The signal selected by the signal selection means 16 is outputted from the output terminal 15.

[Effect]

The present invention operates by controlling a plurality of input/output terminals 12 . to 12 are switched to either input or output. For example, when the control signal is at a low level, a plurality of input/output terminals 12 are switched to output a plurality of signals for observing mutual timing from the internal circuit 13. Output from ~12°. At this time, one of the plurality of signals whose mutual timings are also observed is output from the output terminal 15 via the output switching means 14.

When the control signal is at a high level, the signal selected by the signal selection means 16 is outputted from the plurality of input/output terminals that have been switched to input the select signal via the input/output switching means 14 and is then output to the output terminal 15 via the switching means 14. It is output from Therefore, multiple input/output terminals 121 to 12
ゎ can be used for both input and output, and output terminal 15
Since the output terminal 15 can output the control signal and the signals to be individually observed, the number of terminals can be reduced.

〔Example〕

FIG. 2 shows a configuration diagram of an embodiment of the present invention. In the figure, 20 is an input terminal to which a control signal is input. If the control signal is low level, the control signal is controlled so that the signals are output at the same timing, and if the control signal is high level, the entire circuit is controlled so that the signals are output individually.

50 and 51 are internal circuits, respectively. The internal circuit 50 needs to check the mutual timing of the four systems of signals output from terminals 5 to 504, and the internal circuit 51 needs to check the mutual timing of the four systems of signals output from terminals 5 to 504. ~51. All you have to do is check the level of the signal output from each separately.

21 is an output switching circuit, which is switched by a control signal and outputs an inverter 21a, an AND circuit 21b,
21c and an OR circuit 21d. The control signal is inverted by the inverter 21a and the AND circuit 2
1b. Further, the control signal is directly supplied to one input terminal of the AND circuit 21c without being inverted. The internal circuit 50 is connected to the other input terminal of the AND circuit 21b. The other input terminal of the AND circuit 21c of the output switching circuit 21 is supplied with a signal from a select circuit 29, which will be described later.

AND circuit 2 when the control signal is high level
1c becomes conductive and outputs the output signal of the selector circuit 29 from the output terminal 22 via the OR circuit 21d. When the control signal is at a low level, the AND circuit 21b becomes conductive and outputs the output signal of the internal circuit 5° from the output terminal 22 via the OR circuit 21d.

25 is an input/output switching circuit, and buffers 23a, 2
3b123C,) Right state buffer 24a, 24b
124c.

When the control signal is at a low level, the tri-state buffer 24 becomes active, and the internal circuit terminals 50.
The output signals from ~504 are sent to multiple input/output terminals 26a, 2.
6b and 26c, respectively.

When the control signal is at a high level, the tristate buffer 24 enters a high output impedance state. In this case, a plurality of input/output terminals 26a.

The signals entering 26b and 26c are sent to the buffer 23a123.
terminals 28A and 28B of the decoder 28 through b and 24c
, 28C.

27 is a signal selection circuit composed of a decoder 28 and a selector 29.

The decoder 28 decodes the signals supplied to the terminals 28A, 28B, and 28C and outputs an enable signal from one of the terminals XO to X7. Output terminal XO of decoder 28
-X7 correspond to the input terminals A1 to H1 of the selector 29 and output to each of them.

Output signals from terminals 511 to 51m of internal circuit 51 are supplied to terminals A2 to H2 of selector 29. Selector 2
9 terminals A1, Bl, C1, Dl, El, Fl, G1,
Hl and A2, B2, C2, B2, B2, F2, G2, H
2 corresponds, and the signal supplied to the terminal A2 to H2 corresponding to one of the terminals A1 to H1 to which the enable signal is input is taken out, inverted and output from the terminal X, further inverted by the inverter 30, and output. It is supplied to the AND circuit 21b of the switching circuit 21.

Here, when the control signal is input at a low level, the tri-state buffer 24 becomes active, so that a plurality of input/output terminals 26a, 26b are connected as shown by the broken line in FIG.
, 26c functions as an output terminal. This results in
Terminal 50 of internal circuit 50. The signal is outputted from the output terminal 22 via the output switching circuit 21 as shown by the broken line in FIG. Further, the tri-state buffers 24a, 124b, 24c of the input/output switching circuit 25 are activated, and the input/output terminals 26a, 26b, 26c are connected to the terminals 502, 50s, 50,
The signal from is output. In this case, the mutual timings of the four systems of signals in the internal circuit 50 can be checked.

Next, when a high level control signal is input, the tri-state buffers 24a and 24b.

24c is in a high impedance state, the plurality of input/output terminals 26a, 26b, and 26c function as input terminals. Thereby, the select signal coming from the external circuit passes through the buffers 23a, 23b, 23c to the terminals 28A, 28B of the decoder 28.

28C, and in response to this select signal, the selector 29 selects the terminals 511-51. of the internal circuit 51 that are supplied to the terminals A2-H2. A single signal is extracted from each output signal of. This signal is supplied to the output switching circuit 21 through the inverter 30, and is output from the output terminal 22 via the AND circuit 21c and the OR circuit 21d.

The output switching circuit 21 is connected to the internal circuit 50 from the output terminal 22.
terminal 50. When performing output from terminal 51 . of internal circuit 51 . ~51. There are two types of switching when performing individual output from the .

According to this embodiment, the number of checking terminals can be five in total, so the number of terminals can be reduced.

Note that the internal circuits 50 and 51 of this embodiment may be a single circuit, and are not limited to the above embodiment.

〔Effect of the invention〕

As described above, according to the integrated circuit check signal output method of the present invention, it is not necessary to use separate output terminals when observing simultaneous timing check signals and individual timing check signals, so the number of terminals of the integrated circuit can be reduced. This is useful for rational use of integrated circuits.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a configuration diagram of an embodiment of the present invention, Fig. 3 is a diagram showing signals when observing the same timing in an embodiment of the present invention, and Fig. 4 is FIG. 5 is a diagram showing signals when observing individual timings according to an embodiment of the present invention. FIG. 5 is a diagram showing the number of signals when observing signals of a conventional integrated circuit. In the figure, IO is an external input terminal, 11 is input/output switching means, 12. ~12° are input/output terminals, 13 is an internal circuit, 14 is an output switching means, 15 is an output terminal, 16 is a signal selection means, 20 is an input terminal, 21 is an output switching circuit, 22 is an output terminal, 25 is an input/output 26 is an input/output terminal; 27 is a signal selection circuit; 28 is a decoder; 29 is a selector 50 which is an internal circuit; and 51 is an internal circuit. Fig. 2 is a configuration diagram of an embodiment of the present invention. Fig. 2 is an explanatory diagram of the principles of the present invention. (A) Signals to be observed simultaneously (B) Signals to be observed individually (C) Select signal selection Signal walk diagram when observing conventional integrated circuit signals

Claims (1)

[Scope of Claims] A signal output circuit for checking an integrated circuit that includes a circuit that is checked by simultaneously outputting a plurality of signals and a circuit that is checked by outputting a plurality of signals individually. ) The plurality of input/output terminals (12_1 to 12_n) are switched between input and output according to the control signal supplied from an input/output switching means (11) that outputs from the input/output terminals (12_1 to 12_n) of the input/output terminal (12_n), and an input/output terminal (12_n) which is switched for input by the input/output switching means (11) according to the level of the control signal.
signal selection means (16) for selecting a single signal from the plurality of signals output by the internal circuit (13) in response to the plurality of signals supplied from the input/output circuits (1 to 12_n); Switching means (1
When 1) switches the plurality of input/output terminals (12_1 to 12_n) for output, a single signal directly supplied from the internal circuit (13) is output from the output terminal (15), and the plurality of input/output terminals (12_1 to 12_n) are The output switching means (14) outputs the signal selected by the signal selection means (16) from the output terminal (15) when the output terminals (12_1 to 12_n) are switched for input. Signal output circuit for checking integrated circuits.