JPH0481963A - System bus extending device - Google Patents

Abstract

PURPOSE:To decrease the fact that a transfer on a main system bus is allowed to wait, and to enhance the transfer efficiency by executing an answer by only an interruption processing time of the system bus extending device against an actuation from a central processor. CONSTITUTION:When an interruption from input/output controllers 7a, 7b on an extension system bus 3 is executed, a microprocessor (MPU) 12 executes an interruption processing, based on information (state management information of input/output controllers 7a, 7b) stored in a local memory 13. In this case, the MPU 12 executes an answer by only an interruption processing time of a system bus extending device 1 against an actuation from a central processor 4. In such a way, the time when a main system bus 2 is occupied by an interruption processing on the extension system bus 3 is shortened, a fact that a transfer on the main system bus 2 is allowed to wait decreases, and the transfer efficiency can be enhanced.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a system bus expansion device that connects a main system bus and an expansion system bus of a computer system, and particularly relates to a system bus expansion device that connects a main system bus and an expansion system bus of a computer system. Regarding interrupt control.

(Prior Art) Many computer systems employ system buses. A system bus commonly connects different types of devices, such as a central processing unit, main memory, and input/output control device, and transfers data between devices.
It is characterized by excellent flexibility.

A system bus requires a high transfer capacity because all devices commonly transfer data. For this reason, limits are generally placed on the length of the system bus and the number of connected devices to ensure electrical conditions and enable high-speed transfer.

If a number of devices exceeding this limit are to be connected to a system bus, a system bus expansion device is connected to the system bus to create a hierarchical configuration of the bus. Here, the system bus expansion device is a device that relays data transfer between system buses.

Therefore, the system bus expansion device (hereinafter referred to as 5BSE) is a main system bus to which the central processing unit, main memory, input/output control device, etc. are connected, and an input/output control device for the purpose of adding input/output control devices. It connects the extended system bus to which the system bus is connected, and relays input/output commands, data transfer, and input/output interrupts between the two system buses.

(Problems to be Solved by the Invention) In the computer system described above, when operating a plurality of input/output control devices connected to the expansion system bus, or when operating devices connected to the main system bus, All transfers, including data transfers, compete on the main system bus. Therefore, while one transfer occupies the system bus, waiting time occurs for other transfers. One type of transfer is interrupt processing transfer.

Conventional interrupt processing times are shown in FIGS. 2(a) and 2(b).

In the interrupt processing of the input/output control device connected to the main system bus, the central processing unit (CP
It's called U. ) to an input/output control device (hereinafter referred to as IO).

) and returns a response from T0 to CPIJ. The processing time from activation to response is assumed to be T1.

Next, the interrupt processing time of the input/output control device connected to the expansion system bus is T1, which is the same time as the interrupt processing of the main system bus on the expansion system bus, as shown in (b) of the same figure. In addition, additional processing time T2 is required in the 5BSH for relaying activation from the main system bus to the expansion system bus, and processing time T3 in the 5BSH for relaying responses from the expansion system bus to the main system bus. In other words, the time that the main system bus is occupied is longer in interrupt processing on the extended system bus than in interrupt processing on the main system bus (FIG. 3(a)).

(see (b)).

Thus, interrupt processing on the extended system bus occupies the main system bus for a long time and stops other transfers, thus affecting the performance of the system bus.

SUMMARY OF THE INVENTION An object of the present invention is to provide a system bus expansion device that can reduce the time that the main system bus is occupied by interrupt processing during transfers on the main system bus, and improve the efficiency of system bus usage. There is a particular thing.

(Means for Solving the Problems) The present invention provides a main system bus to which a central processing unit, a main storage device, and an input/output control device are connected, and an expansion system bus for realizing the addition of input/output control devices. Connect and input/output commands between both system buses.

A system bus expansion device that performs data transfer and relay control of input/output interrupts stores state management information of the input/output control device on the expansion system bus, and connects the input/output control device on the expansion system bus to the central processing unit. storage means for storing interrupt information to the device; and receiving interrupts from the expansion system bus without synchronization with the central processing unit;
and control means for performing interrupt processing based on information stored in the storage means.

(Function) Therefore, when there is an interrupt from the input/output control device on the expansion system bus, the control means processes the interrupt based on the information (state management information of the input/output control device) stored in the storage means. do. In this case, the control means can respond to the activation from the central processing unit only in the interrupt processing time of the system bus expansion device. As a result, the time during which the main system bus is occupied by interrupt processing on the extended system bus is shortened compared to the past, so that transfers on the main system bus are less likely to have to wait, and transfer efficiency can be improved.

(Example) Next, the present invention will be explained using the drawings.

FIG. 3 is a system configuration diagram according to the present invention.

In the same figure, system bus expansion equipment (SBSE) 1
A main system bus (hereinafter referred to as MSB) 2 and an extended system bus (hereinafter referred to as SSB) 3 are connected to. The MSB 2 includes a central processing unit (CPU) 4, a main memory device (hereinafter referred to as MEM) 5, and an input/output control device (1
0) 6a and 6b are connected. Also, in 5SB3, l
07a.

7b is connected.

FIG. 1 is a block diagram showing an embodiment of the 5BSE 1 shown in FIG.

In Figure 1, the MSB interface (hereinafter referred to as MSB
I) 8 is an interface unit for transfer of interrupts and the like with the MSB, and a microprocessor (hereinafter referred to as MPU) 12 and a data buffer 10 are connected to the MSB I 8. Further, an SSB interface (hereinafter referred to as 5SBI) 9 is an interface section for data transfer with the SSB, and an MPU 12 and a data buffer 10 are connected to the 5SBI 9.

The data buffer 10 serves as a memory read data buffer when reading MEM5 of MSB2 from IO of 5SB3.
Consists of memory write data buffer when writing from SB3 IO to MSB2 MEM5, MSBI8 and 5SB
I9 is connected.

Furthermore, the MPU 12 controls the relaying of input/output commands and input/output interrupts using a microprogram.
BI8, 5SBI9, local memory (hereinafter referred to as LM) 13, and control memory (hereinafter referred to as CM) 11 are connected. The LM 13 is a memory that stores various control information for relaying input/output commands and input/output interrupts, and can be read and written by the MPU 12 . CMl
1 is a memory in which a microprogram executed by the MPU 12 is stored.

Next, the input/output operations activated by the CPU 4 in FIGS. 3 and 1 will be explained using FIG. 4. Note that FIG. 4 shows the input/output operation protocol between the CPUs 4-5BSEI-I 07a and 7b.

The CPU 4 sends an input/output command for IO, here l07a, to the 5BSE 1. The information of this input/output instruction includes operation command, transfer destination memory address,
Contains the number of transferred data. When the 5BSEI receives an input/output command, the MSBI 8 notifies the MPU 12 of the input/output command.

Here, the LM13 is prepared with an area for storing state management information for each IO, and the state is operable state (
These state transitions are shown in FIG. 5: (hereinafter referred to as the A state), an active or interrupt waiting state (hereinafter referred to as the BSY state), and one interrupt pending state (hereinafter referred to as the ■ state).

The MPU 12 accesses the LM 13 and starts it.
If the state is 7a, check, tick, and if it is not in A state, CPU4
A status response indicating that the operation is not possible is made. MPU
12, when the state of the l07a to be started is the A state, the input/output command is inputted to start the work 07a of the 5SB3.
5SBI9 is started in order to send to 07a. Then, the activated 5SBI9 sends an input/output command to activate the l07a to the 5SB3. When l07a receives an input/output command, it sends a response to 5B indicating whether the command is normal or not.
Send to SE 1. 5BSEI is l07a
If the response status from LM1 is judged to be normal, LM1
Information “A” in the state management information storage area of l07a in 3.
"state" is set to "BSY state" (see Figure 5), and
When 5BSE 1 determines that the response status from l07a is abnormal, LM13
The information "A state" in the state management information storage area of l07a is set to "working state" (see FIG. 5), and an interrupt is sent to the CPU 4. The interrupt transmission procedure is from the MPU 12 to the MS.
Starts to send interrupt to BI8, MSBI8 sends CP
Send the interrupt transmission to tJ4 to MSB2.

Next, a case will be described in which the response status of l07a to activation is normal.

E07a analyzes the received input/output command and starts the specified input/output operation. And when the operation is finished,
5Send termination interrupt to BSE l. 5BSE
1 receives the termination interrupt, the 5SBI9 recognizes the interrupt and notifies the MPU 12.

MPIJ12 sets interrupt permission to 5 for interrupt of 5SB3.
The channel status word sent from l07a is sent to l07a via SBI9, and the channel status word sent from l07a is sent to 5SB.
It is received via I9 (see FIG. 4 for the above).

Here, the channel status word has the format shown in FIG. 6, and includes the end status of the channel, the end status of the unit, and the number of bytes remaining at the time of end.

It consists of the next command address and detailed channel status information, and serves as a standard for determining whether the activated command terminated normally or abnormally.

The MPU 12 stores the channel status word received from l07a in the LM13. An area for storing this channel status word is prepared for each process 0 in the LM 13. Then, the MPU 12 sets the state management information of l07a to "I state" among the state management information held for each IO in the LM13, and the CPU 4 Send an interrupt to

Next, processing after the MPU 12 transmits an interrupt to the CPU 4 will be described.

When CPU4 receives an interrupt from 5BSE 1, 5B
Sends an interrupt grant to MSB2, just as SE 1 did to 5SB3. Then, in 5BSE 1 that received the interrupt permission, the interrupt permission is transferred from MSBIB to MP.
U12 is notified, and MPU12 receives l07 from LM13.
Activate MSB I 8 to read the channel status word of a and transfer it to CPU 4, and MSBIB
Transfer the channel status word of l07a to 2 (
(See Figure 4 above).

The MPU 12 further changes the state management information of I07a in the LM 13 to "A state".

In this way, the channel status word for interrupt permission from CPU4 is set to 5SB3 without accessing 5SB3.
Since the BSE 1 responds to the CPU 4, the response time can be shortened (see FIG. 4). Therefore, for example, l
When 06a and 6b are transferring data between MEMs 5 and 5SB3, the time that MSB2 is occupied by the interrupt processing with 5SB3 is shortened, so MSB2 can be used efficiently for data transfer.

Finally, a case will be described in which interrupts from several IOs overlap.

Assume that interrupts from IO on the system bus are divided into eight levels. Here, for example, it is assumed that l07a interrupts at level l, and l07b interrupts at level 5. 5 depending on input/output commands from CPU4 at each IO interrupt level.
By setting this in advance in the LM 13 of BSE 1, it is possible to process interrupts even if interrupts from several IOs overlap. For this purpose, the system bus is provided with signal lines for the interrupt request itself and the interrupt level.

Now, 5BSEI (7) (7) When the SSBI9 recognizes that it has received level 1 and level 5 interrupts from the IO, it notifies the MPU 12 of this.The 0 interrupt permission is sent for each level. , the interrupt permission is sent from the interrupt with the highest priority. Assuming that the priorities are in order from level O to level 7, the MPU 12 first sends interrupt permission for level 1, which has the highest priority, to the corresponding I07a.

When the MPU 12 receives the channel status word from the l07a, it stores it in the corresponding location of the LM 13 and sends an interrupt permission for level 5 to the l07b.

Similarly, when the MPU 12 receives the channel status word from the I 07b, it stores the information in the LM 13 at a corresponding location.

Next, the MPU 12 stores level l information in the LM 13, sets the state management information in the LM 13 to the "working state", and sends an interrupt to the CPU 4.
2 is the level 5 information L for the level 5 interrupt.
An attempt is made to store the interrupt in M13 and send the interrupt to the CPU 4, but since a level 1 interrupt is already being sent, the interrupt is put on hold.

Here, the 5BSE 1 has an interrupt queue for each interrupt level in the LM13, and when one interrupt is being sent, the number of IO that is pending in the interrupt queue of the corresponding level. If there are two or more interrupts of the same level, they are linked by IO number.

Using the above queue, the level 1 interrupt will be 5BSE
1 is being sent, the level 5 interrupt will be at the head of the level 5 interrupt queue.

If interrupt permission is granted for level 1 interrupts, the MPU 12
reads the level 1 channel status word from LM13 and transfers it to CPU4, then sets the state management information of l07a in LM13 to "A state" and sets the interrupt queue to level 0.
In this case, since I07b at the head of the level 5 interrupt queue is found, I07b is removed from the interrupt queue and sent to the level 5 interrupt CPU 4. The following is the same as in the case of the level 1 interrupt described above.

If you use such a queue, you can suspend multiple IO interrupts at multiple levels or at the same level.
Interrupt processing can be controlled without problems.

As can be seen from the above explanation, by having IO status management information in 5BSE 1, it has become possible to perform primary management of 107a, 7b, . . . connected to 5SB3. Further, the interrupt processing time on the extended system bus according to the present invention is as shown in FIG. 2(C). Therefore,
In the present invention, for booting from the CPU 4, as shown in FIG.
The conventional interrupt processing time T2. shown in FIG. Eliminate T3, 5B
It is now possible to respond in only the interrupt processing time T1 of SE1. As a result, the time that the main system bus (MSB) 2 is occupied by interrupt processing on the expansion system bus (SSB) 3 can be reduced compared to the conventional method.
Transfers on the main system bus (MSB) 3 are not kept waiting, and transfer efficiency can be improved.

The present invention is not limited to this embodiment, and various applications and modifications can be made without departing from the gist of the present invention.

(Effects of the Invention) As described above, if the present invention is used, the control means can respond to activation from the central processing unit using only the interrupt processing time of the system bus expansion device. Due to the above interrupt processing, the time during which the main system bus is occupied can be shortened compared to the conventional method, and therefore, transfer on the main system bus is less likely to be made to wait, and transfer efficiency can be improved. Furthermore, by storing the status management information of the input/output control devices on the expansion system bus in the storage means, it is possible to centrally manage the input/output control devices connected to the expansion system bus.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing an embodiment of the system bus expansion device shown in FIG. A system configuration diagram according to the present invention, FIG. 4 is an explanatory diagram showing the input/output operation protocol between CPU-5BSE-I0, FIG. 5 is an IO state transition diagram in 5BSE, and FIG. 6 is a channel status word It is a figure showing a format. 1... System bus expansion device (SBSE), 2...
Main system bus (MSB), 3... Expansion system bus (SSB), 4... Central processing unit (CPU), 5... Main memory device (MEM), 6a, 6b, 7a, 7b." Output control device (10), 8...MSB interface (MSB ri, 9...S
SB interface (SSBI), 12-... Microprocessor (MPU), 13... Local memory (L
M). Patent applicant: Oki Electric Industry Co., Ltd. Response: Expansion system according to the present invention! < Interrupt processing on the above (c) Interrupt processing time of the prior art and the present invention Fig. 2 (Part 2) Input/output operation protocol Fig. 4

Claims (1)

[Claims] 1. A main system bus to which the central processing unit, main memory, and input/output control device are connected, and an expansion system bus for realizing the expansion of the input/output control device are connected, and both systems A system bus expansion device that performs relay control of input/output commands, data transfer, and input/output interrupts between buses, which stores state management information of the input/output control device of the expansion system bus, and stores input/output control information on the expansion system bus. storage means for storing interrupt information from an output control device to the central processing unit; and storage means for receiving interrupts from the expansion system bus without synchronization with the central processing unit and storing them in the storage means. A system bus expansion device comprising: control means for performing interrupt processing based on certain information. 2. When a plurality of interrupts from a plurality of input/output control devices on the expansion system bus to the central processing unit overlap, the control means transmits interrupts to the central processing unit on the main system bus in a predetermined order. Claim 1, wherein the input/output control device interrupt is suspended in the storage means before the interrupt is notified to the central processing unit.
System bus expansion device as described.