JPH0481002A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable secure grounding and easy assembly by providing a plane capacitor for which one main face is connected while being centralizing to a ground electrode and the other main face is connected respectively to the field effect transistor and the strip line of a semiconductor substrate. CONSTITUTION:On a GaAs substrate 12, the gate electrode of the FET and a parallel plane capacitor 26 are connected by plural wires 34, and the parallel plane capacitor 26 and a strip line 20 are connected by plural wires 36. On the GaAs substrate 12, the drain electrode of the FET and a parallel plane capacitor 28 are connected by plural wires 38, and the parallel plane capacitor 28 and a strip line 24 are connected by plural wires 40. The parallel plane capacitor 26 and the strip line 20 constitute an input side matching circuit, and the parallel plane capacitor 28 and the strip line 24 constitute an output side matching circuit. Thus, the secure grounding and the easy assembly can be realized.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, particularly an internally matched FET in which a matching circuit is provided in a field effect transistor (FET) for power amplification.
Regarding.

[Prior Art] An internally matched FET is known in which a matching circuit is connected to the input and output electrodes, that is, the gate electrode and the drain electrode, of a GaAs FET for high frequency power amplification, and the FET is housed in a single barrier gauge.

A conventional internally matched FET is shown in FIG. FIG. 5(a) is a plan view, and FIG. 2(b) is a sectional view.

Three steps are formed on the upper surface of the metal substrate 50, with the center being higher. The highest central part has Ga with an FET formed.
An As substrate 52 is closely connected. Parallel plate capacitors 5 are provided on the input side of the second stage on both sides of the central part of the metal substrate 50.
4 are tightly connected, and a parallel plate capacitor 56 is connected on the output side.
are closely connected. Furthermore, the lowest 3 of the metal substrate 50
A dielectric substrate 58 is closely connected to the input side of the stepped surface, and a dielectric substrate 60 is closely connected to the output side.

Strip lines 62 and 64 are formed on dielectric substrates 58 and 60, respectively, as part of a matching circuit.

The gate electrode of the FET on the GaAs substrate 52 and the parallel plate capacitor 54 are connected by a plurality of wires 66,
Furthermore, a parallel plate capacitor 54 and a strip line 62
are connected by a plurality of wires 68. GaA
The drain t'I of the FET on the s-substrate 52 and the parallel plate capacitor 56 are connected by a plurality of wires 70, and further, the parallel plate capacitor 56 and the strip line 64 are connected by a plurality of wires 72. In addition, G
The source electrode of the FET on the aAs substrate 52 is the metal substrate 50
It is connected to the.

The parallel plate capacitor 54 and the strip line 62 constitute a matching circuit on the input side, and the parallel plate capacitor 56 and the strip line 64 constitute a matching circuit on the output side.

[Problems to be Solved by the Invention] However, in the case of a conventional internally matched FET, when the parallel plate capacitors 54, 56 are soldered to the metal substrate 50, the parallel plate capacitors 54, 56 are thin at about 100 μm, so that they protrude. The top and bottom surfaces may be short-circuited due to soldering,
There was a problem that the grounding to the metal substrate 50 was insufficient.

Further, since a complicated three-step difference is formed on the metal substrate 50, high processing accuracy is required, and there are also problems in that it is extremely difficult to assemble the GaAs substrate 52 and the parallel plate capacitors 56 and 58.

The purpose of the invention is to be easy to assemble and to
To provide a semiconductor device in which the upper and lower surfaces of a parallel plate capacitor are reliably grounded without shorting.

[Means for solving the problem] The above purpose is. A semiconductor substrate having a field effect transistor formed on one main surface, a metal substrate to which the other main surface of the semiconductor substrate is closely connected, and a dielectric provided on the metal substrate adjacent to the semiconductor substrate. a substrate, and is formed at a position 19IilC on the semiconductor substrate on the dielectric substrate,
A ground electrode connected to the metal substrate, a strip line formed on the dielectric substrate adjacent to the ground electrode, one main surface of which is tightly connected to the ground electrode, and the other main surface of which is closely connected to the ground electrode. This is achieved by a semiconductor device comprising a field effect transistor of the semiconductor substrate and a plate capacitor connected to the strip line, respectively.

[Function] According to the present invention, the upper and lower surfaces of the parallel plate capacitor can be reliably grounded without shorting, and can be easily assembled.

[Actual example] An internally matched FET according to an embodiment of the present invention will be described with reference to FIG. FIG. 5(a) is a plan view, and FIG. 5b) is a sectional view.

The metal substrate 10 is made of a metal conductor with good heat dissipation and electrical conductivity, such as copper, and has a convex portion formed in the center. On the upper surface of this convex portion, an FET is formed with a thickness of approximately 30 to 100 μm.
A thick GaAs substrate 12 is closely connected. On the input side of the metal substrate 10, a dielectric substrate 14 made of ceramic or the like is in close contact with i! # A similar dielectric substrate 16 is closely connected to the output side.

A ground electrode 18 made of Au or the like is formed on the side of the GaAs substrate 12 on the dielectric substrate 14, and a ground t! j 18
A strip line 20 made of Au or the like is formed adjacent to the strip line 20 . Similarly, a ground electrode 22 is formed on the dielectric substrate 16 on the side of the GaAs substrate 12, and a strip line 24 is formed adjacent to the ground electrode 22.

The parallel plate capacitors 26 and 28 are formed of high dielectric constant substrates approximately 100 μm thick. The parallel plate capacitor 26 on the input side is soldered onto the ground electrode 18 using eutectic solder such as Au-Ge. Similarly, the parallel plate capacitor 28 on the output side is soldered to ground on the pole 22.

The upper surface of the convex portion of the metal substrate 10 and the ground electrode 18 on the input side are connected by a plurality of wires 30, and the metal substrate 1
The upper surface of the convex portion 0 and the ground electrode 22 on the output side are connected by a plurality of wires 32.

The gate electrode of the FET on the GaAs substrate 12 and the parallel plate capacitor 26 are connected by a plurality of wires 34,
Furthermore, a parallel plate capacitor 26 and a strip line 20
are connected by a plurality of wires 36. GaA
The drain electrode of the FET on the s-substrate 12 and the parallel plate capacitor 28 are connected by a plurality of wires 38, and further, the parallel plate capacitor 28 and the strip line 24 are connected by a plurality of wires 40. In addition, G
The source electrode of the FET on the aAs substrate 12 is the metal substrate 10
It is connected to the.

The parallel plate capacitor 26 and the strip line 20 constitute a matching circuit on the input side, and the parallel plate capacitor 28 and the strip line 24 constitute a matching circuit on the output side.

A method of assembling the internally matched FET of this example will be explained.

First -1 ground electrode 18.22 and strip line 20
．． Dielectric substrates 14 and 16 on which 24 are respectively formed are prepared and closely connected to both sides of the convex portion of the metal substrate 10.

Next, the upper surface of the convex portion of the metal substrate 10 and the ground electrode 18.22 are connected by a plurality of wires 30.32.

Subsequently, the ground electrode 18.22 of each dielectric substrate 14.16
Parallel plate capacitors 26 and 28 are placed on each A u
- Solder with eutectic solder such as Ge.

Next, the GaAs substrate 12 is tightly placed on the upper surface of the convex portion of the metal substrate 10! ＃Pillow.

Subsequently, the gate electrode of PET on the G A S substrate 12 and the parallel plate capacitor 26 are connected by a plurality of wires 34, the parallel plate capacitor 26 and the strip line 20 are connected by a plurality of wires 36, GaAs
The drain electrode of the FET on the substrate 12 and the parallel plate capacitor 28 are connected by a plurality of wires 38, and the parallel plate capacitor 28 and the strip line 24 are connected by a plurality of wires 40.

Next, another method of assembling the internally matched FET of this embodiment will be described.

Before bonding the dielectric substrate 14, 16 to the metal substrate 10,
Parallel plate capacitors 26.28 are soldered onto the ground electrodes 18.22 of the dielectric substrates 14.16, respectively. Since soldering is done before being bonded to the metal substrate 10, it is possible to solder the parallel plate capacitors 26 and 28 in a wide area where it is easy to work, instead of in a narrow area inside the package as in the conventional case, improving work efficiency. .

After soldering the parallel plate capacitors 26 and 28, the dielectric substrates 14 and 16 are closely connected to both sides of the convex portion of the metal substrate 10.

Subsequently, the upper surface of the convex portion of the metal substrate 10 and the ground electrode 18.22
and are connected by a plurality of wires 30 and 32.

Next, a GaAs substrate 12 is closely connected to the upper surface of the convex portion of the metal substrate 10.

Subsequently, the gate electrode of the FET on the GaAs substrate 12 and the parallel plate capacitor 26 are connected by a plurality of wires 34, and the parallel plate capacitor 26 and the strip line 20 are connected.
are connected by a plurality of wires 36, and the GaAs substrate 1
The drain electrode of the FET on 2 and the parallel plate capacitor 28
are connected by a plurality of wires 38, and the parallel plate capacitor 28 and the strip line 24 are connected by a plurality of wires 4.
Connect by 0.

As described above, according to this embodiment, since the metal substrate has a simple shape, processing is easy. Furthermore, since the parallel plate capacitor is closely connected to the ground electrode, reliable grounding is possible, and there is no possibility of short-circuiting between the upper and lower surfaces of the parallel plate capacitor during assembly.

Furthermore, it is also possible to solder a parallel plate capacitor to a dielectric substrate in a state with good workability before adhering it to a metal substrate.

The present invention is not limited to the above embodiments, and various modifications are possible.

For example, in the above embodiment, a convex portion is formed on a metal substrate, and a dielectric substrate is placed on the metal substrate on both sides of the convex portion, so that the top surface of the convex portion of the metal substrate and the top surface of the dielectric substrate are approximately at the same height. However, they do not necessarily need to be at the same height, and although the connection is made using wire, a metal conductor such as a gold ribbon may also be used.

Further, although a GaAs substrate was used in the above embodiment, other semiconductor substrates may be used.

[Effects of the Invention] As described above, according to the present invention, the upper and lower surfaces of the parallel plate capacitor can be reliably grounded without short-circuiting, and can be easily assembled.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an internally matched FET according to an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional internally matched FET. In the figure, 10...metal substrate 12...GaAs substrate 14.16...dielectric substrate 18.22...ground electrode 20.24...strip line 26.28...parallel plate capacitor 30~ 40...Wire 50...Metal substrate 52...GaAs substrate 54.56...Parallel plate capacitor 58.60...Dielectric substrate 62.64...Strip line 66-72...Wire

Claims (1)

[Claims] 1. A semiconductor substrate with a field effect transistor formed on one main surface, a metal substrate to which another main surface of the semiconductor substrate is closely connected, and a dielectric provided on the metal substrate adjacent to the semiconductor substrate. a substrate; a ground electrode formed on the dielectric substrate at a position adjacent to the semiconductor substrate and connected to the metal substrate; and a strip line formed on the dielectric substrate at a position adjacent to the ground electrode. A semiconductor device, wherein one main surface is closely connected to the ground electrode, and the other main surface has a flat plate capacitor connected to the field effect transistor of the semiconductor substrate and the strip line, respectively.