JPH0478173A - Semiconductor device with built-in eprom - Google Patents
Semiconductor device with built-in epromInfo
- Publication number
- JPH0478173A JPH0478173A JP2191743A JP19174390A JPH0478173A JP H0478173 A JPH0478173 A JP H0478173A JP 2191743 A JP2191743 A JP 2191743A JP 19174390 A JP19174390 A JP 19174390A JP H0478173 A JPH0478173 A JP H0478173A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polyimide film
- eprom
- window
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 229920001721 polyimide Polymers 0.000 claims abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 8
- 238000002161 passivation Methods 0.000 abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- 239000008188 pellet Substances 0.000 abstract description 3
- 230000008646 thermal stress Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 abstract description 2
- 230000035882 stress Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＥＰＲＯＭ内蔵型半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device with a built-in EPROM.
Ｃ従来の技術〕
従来のＥＰＲＯＭ内蔵型半導体装置は第２図に示すよう
に、最終保護膜（パッシベーション膜）は窒化シリコン
膜８やオキシ窒化シリコン膜が用いられていた。窒化シ
リコン膜８の厚さは０．３〜０．５μｍである。C. Prior Art] As shown in FIG. 2, a conventional EPROM built-in semiconductor device uses a silicon nitride film 8 or a silicon oxynitride film as the final protective film (passivation film). The thickness of silicon nitride film 8 is 0.3 to 0.5 μm.
近年のプロセスの微細化により、半導体装置のベレット
表面の凹凸は大きくなる一方である。この為凹凸の大き
い場所では半導体装置が受ける熱ストレスにより、パッ
シベーション膜か割れたり、またこの場所が微細な配線
の部分だったりすると配線がスライドするなどの問題が
あった。Due to the miniaturization of processes in recent years, the unevenness of the pellet surface of semiconductor devices continues to increase. For this reason, in areas with large irregularities, there are problems such as the passivation film cracking due to thermal stress to which the semiconductor device is subjected, and if the area is a part of fine wiring, the wiring may slide.
この対策にはペレット表面の平坦化が必要であるが、従
来のパッシベーション材料である窒化シリコン膜やオキ
シ窒化シリコン膜では平坦化を行うのが困難であった。To counter this, it is necessary to flatten the pellet surface, but it has been difficult to flatten the surface with conventional passivation materials such as silicon nitride films and silicon oxynitride films.
本発明のＥＰＲＯＭ内蔵型半導体装置は、ＥＰＲＯＭ素
子の少なくともゲート電極上方に窓を有するポリイミド
膜で保護されているというものである。The EPROM built-in semiconductor device of the present invention is protected by a polyimide film having a window at least above the gate electrode of the EPROM element.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示す半導体チップの断面図
である。FIG. 1 is a sectional view of a semiconductor chip showing one embodiment of the present invention.
この実施例において、パッシベーション膜は、半導体チ
ップ表面を覆う厚さ０．３μｍの窒化シリコンＭ９と、
厚さ３〜４μｍのポリイミド膜１０ （ＥＰＲＯＭ素子
のゲート電極（浮遊ゲート［ｆｉ３）の上方に窓１１を
有している）とからなっている。In this example, the passivation film is made of silicon nitride M9 with a thickness of 0.3 μm that covers the semiconductor chip surface;
It consists of a polyimide film 10 (having a window 11 above the gate electrode (floating gate [fi3)] of the EPROM element) with a thickness of 3 to 4 μm.
窒化シリコン膜９はポリイミド膜１０とアルミニウム配
線７とが直接触れるのを防止している。The silicon nitride film 9 prevents the polyimide film 10 and the aluminum wiring 7 from coming into direct contact.
ポリイミド膜は平坦性に優れているが、紫外線に対し不
透明である。しかし、浮遊ゲート電極３上方に窓１１が
設けられているので、ウェーハ状態で書込み、特性チエ
ツク後に消去作業を行うことが可能となる。Although polyimide film has excellent flatness, it is opaque to ultraviolet light. However, since the window 11 is provided above the floating gate electrode 3, it is possible to perform writing in the wafer state and erase after checking the characteristics.
窓１１はＥＰＲＯＭ素子ごとに設ける必要はなく、ＥＰ
ＲＯＭ部全体に一つ設けてもよい。いずれにせよ、ポリ
イミド膜を全面に被着したのちフォトリソグラフィー技
術により選択的に除去して窓を形成すればよい。It is not necessary to provide the window 11 for each EPROM element;
One may be provided in the entire ROM section. In any case, a window may be formed by depositing a polyimide film over the entire surface and then selectively removing it using photolithography.
以上説明したように本発明は、メモリートランジスタ（
ＥＰＲＯＭ素子）のゲート電極上部を除きポリイミド膜
を被着してバ・ソシヘーション膜とすることにより、熱
ストしスによるベレ・ソト表面への応力を緩和すること
か出来、ＥＰＲＯＭ内蔵型半導体装置の信頼性を改善で
きる効果かある。As explained above, the present invention provides a memory transistor (
By depositing a polyimide film on the upper part of the gate electrode of the EPROM element (except for the upper part of the gate electrode) to form a barrier film, it is possible to alleviate the stress on the surface due to thermal stress, and it is possible to It has the effect of improving reliability.
第１図は本発明の一実施例を示す断面図、第２図は従来
例を示す断面図である。
１・・・Ｐ型シリコン基板、２ｄ１．２ｄ２・・・ドレ
イン領域、２Ｓ１，２３２・・・ソース領域、３・・・
浮遊ゲート電極、４・・・制御ゲート電極、５・・酸化
シリコン膜、６・・・層間絶縁膜、７・・アルミニウム
配線、８，９・・・窒化シリコン膜、１０・・・ポリイ
ミド膜、１１・・・窓。FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional example. 1...P-type silicon substrate, 2d1.2d2...drain region, 2S1, 232...source region, 3...
Floating gate electrode, 4... Control gate electrode, 5... Silicon oxide film, 6... Interlayer insulating film, 7... Aluminum wiring, 8, 9... Silicon nitride film, 10... Polyimide film, 11...window.
Claims (1)
するポリイミド膜で保護されていることを特徴とするＥ
ＰＲＯＭ内蔵型半導体装置。E characterized in that the EPROM element is protected by a polyimide film having a window above at least the gate electrode.
PROM built-in semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2191743A JPH0478173A (en) | 1990-07-19 | 1990-07-19 | Semiconductor device with built-in eprom |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2191743A JPH0478173A (en) | 1990-07-19 | 1990-07-19 | Semiconductor device with built-in eprom |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0478173A true JPH0478173A (en) | 1992-03-12 |
Family
ID=16279765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2191743A Pending JPH0478173A (en) | 1990-07-19 | 1990-07-19 | Semiconductor device with built-in eprom |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0478173A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6815322B2 (en) * | 2002-07-10 | 2004-11-09 | Renesas Technology Corp. | Fabrication method of semiconductor device |
| US6849896B2 (en) * | 1999-06-10 | 2005-02-01 | Intel Corporation | Flash memory with UV opaque passivation layer |
| JP2009149380A (en) * | 2002-05-24 | 2009-07-09 | Nippon Express Co Ltd | Cold insulating container for delivery |
-
1990
- 1990-07-19 JP JP2191743A patent/JPH0478173A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6849896B2 (en) * | 1999-06-10 | 2005-02-01 | Intel Corporation | Flash memory with UV opaque passivation layer |
| JP2009149380A (en) * | 2002-05-24 | 2009-07-09 | Nippon Express Co Ltd | Cold insulating container for delivery |
| US6815322B2 (en) * | 2002-07-10 | 2004-11-09 | Renesas Technology Corp. | Fabrication method of semiconductor device |
| US6963513B2 (en) | 2002-07-10 | 2005-11-08 | Renesas Technology Corp. | Fabrication method of semiconductor device |
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