JPH0478015B2 - - Google Patents
Info
- Publication number
- JPH0478015B2 JPH0478015B2 JP59096535A JP9653584A JPH0478015B2 JP H0478015 B2 JPH0478015 B2 JP H0478015B2 JP 59096535 A JP59096535 A JP 59096535A JP 9653584 A JP9653584 A JP 9653584A JP H0478015 B2 JPH0478015 B2 JP H0478015B2
- Authority
- JP
- Japan
- Prior art keywords
- hole
- pin
- substrate
- semiconductor device
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 41
- 229910000679 solder Inorganic materials 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 238000001465 metallisation Methods 0.000 claims description 17
- 229920005989 resin Polymers 0.000 claims description 14
- 239000011347 resin Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 5
- 238000005476 soldering Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 description 17
- 238000005219 brazing Methods 0.000 description 14
- 238000007789 sealing Methods 0.000 description 14
- 239000008188 pellet Substances 0.000 description 12
- 230000004907 flux Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000003780 insertion Methods 0.000 description 4
- 230000037431 insertion Effects 0.000 description 4
- 229920001296 polysiloxane Polymers 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000013013 elastic material Substances 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000010186 staining Methods 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、半導体装置のパツケージ基板におけ
る電気系統の信頼性向上に適用して有効な技術に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique that is effective when applied to improving the reliability of an electrical system in a package substrate of a semiconductor device.
基板が樹脂で形成されてなる、いわゆるピング
リツドアレイ型半導体装置は、セラミツク基板を
用いることにより形成している。
A so-called pin grid array type semiconductor device whose substrate is made of resin is formed by using a ceramic substrate.
その際、基板の定位置にスルーホールを形成し
該スルーホールを介してまたは該スルーホールに
植設されている外部端子を介して、搭載するペレ
ツトと電気的に接続されている基板上面の配線か
ら基板裏面の配線や外部へ電気的導通を取り出し
ている。 At that time, a through hole is formed at a fixed position on the board, and wiring on the top surface of the board is electrically connected to the pellet to be mounted through the through hole or through an external terminal planted in the through hole. Electrical continuity is taken out from the board to the wiring on the back of the board and to the outside.
その場合、スルーホールの壁面には基板上面ま
たは下面の銅等からなる配線と電気的に接続され
ている金等の金属層を形成する必要がある。 In that case, it is necessary to form a metal layer such as gold on the wall surface of the through hole, which is electrically connected to wiring made of copper or the like on the upper or lower surface of the substrate.
ところで、本発明者は高価なセラミツク基板に
替えて、安価な樹脂基板を用いてピングリツドア
レイ型半導体装置を構成することに着目したが、
この場合、次のような問題があることを発見し
た。 By the way, the present inventor focused on constructing a pin grid array type semiconductor device using an inexpensive resin substrate instead of an expensive ceramic substrate.
In this case, the following problems were discovered.
前記金属層は余り厚く形成できないこと、それ
故に物性の異なる樹脂の表面に被着されている金
属層は、温度サイクルにより比較的切断または剥
れが生じ易く、特に基板上面または下面に形成さ
れている配線等のメタライズと配線層との接続部
であるスルーホール開口部付近で特に切断等が発
生し易いということが本発明者により見い出され
た。 The metal layer cannot be formed too thick; therefore, the metal layer adhered to the surface of the resin having different physical properties is relatively likely to be cut or peeled off due to temperature cycles. The inventor has discovered that cutting is particularly likely to occur near the opening of the through hole, which is the connection between the metallization of the wiring and the wiring layer.
なお、セラミツクを用いたピングリツドアレイ
型パツケージについては、雑誌「電子材料」1982
年８月号P54〜55に示されている。 Regarding the pin grid array type package using ceramic, please refer to the magazine "Electronic Materials" 1982.
It is shown on pages 54-55 of the August issue.
本発明の目的は、パツケージの樹脂基板におけ
る電気系統に関し、半導体装置の信頼性向上に適
用して有効な技術を提供することにある。
An object of the present invention is to provide an effective technology that can be applied to improve the reliability of semiconductor devices regarding electrical systems in resin substrates of packages.
本発明の他の目的は、前記半導体装置を製造す
るに好適な技術を提供することにある。 Another object of the present invention is to provide a technique suitable for manufacturing the semiconductor device.
本発明の前記ならびにその他の目的と新規な特
徴は、本明細書の記述および添付図面から明らか
になるであろう。 The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なも
のの概要を簡単に説明すれば、次の通りである。
A brief overview of typical inventions disclosed in this application is as follows.
すなわち、樹脂で形成されてなるピングリツド
アレイ型半導体装置のパツケージ基板に形成され
ている、該基板上面または下面に形成されている
配線等のメタライズと電気的に接続されている金
属層が壁面に被着されているスルーホールについ
て、少くともメタライズと金属層との接続部であ
るスルーホール開口部を被覆するようにろう材を
被着することにより、熱履歴等の物理的変化を受
けた場合に切断や剥れが生じ易い接続部を有効に
保護することができることにより、半導体装置の
信頼性を向上させることができるものである。 That is, a metal layer electrically connected to metallization such as wiring formed on the upper or lower surface of the substrate, which is formed on a package substrate of a pin grid array type semiconductor device made of resin, is a wall surface. By applying brazing filler metal to cover at least the opening of the through-hole, which is the connection between the metallization and the metal layer, the through-hole that is adhered to the metal layer can undergo physical changes such as thermal history. The reliability of the semiconductor device can be improved by effectively protecting the connection portions that are likely to be cut or peeled off in some cases.
また、前記ろう材を被着する場合、熔融ろう材
浴にパツケージ基板全体または一部を浸漬するこ
とにより、スルーホールにおける毛管現象を利用
しスルーホール開口部付近または該開口部付近を
含めたスルーホール全体にろう材を被着充填する
ことができることによつて、信頼性の高い半導体
装置の製造を容易に達成するものである。 In addition, when applying the brazing material, by immersing the whole or a part of the package board in a molten brazing material bath, the capillary phenomenon in the through hole can be used to apply the soldering material near the opening of the through hole or through the area including the vicinity of the opening. By being able to fill the entire hole with the brazing material, it is possible to easily manufacture a highly reliable semiconductor device.
〔実施例 １〕
第１図は、本発明による実施例１であるピング
リツドアレイ型半導体装置を、そのほぼ中心を通
る面における断面図で示したものである。[Embodiment 1] FIG. 1 is a sectional view of a pin grid array type semiconductor device according to Embodiment 1 of the present invention taken along a plane passing approximately through the center thereof.
本実施例１の半導体装置は、そのパツケージ基
板１が、配線として銅等のメタライズ２が載設さ
れているエポキシ樹脂で形成されてなるものであ
り、該基板上には、ほぼ中央部にキヤビテイ３が
形成されるようにアルミニウムあるいはエポキシ
樹脂からなるダム４が取り付けられており、該ダ
ム４の周囲の基板１には外部端子である42アロイ
等からなるピン５がメタライズの一部と電気的に
接続した状態で植設されているものである。 In the semiconductor device of Example 1, a package substrate 1 is formed of epoxy resin on which metallization 2 such as copper is mounted as wiring, and a cavity is provided on the substrate approximately in the center. A dam 4 made of aluminum or epoxy resin is attached so that a pin 3 is formed, and a pin 5 made of 42 alloy, etc., which is an external terminal, is connected to a part of the metallization on the substrate 1 around the dam 4. It is planted in a state where it is connected to the
そして、ダム４により形成されているキヤビテ
イ３内にはペレツト６が、該ペレツト６のボンデ
イングパツドと該キヤビテイ３内のメタライズと
を金等のワイヤ７で電気的に接続した状態で搭載
されている。さらにペレツト６とワイヤ７とをシ
リコーンゲル８で封じ込んだ後ダム４上面に接着
剤９でアルミニウム製あるいはエポキシ樹脂製キ
ヤツプ１０を取り付けることにより、キヤビテイ
４を封止してなるものである。 A pellet 6 is mounted in the cavity 3 formed by the dam 4 with the bonding pad of the pellet 6 and the metallization in the cavity 3 electrically connected by a wire 7 made of gold or the like. There is. Further, the pellet 6 and the wire 7 are sealed with a silicone gel 8, and then a cap 10 made of aluminum or epoxy resin is attached to the upper surface of the dam 4 with an adhesive 9, thereby sealing the cavity 4.
第２図は本実施例１の半導体装置のパツケージ
基板１の所定位置に形成されている電気的接続用
のスルーホール１１を、そのほぼ中心を通る面に
おける断面図で示すものである。 FIG. 2 is a sectional view of a through hole 11 for electrical connection formed at a predetermined position in the package substrate 1 of the semiconductor device of the first embodiment, taken along a plane passing approximately through the center thereof.
前記スルーホール１１は基板１上面のメタライ
ズ２から、該スルーホール壁面に被着形成されて
いる金等の金属層１２を介して基板１裏面のメタ
ライズ２ａへ電気的導通を延長するために形成さ
れているものである。通常は、金等をメタライズ
２および２ａと接触するようにめつき等でスルー
ホール１１壁面に被着することにより、金属層１
２を形成することで、または必要に応じてスルー
ホール１１開口部を樹脂で塞いで内部を保護する
のみで前記導通延長は達成されているものであ
る。 The through hole 11 is formed to extend electrical continuity from the metallization 2 on the top surface of the substrate 1 to the metallization 2a on the back surface of the substrate 1 via a metal layer 12 such as gold deposited on the wall surface of the through hole. It is something that Usually, the metal layer 11 is coated with gold or the like by plating or the like so as to be in contact with the metallization 2 and 2a.
The extension of the conduction can be achieved by forming the through-hole 2 or by simply protecting the inside by blocking the opening of the through-hole 11 with resin as necessary.
しかし、一般にスルーホール１１壁面にめつき
等で被着されている金属層は余り厚く形成できな
いうえに物性の異なる樹脂表面に被着されている
ため熱衝撃により、または温度サイクルにより切
断等され導通不良を来すという問題があり、それ
も開口部におけるメタライズ２等と該金属層１２
との接続箇所で特に切断等が起こり易ことが見い
出された。 However, in general, the metal layer that is attached to the wall surface of the through hole 11 by plating or the like cannot be formed very thick, and because it is attached to a resin surface with different physical properties, it may be cut due to thermal shock or temperature cycles, resulting in non-conductivity. There is a problem that the metallization 2 etc. and the metal layer 12 in the opening may cause defects.
It has been found that disconnections are particularly likely to occur at the connection points.
本実施例１の半導体装置における基板に形成さ
れている電気的導通延長用のスルーホール１１
は、第２図に示すように半田１３で開口部の接続
箇所を十分に被覆され、かつ全体に半田１３が充
填された状態で形成されてなるものである。 Through hole 11 for extending electrical continuity formed in the substrate in the semiconductor device of Example 1
As shown in FIG. 2, the connecting portion of the opening is sufficiently covered with solder 13, and the entire portion is filled with solder 13.
このようにスルーホールに半田１３を充填せし
めることにより、切断し易い接続箇所を十分に補
強すると同時に、スルーホール内の壁面に形成さ
れてる金属層をも補強することができるものであ
る。 By filling the through-hole with the solder 13 in this manner, it is possible to sufficiently reinforce the connection points that are easily cut, and at the same time, it is possible to reinforce the metal layer formed on the wall surface inside the through-hole.
ちなみに、−55℃に20分間、常温に10分間、さ
らに150℃に20分間の条件におく温度サイクル試
験では、半田被着しないものが約100サイクルで
あつたものが被着することにより約10000サイク
ルまで耐えうる性能を付与することができた。 By the way, in a temperature cycle test under the conditions of -55℃ for 20 minutes, room temperature for 10 minutes, and 150℃ for 20 minutes, it took about 100 cycles without solder adhesion, but after about 10,000 cycles with solder adhesion. We were able to provide performance that can withstand cycles.
なお、前記の如くスルーホール１１に半田１３
を被着する方法としては、基板１の上部または下
部を単に熔融半田浴に浸漬するだけでよい。すな
わち毛管現象の作用でスルーホール１１全体に半
田がすい上げられて及んで行き、かつ半田の表面
張力の作用で第２図に示す如き端部形状で半田を
被着することができるものである。 In addition, as mentioned above, the solder 13 is applied to the through hole 11.
As a method for depositing the solder, it is sufficient to simply immerse the upper or lower part of the substrate 1 in a molten solder bath. In other words, the solder is swept up and spread over the entire through hole 11 by the action of capillarity, and the solder can be applied to the end shape as shown in FIG. 2 by the action of the surface tension of the solder. .
第３図ａは、本実施例の半導体装置の基板１に
形成されている他のスルーホール１１を前記第２
図に示すスルーホールと同様に断面図で示したも
のである。 FIG. 3a shows another through hole 11 formed in the substrate 1 of the semiconductor device of this embodiment.
It is shown in a cross-sectional view similar to the through hole shown in the figure.
本図に示すスルーホール１１には、実装基板の
配線と電気的に導通をとるためのピン５が挿入さ
れているものであり、該ピン５は挿入部に形成さ
れている連続した形状で、または１または２以上
の部分的に設けられている突出部５ａがスルーホ
ール１１壁面により押え付けられる状態で固定さ
れていながら、なおピン５とスルーホール１１の
壁面との間には十分な空隙が確保されているもの
である。 A pin 5 is inserted into the through hole 11 shown in this figure to establish electrical continuity with the wiring on the mounting board, and the pin 5 has a continuous shape formed in the insertion part. Or, even though one or more partially provided protrusions 5a are fixed in a pressed state by the wall surface of the through hole 11, there is still a sufficient gap between the pin 5 and the wall surface of the through hole 11. It is guaranteed.
それ故、前記第２図に示したスルーホール同
様、基板上部または下部を熔融半田浴に浸漬する
のみで容易に図示する形状で半田をスルーホール
１１に被着することができるものである。この場
合、ピン５に錫等を被着し、半田にぬれ易くして
おくとさらによい。 Therefore, like the through-hole shown in FIG. 2, solder can be easily applied to the through-hole 11 in the shape shown by simply immersing the upper or lower part of the substrate in a molten solder bath. In this case, it is better to coat the pin 5 with tin or the like so that it can be easily wetted by solder.
第３図の如き形状で半田を被着することによ
り、前記第２図のスルーホールと同様に信頼性の
向上を達成できる以外に、ピン５を基板１に強固
に固定することもできるものである。 By applying solder in the shape shown in FIG. 3, not only can the reliability be improved as in the case of the through-hole shown in FIG. 2, but also the pin 5 can be firmly fixed to the substrate 1. be.
なお、前記の如きスルーホール１１の壁面と一
定の空隙を確保した上で半田をすい上げてスルー
ホールを埋め、気密を確保するとともにピン５を
強く固定することができる例としては、横断面が
丸形状のスルーホールに、第３図ｂまたはｃに上
面図で示す形状のピン５を使用する場合、横断面
が丸形状の一様な太さで形成されているピン５に
対し、上面図が第３図ｄまたはｅで形成されてな
るスルーホールを適用する場合を、あげることが
できる。 In addition, as an example in which the pin 5 can be firmly fixed while ensuring airtightness by filling the through hole by scooping up solder after securing a certain gap with the wall surface of the through hole 11 as described above, the cross section is When using a pin 5 having the shape shown in the top view in FIG. A case can be mentioned in which a through hole formed as shown in FIG. 3 d or e is applied.
第３図ｂに示すピン５は本発明における最も好
ましい形態であり、ピンの外周部５ｂより外側に
スルーホール１１の径にほぼ一致する位置まで延
在せられた４つの突出部５ａがピンの最上端に形
成されてなるものである。同図ａに示すピン５で
は、突出部５ａが最上端とスルーホール下端付近
の２ケ所に設けられているものである。 The pin 5 shown in FIG. 3b is the most preferred form of the present invention, and the pin has four protrusions 5a extending outward from the outer circumferential portion 5b to a position that approximately corresponds to the diameter of the through hole 11. It is formed at the top end. In the pin 5 shown in FIG. 5A, protrusions 5a are provided at two locations: at the top end and near the bottom end of the through hole.
この２ケ所に設けられた突出部がスルーホール
内に位置して固定されるために、ピンの傾きが生
じにくく、しかも充分それら突出部間に半田が十
二分に充填することから、それぞれのピンは鉛直
方向を維持して樹脂基板に半田固定されることに
なり、ピン間隔の狭いピングリツドアレイ型半導
体装置に適している。 Since the protrusions provided at these two locations are located and fixed within the through-hole, the pin is less likely to tilt, and since the solder is sufficiently filled between the protrusions, each The pins are soldered to the resin substrate while maintaining their vertical orientation, and are suitable for pin grid array type semiconductor devices with narrow pin spacing.
前記形状のピン５を、横断面丸形状のスルーホ
ール１１に挿入して固定した場合であつても十分
な空隙を確保できるものである。なお、半田にぬ
れ易くするためにピン５を薄い錫等を予め被着し
たものとしてもよい（以下の例でま同様である
が、説明を省略する）。 「第３図ｃに示すピン
は、同図ｂと突出部５ａの形状のみ異なるもので
ある。第３図ｃに示すピンは、突出部５ａが２方
のみに形成された形状であるため、リードを押し
潰すだけで簡単に作ることができる利点がある。 Even when the pin 5 having the above shape is inserted and fixed into the through hole 11 having a round cross section, a sufficient gap can be secured. Note that the pin 5 may be coated with thin tin or the like in advance in order to be easily wetted by solder (the same applies to the following examples, but the explanation will be omitted). "The pin shown in FIG. 3c differs from that shown in FIG. 3b only in the shape of the protrusion 5a.The pin shown in FIG. It has the advantage that it can be easily made by simply crushing the reed.
第３図ｄは、四角形状のスルーホール１１を上
面図で示したものである。図中、二点鎖線で示し
た円形状のものはピン５であり、このようにピン
５のスルーホール挿入部が一様な太さの丸形状で
形成されていてもスルーホール１１の壁面にの間
に空隙１４が確保することができるため、前記ｂ
またはｃ図のピンを使用した場合と同様の目的を
達成できるものである。 FIG. 3d shows a top view of the square-shaped through hole 11. In the figure, the circular shape indicated by the two-dot chain line is the pin 5, and even if the through-hole insertion part of the pin 5 is formed in a round shape with a uniform thickness, it will not fit on the wall surface of the through-hole 11. Since the air gap 14 can be secured between the
Alternatively, the same purpose as in the case of using the pin shown in Fig. c can be achieved.
第３図ｅは、前記ｄ図に示すスルーホールと同
様の目的に使用しうるスルーホールを同じく上面
図で示したものである。 FIG. 3e shows a top view of a through hole which can be used for the same purpose as the through hole shown in FIG. 3d.
本図ｅに示すスルーホール１１は、前記ｄ図に
示すスルーホールより大きな空隙１４が確保でき
るような形状で形成されていることに特徴がある
ものである。このように空隙１４を拡大すること
により、半田がスルーホール１１内を移動する速
さを増大せしめることができることより、製造時
間の短縮をも図ることができるものである。 The through hole 11 shown in Fig. e is characterized in that it is formed in a shape that allows a larger gap 14 to be secured than the through hole shown in Fig. d. By enlarging the void 14 in this manner, the speed at which the solder moves within the through-hole 11 can be increased, and the manufacturing time can also be shortened.
さらに、半田を空隙１４を利用して吸い上げる
ことにより、ピン５の取付け強度を向上し、かつ
パツケージの気密性を保つことができる手段とし
て、第３図Ｆ〜Ｊに示す形状を上げることができ
る。 Furthermore, as a means for improving the mounting strength of the pin 5 and maintaining the airtightness of the package by sucking up the solder using the void 14, the shapes shown in FIG. 3 F to J can be used. .
第３図Ｆ，ＧおよびＨは、夫々、断面形状が円
形状のスルーホール１１に断面形状が四角形、六
角形および三角形のピン５を挿入した例である。
ピン５は四角柱、六角柱、三角柱であるが、第３
図ｂ又はｃに示したような穴起５ａを付加しても
良い。また、図示以外の多角形状であつてもよ
い。 FIGS. 3F, G, and H show examples in which pins 5 having square, hexagonal, and triangular cross-sections are inserted into through-holes 11 having circular cross-sections, respectively.
Pin 5 is a square prism, hexagonal prism, or triangular prism, but the third
A hole raised 5a as shown in FIG. b or c may be added. Further, it may have a polygonal shape other than that shown.
第３図ＩおよびＪはピン５にピンストツパ用カ
シメ５ａと基板製造時ピン抜けを防止しピンを基
板に仮止めしておくためのカシメ５ｃとを用いた
例である。カシメ５ａはスルーホールより大きけ
れば形状は先述した例の他種々変更できる。カシ
メ５ｃはピン５を押し潰すだけで作ることができ
る。 FIGS. 3I and 3J are examples in which the pin 5 is provided with a pin stopper swage 5a and a swage 5c for temporarily fixing the pin to the board to prevent the pin from coming off during board manufacture. As long as the caulking 5a is larger than the through hole, the shape can be changed in various ways other than the above-mentioned example. The caulking 5c can be made by simply crushing the pin 5.
〔実施例 ２〕
第４図は、本発明による実施例２である半導体
装置製造用の器具をその使用態様をも含めた側面
図で示したものである。本実施例２に示す器具は
本発明による半導体装置を製造するに使用して有
効な器具である。また、使用態様の理解容易のた
め、半導体装置としてはキヤツプ封止前における
前記実施例１の半導体装置を、それも断面図のま
まで示してある。[Embodiment 2] FIG. 4 is a side view showing a device for manufacturing a semiconductor device according to Embodiment 2 of the present invention, including the manner in which it is used. The instrument shown in Example 2 is an effective instrument for manufacturing the semiconductor device according to the present invention. Further, in order to facilitate understanding of the manner of use, the semiconductor device of the first embodiment is shown as a cross-sectional view before the cap is sealed.
本実施例２の器具１５は、途中交差し、その交
差部において摺動可能な状態で鋲１６で結合され
ており、かつ一方の先端には四角または丸等の形
状の密閉用皿１７が、他方の先端には基板支持部
１８が設けられている一対のアーム１９で形成さ
れてなるもので、さらに各アーム他端近傍にはば
ね２０が、密閉用皿１７と支持部１８とを近接せ
しめるよう付勢するように取り付けられてなるも
のである。 The instruments 15 of the second embodiment intersect in the middle, and are slidably connected with studs 16 at the intersection, and a sealing plate 17 in the shape of a square or a circle is provided at one end. It is formed of a pair of arms 19 each having a substrate support part 18 at the other end, and a spring 20 near the other end of each arm brings the sealing plate 17 and the support part 18 close to each other. It is attached in such a way that it is biased.
本実施例２の器具は、第４図に示す如く、半導
体装置のペレツト取付部およびメタライズ２の一
部を含むキヤビテイ３を密封して外部からの異物
侵入を防ぎ、内部を保護するための器具である。
すなわち、密封用皿１７の平坦面をダム４の上端
面に載置した状態で支持部１８を基板１の裏面に
当てがい、ばね２１の力で強く押さえつけること
により該皿１７の平坦面とダム４の上端面とを密
着させることができるものである。なお、その際
に皿１８の平坦面とダム４の上端面との間にシリ
コングリース等を介在させることにより、さらに
密着性を向上させることも容易に行なうことがで
きる。 As shown in FIG. 4, the device of the second embodiment is a device for sealing the cavity 3, which includes the pellet attachment part of the semiconductor device and a part of the metallization 2, to prevent foreign matter from entering from the outside, and to protect the inside. It is.
That is, with the flat surface of the sealing plate 17 placed on the upper end surface of the dam 4, the supporting part 18 is applied to the back surface of the substrate 1, and by pressing strongly with the force of the spring 21, the flat surface of the sealing plate 17 and the dam are connected. The upper end surface of No. 4 can be brought into close contact with the upper end surface of No. 4. At this time, by interposing silicone grease or the like between the flat surface of the plate 18 and the upper end surface of the dam 4, the adhesion can be easily further improved.
以上説明した如く、第４図に示すように半導体
装置のキヤビテイ３内を密封することにより、前
記実施例１で示したようなスルーホールの半田被
着処理を行なう場合は、半導体装置を器具１５で
挟持した状態のまま、半田フラツクス液中に浸漬
することができ、さらにそのままの状態で基板上
部または下部を熔融半田浴に浸漬することができ
るものである。それ故、キヤビテイ３内にペレツ
ト６を取り付け、さらにワイヤボンデイング等を
行なつた後であつてもペレツト等をフラツクスま
たは半田で汚すことなく、前記処理を容易に行な
うことが可能となる。 As explained above, by sealing the inside of the cavity 3 of the semiconductor device as shown in FIG. The substrate can be immersed in a solder flux liquid while being held between the substrates, and the upper or lower portion of the substrate can be immersed in a molten solder bath. Therefore, even after the pellet 6 is installed in the cavity 3 and further wire bonding or the like is performed, the above processing can be easily carried out without contaminating the pellet etc. with flux or solder.
なお、本実施例２の器具はステンレス等の半田
が付着されにくい材料であれば如何なるもので形
成したものであつてもよい。 The device of the second embodiment may be made of any material such as stainless steel to which solder is difficult to adhere.
また、皿１７の平坦面にはフッ素樹脂、シリコ
ーン樹脂等を被着して密着性を向上させることが
できる。 Further, the flat surface of the plate 17 can be coated with fluororesin, silicone resin, etc. to improve adhesion.
(1) 基板が樹脂で形成されてなるピングリツドア
レイ型半導体装置において、基板上面または裏
面に形成されているメタライズと電気的に接続
している金属層が被着されているスルーホール
について、少なくともメタライズと金属層との
接続部にろう材を被着することにより、該接続
部を補強することができるので、該接続部にお
ける金属層の切断等を防止することができる。
(1) In a pin grid array type semiconductor device whose substrate is made of resin, through-holes are coated with metal layers that are electrically connected to metallization formed on the top or bottom surface of the substrate. By applying a brazing material to at least the connection portion between the metallized layer and the metal layer, the connection portion can be reinforced, so that cutting of the metal layer at the connection portion can be prevented.
(2) ろう材をスルーホール全体に充填せしめ、か
つ前記接続部をも該ろう材で被着することによ
り、スルーホール内の壁面の切断等をも防止で
きる。(2) By filling the entire through-hole with the brazing material and also covering the connection portion with the brazing material, it is possible to prevent the walls within the through-hole from being cut.
(3) 前記(1)および(2)により温度サイクル等の熱衝
撃に対して信頼性の高い半導体装置を提供でき
る。(3) According to (1) and (2) above, it is possible to provide a semiconductor device that is highly reliable against thermal shocks such as temperature cycles.
(4) 外部端子固定部であるスルーホールに、前記
(2)に示すようにろう材を被着することにより、
外部端子であるピンをも強固に固定することが
できる。(4) Insert the above-mentioned into the through hole which is the external terminal fixing part.
By applying brazing metal as shown in (2),
Pins, which are external terminals, can also be firmly fixed.
(5) 基板スルーホールに、前記(2)の如くろう材を
被着する場合、基板上部または下部を熔融ろう
材浴に浸漬することにより、毛管現象及び表面
張力の作用で容易に被着することができる。(5) When applying a brazing material to the substrate through-hole as described in (2) above, by immersing the upper or lower part of the substrate in a molten brazing material bath, the soldering material can be easily adhered by capillary action and surface tension. be able to.
(7) スルーホールが外部端子固定部であつても、
スルーホール壁面と外部端子との間に空隙を設
けておくことにより、前記(5)と同様にろう材を
被着することができる。(7) Even if the through hole is an external terminal fixing part,
By providing a gap between the through-hole wall surface and the external terminal, the brazing material can be applied in the same manner as in (5) above.
(8) 横断面がほぼ丸形状の外部端子のスルーホー
ル挿入部にほぼ、スルーホールの壁面に接触す
る長さの突出部を設けることにより、外部端子
を機械的に固定した上で前記(7)を容易に実施す
ることができる。(8) By providing a protrusion long enough to almost contact the wall surface of the through hole in the through hole insertion portion of an external terminal having a substantially round cross section, the external terminal can be mechanically fixed and ) can be easily implemented.
(9) 横断面がほぼ丸形状の一様な太さで少なくと
もスルーホール挿入部が形成されている外部端
子を、横断面多角形状のスルーホールに植設す
ることにより、前記(8)と同様の効果が得られ
る。(9) Similar to (8) above, by implanting an external terminal with a substantially round cross section of uniform thickness and at least a through hole insertion portion formed into a through hole with a polygonal cross section. The effect of this can be obtained.
(10) 一方の先端に密封用皿を有し、他方の先端に
支持部を有し、かつ互いに接近するように構成
されている一対のアームで形成されてなる器具
を用い、該密封用皿で基板上面のペレツト取付
部およびメタライズの一部を密封保護すること
により、ペレツト取付部等をフラツクスまたは
ろう材で汚すことなく容易に前記(5)を行なうこ
とができる。(10) Using a device formed of a pair of arms having a sealing plate at one end, a support portion at the other end, and configured to approach each other, the sealing plate By sealing and protecting the pellet mounting portion and part of the metallization on the upper surface of the substrate, the above (5) can be easily carried out without staining the pellet mounting portion etc. with flux or brazing material.
(11) 密封用皿が平坦面で形成されている器具を
用い、基板上面にキヤビテイを形成するように
取り付けられているダムの上端面に該皿の平坦
面を載置密着することにより、キヤビテイ内に
ペレツトを取り付ける等の組立を終了し、キヤ
ツプ封止前の半導体装置であつても、ペレツト
等をフラツクスまたはろう材で汚すことなく容
易に前記(5)を行うことができる。(11) Using a device whose sealing plate has a flat surface, the flat surface of the plate is placed and tightly attached to the upper end surface of a dam attached to form a cavity on the upper surface of the substrate, thereby sealing the cavity. Even if the semiconductor device has been assembled, such as attaching a pellet inside, and has not yet been sealed in a cap, the above (5) can be easily carried out without contaminating the pellet etc. with flux or brazing material.
(12) 器具のアームを弾性材料で形成することに
より、連続した形状で形成できるので安価に該
治具を製造することができる。(12) By forming the arms of the instrument from an elastic material, the arms can be formed in a continuous shape, so the jig can be manufactured at low cost.
(13) 器具のアームを、ばねを用いて互いに接近
するよいに付勢することにより、種々の材料で
該器具を製造することができる。(13) By biasing the arms of the instrument toward each other using springs, the instrument can be manufactured from a variety of materials.
(14) 密封用皿の密着面にシリコーン等の樹脂を
被着することにより、密閉性を向上させること
ができる。(14) Sealing performance can be improved by applying a resin such as silicone to the contact surface of the sealing plate.
(15) ろう機して半田を使用することにより、安
価な半導体装置を提供することができる。(15) By using a solder and soldering, it is possible to provide an inexpensive semiconductor device.
以上本発明者によつてなされた発明を実施例に
基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しな
い範囲で種々変更可能であることはいうまでもな
い。 Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the Examples described above, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.
たとえば、基板１の材料としてはガラスエポキ
シ板等他の樹脂板を用いることもできる。ピング
リツドアレイ型半導体装置としては、ダム周囲の
基板面が露出した状態のものを示したが、メタラ
イズ等は半田レジスト等の樹脂の保護膜を該基板
上面に被着してもよいことは言うまでもなく、ダ
ムの巾を該基板側端部まで拡表して基板上面全体
を覆う形状にしてもよいことは同様である。 For example, as the material for the substrate 1, other resin plates such as a glass epoxy plate can also be used. Although the pin grid array type semiconductor device is shown with the substrate surface around the dam exposed, it is also possible to apply a protective film of resin such as solder resist to the top surface of the substrate for metallization, etc. Needless to say, the width of the dam may be extended to the edge of the substrate to cover the entire upper surface of the substrate.
スルーホールに半田を被着するものとしては、
スルーホール全体に半田を充填したものについて
示したが、スルーホール開口部付近のメタライズ
と金属層の接続箇所のみに被着したものであつて
もよいことは言うまでもない。 For applying solder to through holes,
Although the entire through hole is filled with solder, it goes without saying that the solder may be applied only to the connection portion between the metallization and the metal layer near the opening of the through hole.
また、スルーホールに固定されているピンは前
記実施例で示した、２箇所の突出部で固定される
ものに限るものでなく、１箇所、３箇所以上の突
出部を有するかまたは連続した形状であつてもよ
い。 Further, the pin fixed to the through hole is not limited to the pin fixed with two protrusions as shown in the above embodiment, but may have one protrusion, three or more protrusions, or have a continuous shape. It may be.
さらに、スルーホールの形状についても前記実
施例に示すものに限るものでない。 Furthermore, the shape of the through hole is not limited to that shown in the above embodiment.
なお、前記実施例においては、半田を使用する
場合についてのみ説明したが、他のろう材をも使
用できるものである。 In the above embodiments, only the case where solder is used has been described, but other brazing materials can also be used.
第１図は、本発明による実施例１である半導体
装置を示す断面図、第２図は、本実施例１の半導
体装置の基板に形成されているスルーホールを示
す断面図、第３図ａは、本実施例１の半導体装置
の基板に形成されている外部端子固定用の他のス
ルーホールを示す断面図、第３図ｂは、外部端子
として前記基板に形成されているスルーホールに
固定されるピンを示す上面図、第３図Ｃは、他の
ピンを示す上面図、第３図ｄは、前記基板に形成
されている外部端子固定用のスルーホールを示す
上面図、第３図ｅは、他のスルーホールを示す上
面図、第３図ｆ〜ｊは他のピンを示す図、第４図
は、本発明による実施例２であるマスク治具を、
使用状態で示す側面図である。
１……基板、２，２ａ……メタライズ、３……
キヤビテイ、４……ダム、５……ピン、５ａ……
突出部、５ｂ……外周部、６……ペレツト、７…
…ワイヤ、８……シリコーンゲル、９……接着
剤、１０……キヤツプ、１１……スルーホール、
１２……金属層、１３……半田、１４……空隙、
１５……器具、１６……鋲、１７……皿、１８…
…支持部、１９……アーム、２０……ばね。
FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a sectional view showing a through hole formed in the substrate of the semiconductor device of the first embodiment, and FIG. 3 is a sectional view showing another through hole for fixing an external terminal formed in the substrate of the semiconductor device of Example 1, and FIG. FIG. 3C is a top view showing other pins; FIG. 3D is a top view showing through holes for fixing external terminals formed in the board; FIG. e is a top view showing other through holes, FIGS. 3 f to j are views showing other pins, and FIG.
FIG. 3 is a side view showing the device in use. 1... Substrate, 2, 2a... Metallization, 3...
Cavity, 4...Dam, 5...Pin, 5a...
Projection, 5b... Outer circumference, 6... Pellet, 7...
... wire, 8 ... silicone gel, 9 ... adhesive, 10 ... cap, 11 ... through hole,
12...Metal layer, 13...Solder, 14...Void,
15... utensil, 16... rivet, 17... plate, 18...
...Support part, 19...Arm, 20...Spring.
Claims (1)
イズと電気的に接続されている金属層が壁面に被
着されてなる複数のスルーホールを備えた樹脂基
板に対して、それらスルーホールにピンを挿入
し、半田により固定するピングリツドアレイ型半
導体装置の製造方法であつて、前記スルーホール
は横断面丸形状を成し、前記ピンはピンの外周部
より外側に前記スルーホールの径にほぼ一致する
位置までに延在せられた４つの突出部がそのスル
ーホール内であつてそのスルーホールの最上端と
下端付近の２ケ所に設けられて成り、前記スルー
ホール内部に前記２ケ所に設けられた突出部が位
置するように前記ピンを前記スルーホールに挿入
し、しかる後前記ピンが固定された樹脂基板を溶
融半田浴に浸漬することを特徴とするピングリツ
ドアレイ型半導体装置の製造方法。1. Insert pins into the through-holes of a resin board with multiple through-holes made by adhering to the wall a metal layer that is electrically connected to the metallization formed on the top or bottom of the board. , a method for manufacturing a pin grid array type semiconductor device fixed by soldering, wherein the through hole has a round cross section, and the pin has a diameter approximately equal to the diameter of the through hole outside the outer periphery of the pin. four protrusions extending up to the position are provided at two locations within the through hole near the top and bottom ends of the through hole; A method for manufacturing a pin grid array type semiconductor device, comprising inserting the pin into the through hole so that the protrusion is located, and then immersing the resin substrate to which the pin is fixed in a molten solder bath.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59096535A JPS60241244A (en) | 1984-05-16 | 1984-05-16 | Semiconductor device, manufacture thereof, and implement to manufacture therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59096535A JPS60241244A (en) | 1984-05-16 | 1984-05-16 | Semiconductor device, manufacture thereof, and implement to manufacture therefor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60241244A JPS60241244A (en) | 1985-11-30 |
| JPH0478015B2 true JPH0478015B2 (en) | 1992-12-10 |
Family
ID=14167813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59096535A Granted JPS60241244A (en) | 1984-05-16 | 1984-05-16 | Semiconductor device, manufacture thereof, and implement to manufacture therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60241244A (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6292352A (en) * | 1985-10-17 | 1987-04-27 | Tanaka Denshi Kogyo Kk | Lead pin for chip-on-board |
| JPH0777253B2 (en) * | 1986-03-20 | 1995-08-16 | イビデン株式会社 | Semiconductor mounting board |
| JPH0766953B2 (en) * | 1986-09-11 | 1995-07-19 | イビデン株式会社 | Semiconductor mounting board |
| JPH0815199B2 (en) * | 1986-12-22 | 1996-02-14 | イビデン株式会社 | Method for manufacturing semiconductor mounting substrate and jig plate used therefor |
| JPH01117084A (en) * | 1987-10-29 | 1989-05-09 | Nec Corp | Plastic pin grid array package |
| US5036431A (en) * | 1988-03-03 | 1991-07-30 | Ibiden Co., Ltd. | Package for surface mounted components |
| US5592025A (en) * | 1992-08-06 | 1997-01-07 | Motorola, Inc. | Pad array semiconductor device |
| KR20030004644A (en) * | 2001-07-06 | 2003-01-15 | 홍성결 | The pressed lead pin for pin grid array package |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS48101878A (en) * | 1972-04-03 | 1973-12-21 | ||
| JPS50121258A (en) * | 1974-03-08 | 1975-09-23 | ||
| JPS5256366A (en) * | 1975-11-04 | 1977-05-09 | Sony Corp | Method of conducting bothhside printed substrate |
| JPS5810848A (en) * | 1981-07-14 | 1983-01-21 | Toshiba Corp | Lead pin for hybrid integrated circuit |
| JPS58159355A (en) * | 1982-03-17 | 1983-09-21 | Nec Corp | Manufacture of semiconductor device |
| JPS5982757A (en) * | 1982-11-04 | 1984-05-12 | Toshiba Corp | Stem for semiconductor and manufacture thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS509759U (en) * | 1973-05-24 | 1975-01-31 |
-
1984
- 1984-05-16 JP JP59096535A patent/JPS60241244A/en active Granted
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS48101878A (en) * | 1972-04-03 | 1973-12-21 | ||
| JPS50121258A (en) * | 1974-03-08 | 1975-09-23 | ||
| JPS5256366A (en) * | 1975-11-04 | 1977-05-09 | Sony Corp | Method of conducting bothhside printed substrate |
| JPS5810848A (en) * | 1981-07-14 | 1983-01-21 | Toshiba Corp | Lead pin for hybrid integrated circuit |
| JPS58159355A (en) * | 1982-03-17 | 1983-09-21 | Nec Corp | Manufacture of semiconductor device |
| JPS5982757A (en) * | 1982-11-04 | 1984-05-12 | Toshiba Corp | Stem for semiconductor and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60241244A (en) | 1985-11-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5389739A (en) | Electronic device packaging assembly | |
| US4788626A (en) | Power semiconductor module | |
| US4640436A (en) | Hermetic sealing cover and a method of producing the same | |
| CN112823574B (en) | Substrate housing frame | |
| KR19980058198A (en) | Bottom Lead Semiconductor Package | |
| US8508036B2 (en) | Ultra-thin near-hermetic package based on rainier | |
| JPH0478015B2 (en) | ||
| EP0645812A1 (en) | Resin-sealed semiconductor device | |
| US4046442A (en) | Pluggable semiconductor device package | |
| US3730969A (en) | Electronic device package | |
| JPS59207646A (en) | Semiconductor device and lead frame | |
| JP3196540B2 (en) | Semiconductor device | |
| JP3627633B2 (en) | Semiconductor device | |
| JPS61242053A (en) | Semiconductor device | |
| JPH10189792A (en) | Semiconductor package | |
| JPH0341473Y2 (en) | ||
| JP2001203320A (en) | Power semiconductor device | |
| JPS6236287Y2 (en) | ||
| JPH08204048A (en) | Sealing structure of semiconductor chip | |
| JP2582801B2 (en) | Semiconductor package soldering method | |
| US20020190363A1 (en) | Semiconductor device package and method of die attach | |
| JPH04239160A (en) | Manufacture of resin-sealed type electronic component | |
| JPS63299254A (en) | Manufacture of hermetic seal type semiconductor device | |
| JPH03109757A (en) | Resin-sealed semiconductor device | |
| JPH0331083Y2 (en) |