JPH0476928A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0476928A JPH0476928A JP2191212A JP19121290A JPH0476928A JP H0476928 A JPH0476928 A JP H0476928A JP 2191212 A JP2191212 A JP 2191212A JP 19121290 A JP19121290 A JP 19121290A JP H0476928 A JPH0476928 A JP H0476928A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- lead
- semiconductor
- electrode
- electric field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000004020 conductor Substances 0.000 claims abstract description 10
- 239000010409 thin film Substances 0.000 claims abstract description 8
- 230000005684 electric field Effects 0.000 abstract description 15
- 239000011347 resin Substances 0.000 abstract description 15
- 229920005989 resin Polymers 0.000 abstract description 15
- 239000010408 film Substances 0.000 abstract description 6
- 239000002245 particle Substances 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 3
- 230000007774 longterm Effects 0.000 abstract description 2
- 238000000605 extraction Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000593 degrading effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は半導体装置の電極構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an electrode structure of a semiconductor device.
［従来の技術］
従来の半導体装置の電極構造は第２図に示す様に、入出
力電極から導電体により外部に引き出されるが（以降
引出し導電体をリードと称する）導電体と半導体基板は
半導体上の絶縁膜及び樹脂を介して対面している構造に
なっていた。[Prior Art] As shown in Fig. 2, the electrode structure of a conventional semiconductor device is such that the input/output electrodes are led out by conductors (hereinafter referred to as
The conductor (the lead conductor is called a lead) and the semiconductor substrate face each other with an insulating film on the semiconductor and a resin interposed therebetween.
［発明が解決しようとする課題］
しかし、前述の従来技術では半導体基板とリードとの間
に電界がかかると、樹脂内に水分が含まれた場合は樹脂
内の導電性物質が電界によって移動し、経時的に半導体
基板もしくはリードを劣化させ半導体装置の信頼性を著
しく低下させるという問題点を有する。[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, when an electric field is applied between the semiconductor substrate and the leads, if moisture is contained in the resin, the conductive substance in the resin moves due to the electric field. However, there is a problem in that the semiconductor substrate or leads deteriorate over time, significantly reducing the reliability of the semiconductor device.
そこで本発明はこのような問題点を解決するもので、そ
の目的とするところは経時変化による劣化のない半導体
装置を提供するところにある。The present invention is intended to solve these problems, and its purpose is to provide a semiconductor device that does not deteriorate due to changes over time.
［課題を解決するための手段］
本発明の半導体装置は、信号もしくは電源の入出力電極
を複数有し、ワイヤー 棒状もしくは薄膜状の導電体に
よって外部に電位もしくは信号を入出力する電極構造に
おいて、ワイヤー 棒状もしくは薄膜状の前記導電体の
引出し部分と対向する半導体基板上に各々の電極と同電
位、同一信号の電極を設ける事を特徴とする。[Means for Solving the Problems] The semiconductor device of the present invention has an electrode structure that has a plurality of signal or power input/output electrodes and inputs/outputs a potential or signal to the outside through a wire, rod-shaped or thin film-shaped conductor. The present invention is characterized in that electrodes having the same potential and the same signal as each electrode are provided on the semiconductor substrate facing the lead-out portion of the conductor in the shape of a wire rod or thin film.
［作用］
半導体チップを実装する際、半導体チップの入出力電極
にワイヤーもしくは棒状のリードを用いて外部電極に接
続するが、リードを固定するため樹脂をかぶせる。半導
体基板は正もしくは負電位で一定であり、リードに半導
体基板と反対の電位がかかった場合はリードと半導体基
板間の電界がかかる。[Operation] When mounting a semiconductor chip, the input and output electrodes of the semiconductor chip are connected to external electrodes using wires or rod-shaped leads, and the leads are covered with resin to fix them. The semiconductor substrate has a constant positive or negative potential, and when a potential opposite to that of the semiconductor substrate is applied to the lead, an electric field is applied between the lead and the semiconductor substrate.
樹脂内には導電性粒子が存在し、樹脂に水分が含まれる
と電界により導電性粒子が移動する。半導体基板上の絶
縁膜にわずかにでも傷があれば電流が流れ、半導体装置
の機能を損なうまでに至る。Conductive particles exist within the resin, and when the resin contains moisture, the conductive particles move due to the electric field. If there is even the slightest flaw in the insulating film on the semiconductor substrate, current will flow and the functionality of the semiconductor device will be impaired.
リード下の半導体基板上に入出力電極と同電位の電極を
設ける事により樹脂に電界がかからなくなり電流は流れ
なくなる。By providing electrodes with the same potential as the input/output electrodes on the semiconductor substrate under the leads, no electric field is applied to the resin and no current flows.
［実施例コ
第１図は本発明を説明する一実施例であり、第１図（ａ
）は本半導体装置を上から見た図。第１図（ｂ）は第１
図（ａ）のＡ−Ａ ＝間の断面図である。半導体基板内
の信号及び電源は半導体上のＡＬ配線６を介して入出力
ＡＬ電極１に接続されている。さらに半導体基板上に３
２けられた導電性突起物２を介し棒状のｌノード５に接
続され、外部に電位もしくは信号を人出力する。リード
５の弓出し部分に対向してＡＬ電極３が半導体基板上に
形成されている。本実施例ではＡＬ電極１とＡＬ電極３
とは同一電極となっている。リード５を固定するため半
導体基板上に樹脂を流し封止する。[Example 1] Figure 1 is an example for explaining the present invention, and Figure 1 (a)
) is a top view of this semiconductor device. Figure 1(b) shows the first
It is a sectional view taken along line A-A in Figure (a). Signals and power within the semiconductor substrate are connected to input/output AL electrodes 1 via AL wiring 6 on the semiconductor. Furthermore, 3
It is connected to a rod-shaped l node 5 through a conductive protrusion 2, and outputs a potential or a signal to the outside. An AL electrode 3 is formed on a semiconductor substrate opposite the protruding portion of the lead 5. In this embodiment, AL electrode 1 and AL electrode 3
The same electrode is used. In order to fix the leads 5, resin is poured onto the semiconductor substrate for sealing.
半導体基板をＰ型とした場合、半導体基板は常に最も低
い電位となっており、入出力電極に高い電位がかかると
り−ド５と半導体基板間に電界がかかる。ワード５と半
導体基板の距離は突起物２の高さによって決まり十数ミ
クロン程度である。When the semiconductor substrate is of P type, the semiconductor substrate is always at the lowest potential, and an electric field is applied between the terminal 5, whose input/output electrodes have a high potential, and the semiconductor substrate. The distance between the word 5 and the semiconductor substrate is determined by the height of the protrusion 2 and is approximately 10-odd microns.
一般的に半導体上の絶縁膜に対し樹脂の方が不安定で、
樹脂に水分が含まれた場合、電界により樹脂内の導電粒
子が移動し、半導体基板上の絶縁膜にわずかでも導電性
があれば電流は流れ、長期的にリードもしくは半導体を
劣化させる。これはＮ型半導体基板でも同様である。Generally, resins are more unstable than insulating films on semiconductors,
When moisture is contained in the resin, conductive particles within the resin move due to the electric field, and if the insulating film on the semiconductor substrate is even slightly conductive, current will flow, degrading the lead or semiconductor over the long term. This also applies to N-type semiconductor substrates.
ここで入出力電極と同電位の電極３をリード５に対向し
て設けることによりリード５と半導体基板間に電界がか
からずリードもしくは半導体を劣化させることはなくな
る。By providing the electrode 3 having the same potential as the input/output electrode opposite the lead 5, no electric field is applied between the lead 5 and the semiconductor substrate, thereby preventing deterioration of the lead or the semiconductor.
第３図は本発明の別の実施例を示す半導体装置の断面図
である。入出力電極１はコンタクト７により電極８に電
気的に接続されている。電極８はポリシリコンもしくは
ＡＬで構成されており、リード５に対向してリードの引
出し方向に配されている。入出力電極にかかった電位に
よって発生した電界は電極８と半導体基板間にかかり、
リード５との間にはかからない。FIG. 3 is a sectional view of a semiconductor device showing another embodiment of the present invention. The input/output electrode 1 is electrically connected to an electrode 8 by a contact 7. The electrode 8 is made of polysilicon or AL, and is arranged facing the lead 5 in the direction in which the lead is drawn out. The electric field generated by the potential applied to the input and output electrodes is applied between the electrode 8 and the semiconductor substrate,
There is no distance between it and lead 5.
第４図は本発明の別の実施例を示す半導体装置の断面図
である。入出力電極１はコンタクト１０及び拡散１１に
より電極９に電気的に接続されている。電極９は半導体
基板とは逆極性の半導体で構成されており、リード５に
対向してリードの引出し方向に形成されている。入出力
電極にかかった電位によって発生した電界は電極９と半
導体基板間のジャンクションで吸収され、リード５との
間にはかからない。FIG. 4 is a sectional view of a semiconductor device showing another embodiment of the present invention. The input/output electrode 1 is electrically connected to the electrode 9 by a contact 10 and a diffusion 11. The electrode 9 is made of a semiconductor having a polarity opposite to that of the semiconductor substrate, and is formed facing the lead 5 in the direction in which the lead is drawn out. The electric field generated by the potential applied to the input/output electrodes is absorbed at the junction between the electrode 9 and the semiconductor substrate, and is not applied to the lead 5.
第５図はり−ド１２上に突起物を形成した場合の本発明
の別の実施例である。FIG. 5 is another embodiment of the present invention in which a protrusion is formed on the beam board 12.
第６図は導電性薄膜配線１４が形成された基板１３に半
導体をのせることにより、外部に電位もしくは信号を引
き出す場合の本発明の実施例である。薄膜配ｆｉ１４に
沿って電極３が対向してのびている。FIG. 6 shows an embodiment of the present invention in which a potential or signal is extracted to the outside by placing a semiconductor on a substrate 13 on which a conductive thin film wiring 14 is formed. Electrodes 3 extend along the thin film arrangement 14 to face each other.
［発明の効果］
以上述べたように本発明によれば、ワイヤー・棒状もし
くは薄膜状の導電体の引出し部分と対向する半導体基板
上に各々の電極と同電位・同一信号の電極を設ける事に
より、入出力電極に高電圧がかかった場合でも導電体の
引出し部分と半導体基板との間には電界はかからない。[Effects of the Invention] As described above, according to the present invention, by providing electrodes with the same potential and the same signal as each electrode on the semiconductor substrate facing the lead-out portion of the wire/rod-shaped or thin-film conductor. Even if a high voltage is applied to the input/output electrodes, no electric field is applied between the lead-out portion of the conductor and the semiconductor substrate.
仮に湿度によってリードと半導体基板間の樹脂が導電性
を示しても、リードもしくは半導体を劣化させることな
く耐湿性の優れた信頼性の高い半導体装置が可能となる
。Even if the resin between the leads and the semiconductor substrate exhibits conductivity due to humidity, a highly reliable semiconductor device with excellent moisture resistance can be achieved without deteriorating the leads or the semiconductor.
また電極の電界が緩和されるため微細半導体実装が可能
となる。またより高い電圧を扱う半導体装置が可能とな
る。Furthermore, since the electric field of the electrode is relaxed, fine semiconductor packaging becomes possible. Furthermore, it becomes possible to create a semiconductor device that can handle higher voltages.
第１図（ａ）（ｂ）は本発明の半導体装置の一実施例を
示す図であり、第１図（ａ）は平面図、第１図（ｂ）は
断面図である。
第２図（ａ）（ｂ）は従来の半導体装置を示す図であり
、第２図（ａ）は平面図、第２図（ｂ）は断面図である
。
第３図、第４図は本発明の半導体装置の別の実施例を示
す断面図である。
第５図、第６図は本発明を別の実装方式に適用した場合
を示す半導体装置の断面図である。
１ ・・入出力ＡＬ電極
２ ・・導電性突起物
３ ・・電ｆ！（ＡＬ）
４ ・・半導体エツジ
５．１２・ ・リード
６ ・・ＡＬ配線
７．１０・・コンタクト
・電極（ボワシリコン、ＡＬ）
・電極（半導体）
・拡散
・基板
・薄膜配線
以上
出願人 セイコーエプソン株式会社
代理人弁理士 鈴木喜三部（化１名）
第
図
第
図FIGS. 1(a) and 1(b) are diagrams showing an embodiment of the semiconductor device of the present invention, with FIG. 1(a) being a plan view and FIG. 1(b) being a sectional view. FIGS. 2(a) and 2(b) are diagrams showing a conventional semiconductor device, with FIG. 2(a) being a plan view and FIG. 2(b) being a sectional view. FIGS. 3 and 4 are cross-sectional views showing another embodiment of the semiconductor device of the present invention. FIGS. 5 and 6 are cross-sectional views of a semiconductor device in which the present invention is applied to another mounting method. 1...Input/output AL electrode 2...Conductive protrusion 3...Electric f! (AL) 4 ・・Semiconductor edge 5.12・ ・Lead 6 ・・AL wiring 7.10・・Contact/electrode (boisilicon, AL) ・Electrode (semiconductor) ・Diffusion/substrate/thin film wiring and above Applicant: Seiko Epson Representative Patent Attorney Co., Ltd. Kizobe Suzuki (1 person) Figure Figure
Claims (1)
、棒状もしくは薄膜状の導電体によって外部に電位もし
くは信号を入出力する電極構造において、ワイヤー、棒
状もしくは薄膜状の前記導電体の引出し部分と対向する
半導体基板上に各々の電極と同電位、同一信号の電極を
設けることを特徴とする半導体装置。In an electrode structure that has a plurality of signal or power input/output electrodes and inputs/outputs a potential or signal to the outside using a wire, rod-shaped, or thin-film conductor, the electrode structure faces the lead-out portion of the wire, rod-shaped, or thin-film conductor. A semiconductor device characterized in that electrodes having the same potential and the same signal as each electrode are provided on a semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2191212A JPH0476928A (en) | 1990-07-19 | 1990-07-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2191212A JPH0476928A (en) | 1990-07-19 | 1990-07-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0476928A true JPH0476928A (en) | 1992-03-11 |
Family
ID=16270773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2191212A Pending JPH0476928A (en) | 1990-07-19 | 1990-07-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0476928A (en) |
-
1990
- 1990-07-19 JP JP2191212A patent/JPH0476928A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| SE9703295D0 (en) | Electrical devices and a method of manufacturing the same | |
| KR920006746A (en) | Semiconductor Capacitive Accelerometer | |
| EP0064231A2 (en) | Compression-type semiconductor device | |
| US4902555A (en) | Hybrid circuit element and method of manufacturing the same | |
| GB1296498A (en) | ||
| US4602170A (en) | Resistive gate field effect transistor logic family | |
| KR910013517A (en) | High Power Semiconductor Device | |
| JPH0476928A (en) | Semiconductor device | |
| ATE67897T1 (en) | INTEGRATED SEMICONDUCTOR CIRCUIT WITH AN ELECTRICALLY CONDUCTIVE SURFACE ELEMENT. | |
| JPS5753944A (en) | Semiconductor integrated circuit | |
| GB967365A (en) | Semiconductor devices | |
| JP2881907B2 (en) | Power semiconductor device | |
| JP2006100481A (en) | Semiconductor apparatus | |
| JPS59143358A (en) | Semiconductor thin film resistance element | |
| JPS6362339A (en) | Semiconductor device | |
| US20230140922A1 (en) | Current detection resistor and current detection apparatus | |
| JP3594725B2 (en) | Semiconductor device protection circuit | |
| JPH05501479A (en) | semiconductor switch | |
| JPH04188841A (en) | Semiconductor device | |
| JPS6112691Y2 (en) | ||
| JPH0513768A (en) | Insulating gate type bipolar transistor | |
| JPH05326844A (en) | Semiconductor integrated circuit | |
| JPS62155548A (en) | Electrostatic protective circuit element for semiconductor integrated circuit | |
| JPS61252652A (en) | Resin sealed type semiconductor device | |
| JPH04120771A (en) | Delay cell for master slice system ic device |