JPH04188841A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04188841A
JPH04188841A JP2318800A JP31880090A JPH04188841A JP H04188841 A JPH04188841 A JP H04188841A JP 2318800 A JP2318800 A JP 2318800A JP 31880090 A JP31880090 A JP 31880090A JP H04188841 A JPH04188841 A JP H04188841A
Authority
JP
Japan
Prior art keywords
lead
semiconductor substrate
semiconductor device
semiconductor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2318800A
Other languages
Japanese (ja)
Inventor
Toshihito Takagi
高木 稔仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2318800A priority Critical patent/JPH04188841A/en
Publication of JPH04188841A publication Critical patent/JPH04188841A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05073Single internal layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48095Kinked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]

Abstract

PURPOSE:To prevent the generation of a leakage due to the contact of a lead with a semiconductor substrate as well as to prevent the generation of the deterioration of a semiconductor device due to the moisture adsorption of a resin and to improve the moisture resistance of the device by a method wherein independent floating conductors are provided on the semiconductor substrate to oppose to the lead-out part of the lead. CONSTITUTION:A signal or a power supply is connected to an input/output aluminium electrode 5 via an aluminium wiring 10 on a semiconductor substrate and is inputted/outputted into/from the outside through a rodlike lead 11 via a conductive projected matter 4. A polysilicon layer or an aluminium layer 9 is formed between electrodes on adjacent chips at the time of the state of a wafer in such a way as to oppose to a lead-out part of this lead 11 and when this layer 9 is cut in each chip, the layer 9 is turned into conductors in a floating state. Accordingly, an electric field is not applied between the lead and the semiconductor substrate and it is eliminated that a semiconductor device or the lead is deteriorated. Thereby, the device, which is superior in moisture resistance and is capable of using a high voltage, can be obtained.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明は半導体装置の電極を有するチップエツジの半導
体基板の構造に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a chip edge semiconductor substrate having electrodes of a semiconductor device.

[従来の技術] 従来の半導体装置では、第2図A及び第2図Bに示すの
ように信号もしくは電位は入出力電極から導電体(以後
、リードと称す)により外部に引き出されるが、導電体
と半導体基板は半導体上の酸化膜及び樹脂を介して対面
している構造になっていた。
[Prior Art] In conventional semiconductor devices, as shown in FIGS. 2A and 2B, signals or potentials are drawn out from input/output electrodes by conductors (hereinafter referred to as leads). The structure was such that the body and the semiconductor substrate faced each other through an oxide film and resin on the semiconductor.

[発明が解決しようとする課題] しかし、前述の従来技術では、実装を行った徨、使用状
態等の様々な原因によりリードの曲がりを生じた場合、
第2図Aのように、そのリードがエツチングによりむき
だしになった半導体基板に接触することにより、リーク
を生じる可能性がある。
[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, if the lead is bent due to various reasons such as mounting errors or usage conditions,
As shown in FIG. 2A, leakage may occur when the leads come into contact with the semiconductor substrate exposed by etching.

更に、半導体基板とリードとの間に電界がかかると、樹
脂内に水分が含まれた場合は樹脂内の導電性物質が電界
によって移動し、経時的に半導体基板もしくはリードを
劣化させ半導体装置の信頼性を著しく低下させるという
問題点を有する。
Furthermore, when an electric field is applied between the semiconductor substrate and the leads, if moisture is contained in the resin, the conductive substance in the resin will move due to the electric field, degrading the semiconductor substrate or leads over time and damaging the semiconductor device. This has the problem of significantly lowering reliability.

そこで本発明は、このような問題点を解決するもので、
その目的とするところは、リードと半導体基板との接触
によるリークを防ぎ、経時的変化による劣化のない半導
体装置を提供することにある。
Therefore, the present invention aims to solve these problems.
The purpose is to prevent leakage due to contact between the leads and the semiconductor substrate, and to provide a semiconductor device that does not deteriorate due to changes over time.

[課題を解決するための手段] 本発明の半導体装置は、複数の信号もしくは電源の入出
力電極を有し、前記電極よりワイヤー、棒状もしくは薄
膜状の導電体によって外部に電位もしくは信号を入出力
する半導体装置において、ワイヤー、棒状もしくは薄膜
状の前記導電体の引出し部分と対向する半導体基板に浮
き導体を設けることを特徴とする。
[Means for Solving the Problems] The semiconductor device of the present invention has a plurality of signal or power input/output electrodes, and inputs/outputs potentials or signals to the outside from the electrodes using a wire, rod-shaped, or thin film-shaped conductor. The semiconductor device is characterized in that a floating conductor is provided on the semiconductor substrate facing the lead-out portion of the conductor in the shape of a wire, rod, or thin film.

[実施例] 第1図Aおよび第1図Bは本発明の構造を示す半導体装
置の一実施例である。第1図Aは、チップの断面図、第
1図Bは、チップを表面から見た図である。
[Embodiment] FIGS. 1A and 1B show an embodiment of a semiconductor device showing the structure of the present invention. FIG. 1A is a cross-sectional view of the chip, and FIG. 1B is a view of the chip viewed from the surface.

半導体基板内の信号および1!l源は半導体上のアルミ
配置s10を介して入出力アルミ電極5に接続され、更
に入出力アルミ電極上に形成された導電性突起物4を介
して棒状のリード11に接続され、外部に信号もしくは
電位を入出力する。このリード11の引出し部分に対向
してウェハー状態のときに互いにとなり合うチップの電
極間にPo1y−Siの層もしくはアルミの層が形成さ
れており、これをチップ毎にカットすると第1図Aおよ
びBのような状態になる。これは、酸化M8上にどの配
線や基板にもつながらない浮いた状態の導体が存在する
ことになる。Po1y−5iもしくはアルミの層がない
場合は第2図Aのようにチップエツジのみエツチングに
より酸化1[8が除去されてしまい基板がむきだしにな
るため、リード11が基板に接触した場合に基板とリー
ド間のみならず他端子との間にもリークが発生する。し
かし、本発明によれば、Po1y−3iもしくはアルミ
の層はそれぞれ独立した浮き導体となっているためにエ
ツチングをおこなっても基板がむきだしにならないので
、リードの接触によるリークは発生し得ない。POLY
−5iまたはアルミの浮き導体は、どの配線や基板にも
つながっていないのでむきだしとなっても問題はない。
Signals in the semiconductor substrate and 1! The l source is connected to the input/output aluminum electrode 5 via the aluminum arrangement s10 on the semiconductor, and further connected to the bar-shaped lead 11 via the conductive protrusion 4 formed on the input/output aluminum electrode, and is connected to the external signal. Or input/output the potential. A Po1y-Si layer or an aluminum layer is formed between the electrodes of chips that are adjacent to each other when they are in a wafer state, facing the lead-out portion of the lead 11, and when this is cut into chips, as shown in FIG. 1A and FIG. It will be in a state like B. This means that there is a floating conductor on the oxidized M8 that is not connected to any wiring or substrate. If there is no Po1y-5i or aluminum layer, as shown in Figure 2A, only the chip edge is etched to remove the oxide 1[8 and the substrate is exposed, so when the lead 11 comes into contact with the substrate, the substrate and the lead Leakage occurs not only between terminals but also between other terminals. However, according to the present invention, since the Po1y-3i or aluminum layers are independent floating conductors, the substrate is not exposed even when etched, so that leakage due to lead contact cannot occur. POLY
The -5i or aluminum floating conductor is not connected to any wiring or board, so there is no problem even if it is exposed.

また、リード11を固定するために半導体基板上に樹脂
を流し封止すると、半導体基板をP型とした場合、半導
体基板は常に最も低い電圧となっており、入出力電極に
高い電圧がかかるとり−ド11と半導体基板との間に電
界が生しる。樹脂は半導体基板上の絶縁層に比べ不安定
であるため、樹脂に水分が含まれた場合、電界により樹
脂内の導電粒子が移動し、絶縁層に少しでも導電性があ
ればlit流が流れ、これが長期的に続けばリードもし
くは半導体装置自体を劣化させる。第3図に、この状態
の等価回路を示す。12は基板側の電位、13はリード
側の電位、14は樹脂の抵抗R115はリードと半導体
基板間の容量C1を示す。電界がかかり、導電粒子が移
動するということは抵抗Rに電流が流れるということで
ある。つまり、リークが生じることになる。これは、N
型半導体基板でも同様である。
Furthermore, when resin is poured onto the semiconductor substrate to fix the lead 11 and the semiconductor substrate is sealed, if the semiconductor substrate is of P type, the semiconductor substrate always has the lowest voltage, and even if a high voltage is applied to the input/output electrodes, the semiconductor substrate will always be at the lowest voltage. - An electric field is generated between the node 11 and the semiconductor substrate. Resin is unstable compared to the insulating layer on the semiconductor substrate, so if the resin contains moisture, the electric field will move the conductive particles in the resin, and if the insulating layer has even a little conductivity, a lit current will flow. If this continues for a long time, the leads or the semiconductor device itself will deteriorate. FIG. 3 shows an equivalent circuit in this state. Reference numeral 12 indicates a potential on the substrate side, 13 indicates a potential on the lead side, and 14 indicates a resin resistor R115 indicating a capacitance C1 between the lead and the semiconductor substrate. When an electric field is applied and the conductive particles move, this means that a current flows through the resistor R. In other words, a leak will occur. This is N
The same applies to type semiconductor substrates.

ここで、Po1y−3iまたはアルミの浮き導体9を第
1図AおよびBのように形成することにより、リードと
半導体基板間に電界がかからず半導体装置またはリード
を劣化させることがなくなる。この状態を示す等価回路
が第4図である。これは、第3図に更に容量C2: 1
6をつけた形となり、例えリードと半導体基板間の樹脂
が導電性を示しても電流が流れなくなる。
By forming the floating conductor 9 of Poly-3i or aluminum as shown in FIGS. 1A and 1B, an electric field is not applied between the lead and the semiconductor substrate, thereby preventing deterioration of the semiconductor device or the lead. An equivalent circuit showing this state is shown in FIG. This further shows the capacitance C2: 1 in Figure 3.
6, and even if the resin between the lead and the semiconductor substrate exhibits conductivity, no current will flow.

第5図は、本発明の別の実施例で、リ−ド17上に突起
物を形成した場合を示す。
FIG. 5 shows another embodiment of the present invention in which protrusions are formed on the leads 17.

第6図は、導電性薄膜配線19が形成された回路基板1
8に半導体装置1をのせることにより、外部に信号もし
くは電位を引き出す場合の本発明の実施例である。薄膜
配線19に沿って浮き導体9が対向して伸びている。
FIG. 6 shows a circuit board 1 on which conductive thin film wiring 19 is formed.
This is an embodiment of the present invention in which a signal or a potential is extracted to the outside by mounting the semiconductor device 1 on the semiconductor device 8. Floating conductors 9 extend along thin film wiring 19 to face each other.

第7図は、ガラス基板20に導電性nfs配線19が形
成されており、半導体装置1を導電性粒子21を介して
接続されている。この場合では、第8図のように、電極
以外の所で薄膜配lll119と半導体装置1を導電性
粒子21が接触させてしまう可能性がある。この場合に
も、本発明は有効である。
In FIG. 7, conductive NFS wiring 19 is formed on a glass substrate 20, and the semiconductor device 1 is connected via conductive particles 21. In FIG. In this case, as shown in FIG. 8, there is a possibility that the conductive particles 21 may come into contact with the thin film interconnection 119 and the semiconductor device 1 at a location other than the electrode. The present invention is also effective in this case.

[発明の効果] 以上述べたように本発明によれば、リードの引出し部分
と対向する半導体基板上に各々独立した浮き導体を設け
ることにより、リードと半導体基板の接触により生ずる
リークを未然に防ぎ、入出力電極に高電圧がかかった場
合でもリードの引出し部分と半導体基板間には電界が生
じない。仮に湿度によって樹脂が導電性を示したとして
も、リードもしくは半導体装置を劣化することなく耐湿
性に優れた半導体装置とすることができる。また、電極
の電界が緩和されるため、微細実装が可能となり、より
高い電圧を扱う半導体装置の提供が可能になるという効
果を有する。
[Effects of the Invention] As described above, according to the present invention, by providing independent floating conductors on the semiconductor substrate facing the lead-out portion of the leads, leaks caused by contact between the leads and the semiconductor substrate can be prevented. Even if a high voltage is applied to the input/output electrodes, no electric field is generated between the lead-out portion of the lead and the semiconductor substrate. Even if the resin exhibits conductivity due to humidity, a semiconductor device with excellent moisture resistance can be obtained without deteriorating the leads or the semiconductor device. Furthermore, since the electric field of the electrode is relaxed, it is possible to carry out finer packaging, and it is possible to provide a semiconductor device that can handle higher voltages.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A及びBは、本発明の一実施例を示す半導体装置
の断面図及び表面図。 第2図A及びBは、従来の半導体装置及びその問題点を
示す断面図及び表面図。 第3図は、従来の半導体装置の等価回路図。 第4図は、本発明の一実施例を示す半導体装置の等価回
路図。 第5図、第6図、第7図、第8図は、本発明を別の実装
方式に適用した場合を示す半導体装置の断面図。 1:半導体装置 2:チップエツジ 3:電極開口部 4:導電性突起物 5ニアルミ電極 6.7.8:@化膜 9: Po1y−3iまたはA1の浮き導体10ニアル
ミ配線 11.17: リード 12: P型基板側の電位 13:リード側の電位 14:抵抗R 15,16:容量C1、C2 1日:回路基板 19:i膜配線 20ニガラス基板 21:導電性粒子 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 鈴木喜三部(他1名)第1図A 第1図B 第2図A 第2図B 第゛4図
1A and 1B are a sectional view and a surface view of a semiconductor device showing an embodiment of the present invention. FIGS. 2A and 2B are a cross-sectional view and a surface view showing a conventional semiconductor device and its problems. FIG. 3 is an equivalent circuit diagram of a conventional semiconductor device. FIG. 4 is an equivalent circuit diagram of a semiconductor device showing an embodiment of the present invention. 5, 6, 7, and 8 are cross-sectional views of semiconductor devices in which the present invention is applied to other mounting methods. 1: Semiconductor device 2: Chip edge 3: Electrode opening 4: Conductive protrusion 5 Ni-aluminum electrode 6.7.8: @ film 9: Poly-3i or A1 floating conductor 10 Ni-aluminum wiring 11.17: Lead 12: P-type substrate side potential 13: Lead side potential 14: Resistance R 15, 16: Capacitance C1, C2 1st: Circuit board 19: i-film wiring 20 Ni glass substrate 21: Conductive particles and above Applicant: Seiko Epson Corporation Agent Person Patent attorney Kizobe Suzuki (and 1 other person) Figure 1A Figure 1B Figure 2A Figure 2B Figure 4

Claims (1)

【特許請求の範囲】[Claims] 複数の信号もしくは電源の入出力電極を有し、前記電極
よりワイヤー、棒状もしくは薄膜状の導電体によって外
部に電位もしくは信号を入出力する半導体装置において
、ワイヤー、棒状もしくは薄膜状の前記導電体の引出し
部分と対向する半導体基板に個々に浮き導体を設けるこ
とを特徴とする半導体装置。
In a semiconductor device that has a plurality of signal or power input/output electrodes and inputs/outputs a potential or signal to the outside through a wire, rod-shaped or thin film-shaped conductor from the electrodes, the wire, rod-shaped or thin film-shaped conductor is A semiconductor device characterized in that floating conductors are individually provided on a semiconductor substrate facing a drawer portion.
JP2318800A 1990-11-22 1990-11-22 Semiconductor device Pending JPH04188841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2318800A JPH04188841A (en) 1990-11-22 1990-11-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2318800A JPH04188841A (en) 1990-11-22 1990-11-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04188841A true JPH04188841A (en) 1992-07-07

Family

ID=18103087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2318800A Pending JPH04188841A (en) 1990-11-22 1990-11-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04188841A (en)

Similar Documents

Publication Publication Date Title
KR920006746A (en) Semiconductor Capacitive Accelerometer
GB1137907A (en) Improvements in or relating to multiple-chip integrated circuit assembly with interconnection structure
KR970067775A (en) Semiconductor devices
JPS61500996A (en) Semiconductor structure with resistive electric field shield
JPS6119118B2 (en)
KR850004344A (en) Built-in resistor of cathode ray tube
JPH04188841A (en) Semiconductor device
JPS5753944A (en) Semiconductor integrated circuit
JPS63108763A (en) Semiconductor integrated circuit
JPS5864065A (en) Preventing device for corroding semiconductor integrated circuit
JPS59143358A (en) Semiconductor thin film resistance element
JPH0580153B2 (en)
JPS6362339A (en) Semiconductor device
JPS5982753A (en) Package for semiconductor device
JPS61230333A (en) Integrated circuit
JPS61252652A (en) Resin sealed type semiconductor device
JPH0476928A (en) Semiconductor device
KR200165750Y1 (en) Metal wiring in semiconductor device
JP2682236B2 (en) Semiconductor integrated circuit device
KR200183767Y1 (en) Semiconductor device
JPS6011646Y2 (en) flat package
KR950004785Y1 (en) Taping structure of lead wire in electrolytic condenser
JPH0130301B2 (en)
JPS62155548A (en) Electrostatic protective circuit element for semiconductor integrated circuit
JPH0278274A (en) Insulated gate field effect transistor