JPH0476916A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0476916A
JPH0476916A JP19180190A JP19180190A JPH0476916A JP H0476916 A JPH0476916 A JP H0476916A JP 19180190 A JP19180190 A JP 19180190A JP 19180190 A JP19180190 A JP 19180190A JP H0476916 A JPH0476916 A JP H0476916A
Authority
JP
Japan
Prior art keywords
resist
polymer resin
substrate
film
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19180190A
Other languages
Japanese (ja)
Other versions
JP2510038B2 (en
Inventor
Hiromichi Arai
新井 廣道
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP19180190A priority Critical patent/JP2510038B2/en
Publication of JPH0476916A publication Critical patent/JPH0476916A/en
Application granted granted Critical
Publication of JP2510038B2 publication Critical patent/JP2510038B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To improve productivity and quality with the steps of resist coating and peeling cut down and residuals of resist and chemicals eliminated by sticking a polymer resin film directly to a substrate without use of resist film. CONSTITUTION:The surface of a semiconductor substrate 1 is stuck as a first polymer resin film 2 entirely with a rubbery high polymer resin tape 2 slightly extendable and back-coated with adhesive, and the tape is cut on the substrate 1 side. Next, an excel coat liquid of vinyl chloride that is a second polymer resin is applied by covering the edge side face of the substrate 1 and the tape 2 and naturally dried to volatilize flux, thereby forming a vinyl chloride film 3. Then, the substrate 1 is ground and polished in three stages using a polisher of semiconductor substrate back. The polished substrate 1 rid of the tape 2 by peeling together with the film 3. Use of no resist film like this prevents residuals of resist peeling liquid and deposits of resist and contribute improvement in productivity and quality with the surface kept clean.

Description

【発明の詳細な説明】 〔概要〕 本発明は、半導体装置の製法に係り、特に半導体基板の
研磨方法に関し 研削工程の短縮と半導体基板表面の損傷防止を目的とし 半導体基板表面に第1の高分子樹脂膜を貼りつける工程
と、#f;半導体基板の端側面並びに該第1の高分子樹
脂膜を覆って、第2の高分子樹脂のコート液を塗布し、
乾燥して第2の高分子樹脂膜を形成する工程と、しかる
後、該半導体基板の背面を一定の厚さまで研磨する工程
と、該半導体基板表面の第2の高分子樹脂膜並びに第1
の高分子樹脂膜を同時に剥離除去する工程とを含むよう
に構成する。
Detailed Description of the Invention [Summary] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for polishing a semiconductor substrate. a step of pasting a molecular resin film;
a step of drying to form a second polymer resin film, then a step of polishing the back surface of the semiconductor substrate to a certain thickness, and a step of drying the second polymer resin film and the first polymer resin film on the surface of the semiconductor substrate.
The method is configured to include a step of simultaneously peeling off and removing the polymer resin film.

〔産業上の利用分野〕[Industrial application field]

本発明は、半導体装置の製法に係り、特に半導体基板の
研磨方法に関する。
The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for polishing a semiconductor substrate.

現状の半導体基板研削工程は、工程が長く、且っ マス
クとして使用したレジストを専用液で剥離する際に、レ
ジストが半導体基板の表面に残る或いは、レジスト剥離
専用液が表面に残るといった問題を抱えており、この打
開策が必要である。
The current semiconductor substrate grinding process is long and has problems such as when removing the resist used as a mask with a special solution, the resist remains on the surface of the semiconductor substrate, or the resist stripping solution remains on the surface. A solution to this problem is necessary.

[従来の技術] 第今図は従来例の説明図である。[Conventional technology] Figure 1 is an explanatory diagram of a conventional example.

図において、21は半導体基板、22はレジスト膜23
は高分子樹脂膜である。
In the figure, 21 is a semiconductor substrate, 22 is a resist film 23
is a polymer resin film.

従来の半導体基板研削工程においては、半導体素子を形
成した基板表面が研削工程中に損傷しないように、厚く
レジスト膜を塗布し、その上に高分子樹脂膜からなるイ
クロステープを張り付けた状態で背面を研削していた。
In the conventional semiconductor substrate grinding process, in order to prevent the surface of the substrate on which semiconductor elements are formed from being damaged during the grinding process, a thick resist film is applied and ICROSS tape made of a polymer resin film is pasted on top of the resist film. The back was being ground.

この方法はレジストの塗布、乾燥、及び研削後のレジス
ト膜の剥離除去等と工程が長い事と、レジストの微片が
取り切れず残ること、及びレジスト剥離液の残渣が半導
体基板の表面ムこ残る事など多くの問題があった。
This method requires a long process of applying the resist, drying it, and peeling off the resist film after grinding, and also has the disadvantages that small pieces of the resist remain without being removed, and that the residue of the resist stripping solution may cause unevenness on the surface of the semiconductor substrate. There were many problems that remained.

(発明が解決しようとする課題] 従って、従来工程ではレジストの塗布、剥離が独立の工
程として存在し、工程も長く、レジストや剥離液の残渣
が残ってしまうといった問題があった。
(Problems to be Solved by the Invention) Therefore, in the conventional process, resist coating and stripping exist as independent steps, the steps are long, and there are problems in that residues of the resist and stripping solution remain.

本発明は9以上の点に鑑み、これらの欠点を解消して、
半導体基板の研削工程を短縮し1種々の表面残渣がなく
なる方法を得ることを目的として提供されるものである
In view of the above points, the present invention solves these drawbacks, and
The object of the present invention is to provide a method that shortens the process of grinding a semiconductor substrate and eliminates various surface residues.

〔課題を解決するための手段〕[Means to solve the problem]

第1図は本発明の原理説明図兼半導体基板背面研磨の工
程順模式断面図である。
FIG. 1 is an explanatory diagram of the principle of the present invention and a schematic cross-sectional view of the process order of back polishing of a semiconductor substrate.

図において、1は半導体基板、2は第1の高分子樹脂膜
、3は第2の高分子樹脂膜、4;まダイシングライン溝
、5は隙間、6は研削面、7は研磨面である。
In the figure, 1 is a semiconductor substrate, 2 is a first polymer resin film, 3 is a second polymer resin film, 4 is a dicing line groove, 5 is a gap, 6 is a ground surface, and 7 is a polished surface. .

本発明では、上記の問題点を解決するためにゴム性の多
少伸展性のある第1の高分子樹脂膜例えば、イクロステ
ーブを直接に半導体基板上の素子表面に張り付け2ダイ
シングライン溝を介して、半導体基板の周縁よりの水等
の研削液の進入を防くために、塩化ビニールあどの第2
の高分子樹脂を溶剤にで容かした1例えばエクセルコー
ト液を塗布することによって、レジストを使用せずに即
ち、レジスト膜の塗布工程や剥離工程をなくして、レジ
スト等の残渣の発生を防止する。
In the present invention, in order to solve the above-mentioned problems, a rubbery and somewhat extensible first polymer resin film, for example, a Microstave, is directly attached to the element surface on a semiconductor substrate through two dicing line grooves. In order to prevent grinding fluid such as water from entering from the periphery of the semiconductor substrate, a second layer of vinyl chloride gate is installed.
By applying, for example, an Excel coat solution containing a polymer resin in a solvent, no resist is used, i.e., the process of applying and peeling off a resist film is eliminated, and the generation of residues such as resist is prevented. do.

即ち1本発明の目的は 第1図(a)に示すように、半導体基板1表面に第1の
高分子樹脂膜2を貼りつける工程と第1図(b)に示す
ように、該半導体基板1の端側面並びに該第1の高分子
樹脂膜2を覆って。
That is, one object of the present invention is the process of attaching a first polymer resin film 2 to the surface of a semiconductor substrate 1, as shown in FIG. 1 and the first polymer resin film 2.

第2の高分子樹脂のコート液を塗布し1乾燥して第2の
高分子樹脂膜3を形成する工程としかる後、第1図(c
)に示すように、該半導体基板1の背面を一定の厚さま
で研磨する工程と該半導体基板lの表面の第2の高分子
樹脂膜3並びに第1の高分子樹脂膜2を同時に剥離除去
する工程とを含むことにより達成される。
After that, a second polymer resin coating solution is applied and dried to form a second polymer resin film 3, as shown in FIG.
), the step of polishing the back surface of the semiconductor substrate 1 to a certain thickness and simultaneously peeling off and removing the second polymer resin film 3 and the first polymer resin film 2 on the surface of the semiconductor substrate 1 This is achieved by including the steps.

[作用〕 本発明では、レジスト膜を使用せず、基板乙こ直接に高
分子樹脂膜を張り付けるので、レジストの塗布や剥離工
程か削減され、レジストや薬品の残渣がなくなる。
[Function] In the present invention, a polymer resin film is attached directly to the substrate without using a resist film, so the steps of resist application and peeling are reduced, and there is no resist or chemical residue.

〔実施例〕〔Example〕

て 第奢図は本発明の一実施例の工程+1[+¥模式断面図
第2図は半導体基板背面研磨の工程順模式断面図第3図
は半導体基板背面研磨装置の斜視図である。
FIG. 2 is a schematic cross-sectional view of the steps of polishing the back surface of a semiconductor substrate according to an embodiment of the present invention. FIG. 3 is a perspective view of a semiconductor substrate back surface polishing apparatus.

図において、1は半導体基板、2は第1の高分子樹脂膜
、3は第2の高分子樹脂膜、4はダイシングライン溝、
5は隙間、6は研削面、7は研磨面、8は第1のホイー
ル、9は第2のホイール。
In the figure, 1 is a semiconductor substrate, 2 is a first polymer resin film, 3 is a second polymer resin film, 4 is a dicing line groove,
5 is a gap, 6 is a grinding surface, 7 is a polishing surface, 8 is a first wheel, and 9 is a second wheel.

10は第3のホイール、 11は第1のコラム、 12
は第2のコラム、13は第3のコラム、14はエレヘー
ターカハー115は基板装填アーム、16は調整アーム
17は研削テーブル、18は基板脱着アーム、19はコ
ントロールテーブル、20は表示パネルである。
10 is the third wheel, 11 is the first column, 12
14 is the second column, 13 is the third column, 14 is the electric heater 115 is the substrate loading arm, 16 is the adjustment arm 17 is the grinding table, 18 is the substrate removal arm, 19 is the control table, and 20 is the display panel. be.

本発明の一実施例について説明する。An embodiment of the present invention will be described.

先ず、第1図(a)に示すように、半導体基板1として
の1表面に素子を形成した直径150mm。
First, as shown in FIG. 1(a), a semiconductor substrate 1 having a diameter of 150 mm has elements formed on one surface thereof.

厚さ約625μmの厚さのシリコンウェハーの表面に第
1の高分子樹脂膜2として、ゴム系の多少伸展性のある
。裏面に接着剤を塗布した50μm厚さのイクロステー
プをウェハ全面に貼り付け、ウェハ側面にてテープをカ
ッティングする。
A first polymer resin film 2 made of a rubber-based material with some extensibility was formed on the surface of a silicon wafer having a thickness of about 625 μm. A 50 μm thick ICROS tape coated with adhesive on the back side is pasted on the entire surface of the wafer, and the tape is cut on the side of the wafer.

次に第1図(b)に示すように、ウェハ1の端側面並び
にイクロステープ2を覆って1第2の高分子樹脂である
塩化ビニールのエクセルコート液をスピナーにより約1
0μmの厚さに塗布し、自然乾燥して1溶剤を揮発し5
塩化ビニール膜を形成する。
Next, as shown in FIG. 1(b), about 1 coat of Excel coating solution of vinyl chloride, which is a second polymer resin, is applied using a spinner to cover the end side surface of the wafer 1 and the ICROS tape 2.
Apply to a thickness of 0 μm, dry naturally to evaporate the solvent, and
Forms a vinyl chloride film.

しかる後、第1図(C)に示すように、第3図に斜視図
により示した半導体基板背面研磨装置を用いて、ウェハ
1を3段階に研削・研磨する。
Thereafter, as shown in FIG. 1C, the wafer 1 is ground and polished in three stages using the semiconductor substrate back polishing apparatus shown in a perspective view in FIG.

研磨装置は第3図に斜視図で示すように、ウェハカセッ
トに装填されたウェハの基板1は、基板装着アーム15
により研削テーブルに装着し、真空吸着により固定する
。研磨テーブルには、  150mm径ウェハがつ枚装
填可能である。
In the polishing apparatus, as shown in a perspective view in FIG.
Attach it to the grinding table and fix it by vacuum suction. The polishing table can be loaded with 150 mm diameter wafers.

装置には第1コラム11から第3コラム13までの3個
のコラムが設けられ、コラムにはそれぞれに・回転する
鋼製のホイールがセットされている。ホイールの先端に
は粒度の異なる工業ダイヤモンドの微粒が埋め込まれて
おり、第1から第3のホイールへと1粒度が細かくなっ
ている。
The device is provided with three columns from a first column 11 to a third column 13, and each column is equipped with a rotating steel wheel. The tip of the wheel is embedded with fine grains of industrial diamond of different grain sizes, and the grain size becomes finer from the first to the third wheel.

ホイールは1 、500rpmで回転しながら、ゆっく
り回転する研削テーブル17上のウェハー1を端より順
に研削していく。
While rotating at 1.500 rpm, the wheel sequentially grinds the wafer 1 on the slowly rotating grinding table 17 starting from the end.

研削は3第2図(a)に示すように、ウェハ1を第1の
ホイール8で粗削りを行い、540μm厚さまで削る。
As shown in FIG. 2(a), the wafer 1 is roughly ground with the first wheel 8 to a thickness of 540 μm.

次に、第2図(b)に示すように第2のホイール9で中
削りを行い510μmの厚さまで削る。更に、第2図(
c)に示すように、第3のホイール10で仕上げ削りを
行い、500 μmまで削る。
Next, as shown in FIG. 2(b), the second wheel 9 is used to perform medium cutting to a thickness of 510 μm. Furthermore, Figure 2 (
As shown in c), finish cutting is performed using the third wheel 10 to cut down to 500 μm.

全体の研削時間は5−6分で1枚仕上がり、自動的に基
板脱着アーム18によりウェハ1を吸着して ウニバカ
セットに収められる。
The total grinding time is 5 to 6 minutes, and one wafer is finished, and the wafer 1 is automatically sucked by the substrate removal arm 18 and placed in the Univac set.

背面を研削したウェハlは、そのまま弗硝酸のエンチン
グ液で背面を軽<30秒程度エツチングし。
After the back side of the wafer has been ground, the back side of the wafer is lightly etched for about 30 seconds using an etching solution of fluoronitric acid.

ウェハlを490μmの厚さに研磨して仕上る。The wafer 1 is polished to a thickness of 490 μm.

研磨の終了したウェハーは3第1図(d)!:示すよう
に、イクロステープ2をその上のエクセルコートフィル
ム3毎剥がして取り去る。
The wafer that has been polished is shown in Figure 1 (d)! : As shown, peel off the ICROS tape 2 along with the EXCEL coat film 3 on it and remove it.

この様にして、研磨したウェハはレジスト膜を使用しな
いので、レジスト剥離液の残渣や、レジストの付着がな
く、清浄な表面を保つことができた。
Since no resist film was used on the polished wafer in this manner, it was possible to maintain a clean surface without any residue of the resist stripping solution or adhesion of resist.

[発明の効果] 本発明では、上記のように、レジストの剥離工程が削減
され、レジストや薬品の残渣が無くなるので、生産性の
向上1品質の向上に寄与するところが大きい。
[Effects of the Invention] As described above, the present invention reduces the resist peeling process and eliminates resist and chemical residues, which greatly contributes to improved productivity and improved quality.

第3図はウェハ背面研磨装置 第4図は従来例の説明図 である。Figure 3 shows wafer back polishing equipment Figure 4 is an explanatory diagram of the conventional example. It is.

図において。In fig.

】は半導体基板、   2は第1の高分子樹脂膜。] is a semiconductor substrate, and 2 is a first polymer resin film.

3は第2の高分子樹脂膜 4はダイシングライン溝 5は隙間、      6は研削面 7は研磨面1    8は第1のホイール9は第2のホ
イール、 10は第3のホイール11は第1のコラム、
12は第2のコラム13は第3のコラム、14はエレヘ
ーターカハ15は基板装填アーム、16は調整アーム。
3 is the second polymer resin film 4, the dicing line groove 5 is the gap, 6 is the grinding surface 7 is the polishing surface 1, 8 is the first wheel 9 is the second wheel, 10 is the third wheel 11 is the first column,
12 is a second column 13 is a third column, 14 is an electric heater 15 is a substrate loading arm, and 16 is an adjustment arm.

17は研削チーフル、  18は基板脱着アーム19は
コントロールチーフル 20は表示パネル
17 is the grinding chiffle, 18 is the board removal arm 19 is the control chifur, and 20 is the display panel.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の工程順模式断面図第2図は
ウェハ研磨の工程順模式断面図(d) 「]二Y=北」■面 本年明の 実施例の工材llI!iI人断面図 第人口 面図第1図粛装置 鞘 3 図
Fig. 1 is a schematic sectional view of the process order of one embodiment of the present invention. Fig. 2 is a schematic sectional view of the process order of wafer polishing (d). ! iI Human cross section Figure 1 Figure 1 Figure 3

Claims (1)

【特許請求の範囲】 半導体基板(1)表面に第1の高分子樹脂膜(2)を貼
りつける工程と、 該半導体基板(1)の端側面並びに該第1の高分子樹脂
膜(2)を覆って、第2の高分子樹脂のコート液を塗布
し、乾燥して第2の高分子樹脂膜(3)を形成する工程
と、 しかる後、該半導体基板(1)の背面を一定の厚さまで
研磨する工程と、 該半導体基板(1)表面の第2の高分子樹脂膜(3)並
びに第1の高分子樹脂膜(2)を同時に剥離除去する工
程とを含むことを特徴とする半導体装置の製造方法。
[Claims] A step of pasting a first polymer resin film (2) on the surface of a semiconductor substrate (1), and an end side surface of the semiconductor substrate (1) and the first polymer resin film (2). a step of coating the semiconductor substrate (1) with a second polymer resin coating solution and drying it to form a second polymer resin film (3); It is characterized by comprising the step of polishing to a thickness, and the step of simultaneously peeling and removing the second polymer resin film (3) and the first polymer resin film (2) on the surface of the semiconductor substrate (1). A method for manufacturing a semiconductor device.
JP19180190A 1990-07-18 1990-07-18 Method for manufacturing semiconductor device Expired - Lifetime JP2510038B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19180190A JP2510038B2 (en) 1990-07-18 1990-07-18 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19180190A JP2510038B2 (en) 1990-07-18 1990-07-18 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0476916A true JPH0476916A (en) 1992-03-11
JP2510038B2 JP2510038B2 (en) 1996-06-26

Family

ID=16280765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19180190A Expired - Lifetime JP2510038B2 (en) 1990-07-18 1990-07-18 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2510038B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008151028A (en) * 2006-12-18 2008-07-03 Suzuki Motor Corp Oil filter mounting structure of inclined engine

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008151028A (en) * 2006-12-18 2008-07-03 Suzuki Motor Corp Oil filter mounting structure of inclined engine

Also Published As

Publication number Publication date
JP2510038B2 (en) 1996-06-26

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