JPH0476147B2 - - Google Patents

Description

Detailed Description of the Invention [Industrial Application Field] The present invention is located between a central processing unit and a plurality of peripheral devices, and temporarily stores input/output information between the central processing unit and each peripheral device in a memory. An input/output control device comprising a control unit that stores and distributes data to each device, a line support unit that is distributed to each peripheral device and communicates with the peripheral device, and a bus that connects the control unit and the line support unit. .

[Conventional technology]

FIG. 2 is a block diagram showing the configuration of a conventional input/output control device located between a host computer and a peripheral device when a facsimile terminal is used as a computer peripheral device.

This input/output control device is a microprocessor 2
4 and a host computer interface circuit 21, a memory 22, a bus control circuit 23, an image signal conversion circuit 25, and a bus expansion circuit 26, which are connected to the host computer by a bus 27. a multiplex facsimile signal converter 2 that converts the signals into lines and sends them out in a line-compatible manner; and a facsimile signal modem 32 ₁ , 32
₂ ,..., 32 _o and modem control circuits 31 ₁ , 31 ₂ ,..., 31 _o that control these, and lines (line numbers #0, #1,..., #n) that control communication with facsimile terminals. -1) Correspondingly distributed facsimile control units 3 ₁ , 3 ₂ , ..., 3 _o , multiple facsimile signal conversion unit 2 and facsimile control unit 3 ₁ ,
3 ₂ , _. in this case,
The facsimile control unit 3 ₁ , 3 ₂ , ..., 3n outputs the message of the line to the facsimile terminal,
The address of the area where the message is stored is sequentially output to the address of the bus 4, and the message is read from the memory 22.

[Problem that the invention seeks to solve]

In the conventional input/output control device for facsimile described above, in the multiplex facsimile signal converter 2, message storage areas in the memory 22 are determined one-to-one for each line, Since the messages to be sent are managed by the start address of each area, if the correspondence between the line number and the address is disrupted due to some kind of failure, the message that should be sent to another line will be incorrectly output. There are drawbacks.

[Means for solving problems]

The input/output control device of the present invention includes a register in which a predetermined identification code corresponding to each line corresponding section is written by the control section when transmitting and receiving data between the control section and the line corresponding section; Each bit of data is input to one input terminal, each output of the register is input to the other input terminal, and the output terminal is connected to the bus. A first connected exclusive OR circuit group, a logic circuit that outputs the predetermined identification code to the line corresponding section, and a logic circuit corresponding to the number of bits of the data, one input terminal of which is connected to the bus. It has a second exclusive OR circuit group to which each bit of the above data is input, each output of the logic circuit is input to the other input terminal, and the output terminal is connected to the data input circuit of the control section.

Therefore, when the data stored in the address corresponding to the line corresponding section of the control section is connected so as to be correctly output to the line corresponding section, the data is stored at the address corresponding to the line corresponding section in the first exclusive OR circuit group. Based on the identification code set for the line corresponding section, the bits of the data input to the first exclusive OR circuit to which "1" is input from the register are inverted. The data in which one or more bits have been inverted is transferred to the logic circuit in the second exclusive logic circuit group with the same identification code given to the first exclusive OR circuit for each bit corresponding to the data. Since the bits of the data inverted in the first exclusive OR circuit group are restored to their original state, the data is restored. However, if the data is output to the wrong line corresponding section, the identification code given to the first exclusive OR circuit group and the identification code given to the second exclusive OR circuit group will not correspond. Information cannot be read correctly, and understanding of information output to the wrong line can be hindered.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

1A and 1B are block diagrams of an image signal output circuit and an image signal input circuit, respectively, which constitute one embodiment of the input/output control device of the present invention.

The image signal output circuit and image signal input circuit are each
The bus expansion circuit 26 and the facsimile control unit 3 of the multiple facsimile signal conversion unit 2 of the conventional input/output control device shown in FIG. 2 are provided when the peripheral devices are a plurality of facsimile terminals.

The image signal output circuit includes input terminals 51 ₁ , 52 ₂ , ..., 51m connected to the data bus of the bus 27,
Output terminal 58 ₁ connected to the data bus of bus 4,
58 ₂ ,..., 58m, a clock terminal 53 to which a clock is applied, a buffer control signal terminal 54 to which a buffer control signal is applied, and an input terminal 51 ₁ ,
51 ₂ ,..., 51 _n and a register 55 to which the clock terminal 53 is connected, and the input terminals 51 ₁ , 51 ₂ ,
..., 51 _n are connected to one input terminal of each, and the output of the register 55 is connected to the other input terminal of the first exclusive OR circuit 56 ₁ , 5
6 ₂ ,..., 56 _n and the first exclusive OR circuits 56 ₁ , 56 ₂ , controlled by the buffer control signal.
..., 56 _n , output terminals 58 ₁ , 58 ₂ ,
..., 58 _n . Note that the clock terminal 53 and buffer control signal terminal 54 are connected to a control circuit within the bus expansion circuit 26.

The image signal input circuit is connected to input terminals 61 ₁ , 61 ₂ , ..., 61 _n connected to the data bus 4 and data input terminals of the modem control circuits 31 ₁ , 31 ₂ , ..., 31 _o . Output terminals 58 ₁ , 58 ₂ ,
..., 58 _n and the upper bits of the image signal storage address of the memory 22 to be output to the bus 4 when reading the image signal are inputted to the facsimile control section 3 ₁ , 3 ₂ , . . .
3 Line numbers corresponding to _o #0, #1,..., #n-
1, a second buffer 63 to which the input terminals 61 ₁ , 61 ₂ , ..., 61 _n are connected, and the logic circuit 65
The outputs of the second buffer 63 are connected to one input terminal, respectively, and the outputs of the second buffer 63 are connected to the other input terminal, and the outputs of the second buffer 63 are connected to the output terminals 67 ₁ , 67 ₂ , . . . , 6 .
7 _n connected to the second exclusive OR circuit 66 ₁ ,
66 ₂ ,...,66 _n .

Next, the operation of this embodiment will be described in the case where an image signal is sent from the multiplex facsimile signal converter 2 to the #0 circuit of the facsimile controller 3.

The microprocessor 24 of the multiplex facsimile signal converter 2 instructs the facsimile controller 3 to send out an image signal via the bus 4, and then stores an identification code [1010...
10〕 Write _B. When the facsimile control unit 3 receives an instruction to transmit an image signal from the multiple facsimile signal conversion unit 2, the facsimile control unit 3 converts the multiple facsimile signal conversion unit 2 into which the message of the line #0, which has been notified in advance by the multiple facsimile signal conversion unit 2, is stored. The address of the memory 22 is output to the address bus 4, and the image signal read from the memory 22 is sent to the bus 27 of the microprocessor 24 and the first exclusive OR circuit 56 ₁ , 56 ₂ , of the image signal output circuit. ..., 56 _n ,
The first buffer 57, the bus 4, the second buffer 63 of the image signal input circuit, and the second exclusive OR circuit 6
6 ₁ , 66 ₂ , ..., 66 _n .

The image signal is connected to the first exclusive logical solution path 56 ₁ , 56
₂ ,..., _56n , the other input terminal of the first exclusive OR circuit ₅₆₁ , ₅₆₂ ,..., _56n receives a logic signal according to the line number identification code written in the register 55. Where 1 is input, the image signal is inverted and output. In other words, the line number identification code for line number #0 [ _MSB 1 010...1
_LSB 0 ] _B , so the output terminal 58 ₁ of the image signal output circuit,
The image signals outputted to 58 ₂ , . . . , 58 _n are inverted every other bit and outputted from the output terminal 58 ₁ .
The image signal passes through the second buffer 63 of the image signal input circuit connected to the facsimile control section 3 and is then input to the second exclusive OR circuits 66 ₁ , 66 ₂ , . . . , 66 _n
When passing through the second exclusive OR circuit 66 ₁ ,
Since the line number identification code of line number #0 from the logic circuit 65 is given to the other input terminal of 66 ₂ , ..., 66 _n , the image signal inverted by the image signal output circuit is inverted again. The original image signal is restored. Here, the logic circuit 65 inputs the upper bits of a different address for each line that the facsimile control unit outputs to the bus 4, and outputs a predetermined line number identification code that corresponds one-to-one to the line number. It's summery. Therefore, if the correspondence between the line number and the message storage address in the memory 22 is correct, the second exclusive OR circuits 66 ₁ , 66 ₂ ,
. . , 66 _n, an image signal restored to the original image signal read out from the memory 22 appears. However, if the correspondence between the line number and the message storage address in the memory 22 is disrupted due to some fault, the line identification code written in the register 55 and the line number identification code created from the address signal by the logic circuit 65 will be different, and some bits of the outputs of the second exclusive OR circuits 66 ₁ , 66 ₂ , . . . , 66 _n will remain inverted.
Therefore, when this image signal is transmitted to a facsimile terminal, a decoding error occurs at the facsimile terminal and a communication error occurs in the G3 facsimile that uses a modified Huffman code as the image signal. Furthermore, in G2 facsimile machines that use binary codes, vertical stripes appear on the screen recorded on the facsimile terminal, making it impossible to read the screen correctly.

In this embodiment, _an example has been shown in which data is sent from the multiplex facsimile signal converter 2 to the facsimile control units _{3 1 ,} 3 ₂ , ..., 3n; When transmitting data from the facsimile signal converter 2 to the multiplex facsimile signal converter 2, the multiplex facsimile signal converter 2 and the facsimile controllers 3 ₁ , 3 ₂ , . This is possible by adding one more set.

〔Effect of the invention〕

As explained above, in the present invention, when data is sent from the control section to the line correspondence section, the data is converted with an identification code corresponding to the line correspondence section, and the line correspondence section converts the data using the identification code. By restoring the data with an identification code compatible with the line handling unit, even if data from another line is sent due to a device failure, the line handling unit will experience a communication error or become unable to understand the data. It has the effect of preventing leakage.

[Brief explanation of the drawing]

FIGS. 1a and 1b are block diagrams of an image signal output circuit and an image signal input circuit, respectively, which constitute one embodiment of the input/output control device of the present invention, and FIG. 1 is a block diagram of a conventional input/output control device. 51 ₁ ~ 51 _n ... Input terminal, 61 ₁ ~ 61 _n ...
Input terminal, 58 ₁ ~ 58 _n ... Output terminal, 67 ₁ ~
67 _n ...Output terminal, 56 ₁ to 56 _n ... First exclusive OR circuit, 66 ₁ to 66 _n ... Second exclusive OR circuit, 55... Register, 65... Logic circuit, 57...First buffer, 63...Second buffer, 53...Clock terminal, 62...Buffer control signal, 54...Buffer control signal terminal, 6
4 ₁ to 64m...Input terminal.

Claims (1)

[Scope of Claims] 1. A control unit located between the central processing unit and the plurality of peripheral devices, which temporarily stores input/output information between the central processing unit and each peripheral device in a memory and distributes it to each device; In an input/output control device consisting of a line correspondence section that is distributed for each peripheral device and communicates with the peripheral device, and a bus that connects the control section and the line correspondence section, data is exchanged between the control section and the line correspondence section. A register into which a predetermined identification code is written by the control unit corresponding to each line corresponding unit when transmitting and receiving, and a register corresponding to the number of bits of data output from the data output circuit of the control unit to the bus, Each bit of data is input to one input terminal, each output of the register is input to the other input terminal, and the first exclusive OR circuit group has an output terminal connected to the bus; a logic circuit that outputs the predetermined identification code for the bus; and a logic circuit for the number of bits of the data, each bit of the data on the bus is input to one input terminal, and a logic circuit to the other input terminal. An input/output control device comprising a second exclusive OR circuit group to which each output is input and whose output terminal is connected to a data input circuit of a control section.