JPH0398385A - Facsimile reply equipment - Google Patents

Facsimile reply equipment

Info

Publication number
JPH0398385A
JPH0398385A JP23643689A JP23643689A JPH0398385A JP H0398385 A JPH0398385 A JP H0398385A JP 23643689 A JP23643689 A JP 23643689A JP 23643689 A JP23643689 A JP 23643689A JP H0398385 A JPH0398385 A JP H0398385A
Authority
JP
Japan
Prior art keywords
data
facsimile
equipment
buffer
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23643689A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Mihashi
三橋 嘉之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23643689A priority Critical patent/JPH0398385A/en
Publication of JPH0398385A publication Critical patent/JPH0398385A/en
Pending legal-status Critical Current

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  • Facsimile Transmission Control (AREA)

Abstract

PURPOSE:To prevent mis-output of a data to other line by providing a bit replacement circuit for bit replacement with respect to a data sent/received to/from a buffer memory to a position of a terminal control section accessing the buffer memory. CONSTITUTION:The equipment is provided with a counter host interface section 1 sending/receiving a data between buffer memories 2-4 in the equipment and a host equipment and facsimile terminal control sections 5-7 sending/receiving a data between the buffer memories 2-4 and a facsimile equipment. Moreover, a bit replacement circuit is provided, which receives a picture signal data and a data line number at the position accessing the buffer memories 2-4 in the equipment and replaces the bit location in the picture signal data according to the predetermined algorithm in response to the inputted line number. Thus, even when a data is read from buffers of other line, no correct data is obtained, an output of a pattern recognized normally to the facsimile equipment is not outputted and mis-output of data to other line is prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はファクシミリ画信号を入力とし、ファクシミリ
端末との手順、画出力を複数回線の多重動作を行うファ
クシミリ応答装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a facsimile response device that receives a facsimile image signal as input, performs procedures with a facsimile terminal, and multiplexes image output over a plurality of lines.

〔従来の技術〕[Conventional technology]

従来のファクシミリ応答装置は、上位装置からキャラク
タコード情報或はファクシミリの画信号を受信し、コー
ド情報の場合は文字パタンに変換した後ファクシミリの
符号化を行い、画信号の場合は符号化方式の変換などを
行う。その後、回線に接続されたファクシミリ端末と通
信手順を進め前記の画信号を出力する。以上の動作を複
数回線の多重で行う。
Conventional facsimile answering devices receive character code information or facsimile image signals from a host device, convert the code information into character patterns, and then encode the facsimile, and in the case of image signals, convert the character code information or facsimile image signals into character patterns. Perform conversion, etc. Thereafter, the communication procedure is carried out with the facsimile terminal connected to the line, and the above-mentioned image signal is output. The above operations are performed by multiplexing multiple lines.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述したファクシミリ応答装置は、ファームウェアで構
成されており、内蔵されたプログラムに従ってマイクロ
コンピュータが装置内の各部の制御を行っている。上位
装置とは例えばGPIB等のバスによって接続され、こ
のバスを通して制御データ、画信号データ等を授受を行
う。例えば上位装置からバスを通して一定の大きさ(例
えば8Kバイト)を単位としたブロックのデータを受信
する。このデータは装置内部のメモリ上に回線対応に割
り当てられたバッファメモリに一旦格納される。その後
、ファクシミリ端末制御部がファク改り端末と手順をと
った後、前記バッファの中のデータを読み出しファクシ
ミリ端末に出力する。
The facsimile response device described above is configured with firmware, and a microcomputer controls each part within the device according to a built-in program. It is connected to the host device via a bus such as GPIB, and sends and receives control data, image signal data, etc. through this bus. For example, data in blocks of a certain size (for example, 8 Kbytes) is received from a host device via a bus. This data is temporarily stored in a buffer memory allocated to each line on the internal memory of the device. Thereafter, the facsimile terminal control section performs procedures with the facsimile terminal, and then reads out the data in the buffer and outputs it to the facsimile terminal.

上記のバッファは通信システムメモリ上に回線対応にア
ドレスを分割して割り当てられる。そのため、上位装置
からデータを受信する際、誤って他回線のバッファにデ
ータを格納したり、ファクシミリ端末に出力する際に他
回線のバッファがちデータを読み出したりすると、他回
線の内容のファクシミリ画面がそのまま出力されてしま
い、サービス上重大な問題となる。
The above-mentioned buffer is allocated on the communication system memory by dividing addresses into lines. Therefore, if you accidentally store data in the buffer of another line when receiving data from a host device, or read data that is not in the buffer of another line when outputting to a facsimile terminal, the facsimile screen of the contents of the other line may be If the data is output as is, it will cause a serious problem in terms of service.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のファクシミリ応答装置は、画信号データを記憶
する複数のバッファメモリと、このバッファメモリと上
位装置間とのデータ授受を行う対上位インタフェース部
と、前記バッファメモリとファクシミリ端末間とのデー
タの授受を行うファクシミリの端末制御部と、この端末
制御部のバッファメモリをアクセスする部位に前記バッ
ファメモリに送受するデータに対し、ビット入れ替えを
行うためのビット入れ替え回路を有している。
The facsimile response device of the present invention includes a plurality of buffer memories for storing image signal data, a host interface unit for transmitting and receiving data between the buffer memories and a host device, and a data exchange unit for transmitting and receiving data between the buffer memory and a facsimile terminal. A facsimile terminal control unit that performs transmission and reception, and a part of the terminal control unit that accesses the buffer memory include a bit replacement circuit for performing bit replacement for data sent to and received from the buffer memory.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

本実施例は、ファクシミリ画信号を入力とし、ファクシ
ミリ端末制御回路とこれを制御する制御回路とを有し、
ファクシミリ画信号を必要に応じて符号化方式の変換を
行いファクシミリ端末に出力する動作を複数回線の多重
で行う装置において、装置内のバッファメモリ2〜4と
上位装置間のデータの授受を行う対上位インタフェース
部1及びバッファメモリ2〜4とファクシミリ端末間の
データの授受を行うファクシミリ(FAX)端末制御部
5〜7と、装置内のバッファメモリ2〜4とアクセスす
る部位において、画信号データとそのデータの回線番号
とを入力とし、入力した回線番号に応じて、予め定めら
れたアルゴリズムに従って画信号データ内のビット位置
の入れ替えを行うビット入れ替え回路を有して構威され
る。
This embodiment receives a facsimile image signal as an input, and includes a facsimile terminal control circuit and a control circuit that controls the facsimile terminal control circuit.
In a device that performs the operation of converting the encoding method of a facsimile image signal as necessary and outputting it to a facsimile terminal by multiplexing multiple lines, this function is used to send and receive data between buffer memories 2 to 4 in the device and a host device. Facsimile (FAX) terminal control units 5 to 7, which exchange data between the upper interface unit 1 and buffer memories 2 to 4 and the facsimile terminal, and portions that access the buffer memories 2 to 4 in the device, transmit image signal data and The circuit is configured to include a bit switching circuit that receives the line number of the data as input and switches bit positions in the image signal data according to a predetermined algorithm according to the input line number.

次に、動作について第1図及び第2図を参照して説明す
ると、ファクシミリ応答装置は上位装置より対上位イン
タフェース部1を通して画信号データを受信する。この
とき対上位インタフェース部1は受信したデータ1バイ
トごとに、回線番号の中で“1″になっている部分に対
応する隠データ中のビットを入れ換えた後、その回線に
対応したバッファ2〜4に格納する。該当バッファのデ
ータをファクシミリ端末に出力する際には、まずファク
シミリ端末制御部5〜7がファクシミリ端末と通信手順
をたった後、バッファのデータを読みだしたデータ1バ
イト毎に、バッファ格納時に行ったと同じビット入れ替
え処理を行った後に、そのデータをファクシミリ端末に
送出する。
Next, the operation will be explained with reference to FIGS. 1 and 2. The facsimile response device receives image signal data from a host device through the host interface section 1. At this time, the upper-level interface unit 1 replaces the bits in the hidden data corresponding to the "1" part of the line number for each byte of received data, and then transfers the bits from the buffers 2 to 2 corresponding to the line. Store in 4. When outputting the data in the corresponding buffer to the facsimile terminal, the facsimile terminal controllers 5 to 7 first perform a communication procedure with the facsimile terminal, and then, for each byte of data read from the buffer, perform the same process as when storing the buffer. After performing the same bit permutation processing, the data is sent to the facsimile terminal.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、上位がら受信するデー
タを回線対応のバッファに格納する際、データのバイト
内ビット入れ替えを行い、バッファからデータを読みだ
す際にも同じバイト内ビット入れ替え処理を行うことに
より、誤ってっ他回線のバッファからデータを読みだし
た場合でも正しいデータが得られず、ファクシミリ端末
に対して正常に認識できる画面が出力されることは熊く
なり、他回線にデータの誤出力を防止できる効果がある
As explained above, the present invention performs bit swapping within a byte of data when storing data received from the higher order into a line-compatible buffer, and performs the same intra-byte bit swapping process when reading data from the buffer. By doing this, even if data is read from the buffer of another line by mistake, the correct data will not be obtained, and a screen that can be recognized normally will be output to the facsimile terminal. This has the effect of preventing erroneous output.

【図面の簡単な説明】[Brief explanation of drawings]

第l図は本発明の一実施例のブロック図、第2図は本実
施例のデータのバッファ格納・読みだし処理を示す図あ
る。 1・・・対上位装置インタフェース部、2〜4・・・回
線対応バッファメモリ、5〜7・・・回線対応ファクシ
ミリ制御部。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing the data buffer storage/reading process of this embodiment. DESCRIPTION OF SYMBOLS 1... Upper device interface unit, 2-4... Line compatible buffer memory, 5-7... Line compatible facsimile control unit.

Claims (1)

【特許請求の範囲】[Claims] 画信号データを記憶する複数のバッファメモリと、この
バッファメモリと上位装置間とのデータ授受を行う対上
位インタフェース部と、前記バッファメモリとファクシ
ミリ端末間とのデータの授受を行うファクシミリの端末
制御部と、この端末制御部のバッファメモリをアクセス
する部位に前記バッファメモリに送受するデータに対し
、ビット入れ替えを行うためのビット入れ替え回路を有
することを特徴とするファクシミリ応答装置。
A plurality of buffer memories for storing image signal data, a host interface section for transmitting and receiving data between the buffer memory and a host device, and a facsimile terminal control section for transmitting and receiving data between the buffer memory and a facsimile terminal. A facsimile response device characterized in that a part of the terminal control unit that accesses the buffer memory includes a bit switching circuit for switching bits of data sent to and received from the buffer memory.
JP23643689A 1989-09-11 1989-09-11 Facsimile reply equipment Pending JPH0398385A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23643689A JPH0398385A (en) 1989-09-11 1989-09-11 Facsimile reply equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23643689A JPH0398385A (en) 1989-09-11 1989-09-11 Facsimile reply equipment

Publications (1)

Publication Number Publication Date
JPH0398385A true JPH0398385A (en) 1991-04-23

Family

ID=17000728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23643689A Pending JPH0398385A (en) 1989-09-11 1989-09-11 Facsimile reply equipment

Country Status (1)

Country Link
JP (1) JPH0398385A (en)

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