JP2676820B2 - Multiplex facsimile signal processor - Google Patents

Description

The present invention relates to a multiplex facsimile signal processing apparatus for performing line multiplex processing.

[Conventional technology]

A character code output from a device such as a host computer cannot be directly transmitted to a facsimile device. Therefore, in such a case, the facsimile signal processing device converts the character code into a facsimile image signal and transmits it to the facsimile device.

FIG. 3 shows an example of a conventionally used multiplex facsimile signal processing apparatus. In this multiplex facsimile signal processing device, the following circuits or devices are connected to the shared bus 11.

(I) Processor circuit 12: A CPU (central processing unit) is configured to perform various controls using a program stored in a built-in ROM (read only memory).

(Ii) Character pattern generation circuit 13: a circuit for generating a character pattern based on the supplied character code.

(Iii) Facsimile coding circuit 14: a circuit for coding a character pattern and compressing it to create a facsimile signal.

(Iv) Shared memory 15: Composed of a RAM (random access memory), and a part of the area is allocated as an image signal buffer memory 16 for temporarily storing a facsimile image signal.

(V) Parallel / serial conversion circuits 17: Parallel / serial conversion circuits 17-1 to 17-1 corresponding to the number of lines
17-N are provided, and the modulation circuit 18-1 is provided in each.
~ 18-N are connected. The facsimile image signals modulated by the modulation circuits 18-1 to 18-N are transmitted to the corresponding facsimile device (not shown).

In the conventional multiplex facsimile signal processing device having such a configuration, the character code received from the outside is input to the character pattern generation circuit 13, and the character pattern output from this is edited line by line. The edited image data is input to the facsimile encoding circuit 14 and encoded. The encoded facsimile signal is temporarily stored in the image signal buffer memory 16, and then the parallel / serial conversion circuit.
It is supplied to the corresponding one of 17-1 to 17-N, and is output to a line (not shown) via the modulation circuit 18.

In this multiplex facsimile signal processing device, a parallel / serial conversion circuit 17 is provided corresponding to the number of lines to be processed.
Although the -1 to 17-N and the modulation circuits 18-1 to 18-N are required, the processor circuit 12, the character pattern generation circuit 13 and the facsimile encoding circuit 14 are shared by one. Further, the shared memory 15 uses the image signal buffer memory 16 by dividing the area for each line and uses the hardware resources effectively.

[Problems to be solved by the invention]

By the way, in such a multiplex facsimile signal processing apparatus, if the apparatus performs an abnormal operation or a hardware failure occurs due to a software defect, the management of the image signal buffer memory may be abnormal. In such a case, a part or all of the facsimile image signal prepared for a certain line is written in the memory area for another line, or the facsimile image signal stored in the memory area for another line is In some cases, some or all could be read by mistake. In such a case,
A facsimile image signal will be transmitted to the wrong party, and there is a risk that a confidential information leakage accident will occur especially in the case of a document requiring confidentiality protection.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multiplex facsimile signal processing device which prevents a receiver from correctly reproducing an image when a facsimile image signal is sent to the wrong line.

[Means for solving the problem]

In the present invention, (i) a character pattern generation circuit for inputting a character code and outputting a character pattern, and (ii) an image editing circuit for editing the character pattern output by the character pattern generation circuit and outputting a document image. (Iii) an encoding circuit that encodes the image edited by the image editing circuit into a facsimile image signal, and (iv) a buffer memory that temporarily stores the facsimile image signal,
(V) When writing and reading a facsimile image signal to and from this buffer memory, a data bit is executed so that a bit exchange unique to each line is performed in the opposite direction between writing and reading in units of each data word. The replacement means is provided in the multiplex facsimile signal processing apparatus.

That is, according to the present invention, the data bit exchange means performs different bit exchange for each line in data units and stores the result in the buffer memory. Then, when the facsimile image signal is transmitted, the bits corresponding to the line are exchanged again, the original bit arrangement is restored, and then the signal is transmitted to the destination line. In this way, when a facsimile image signal is sent to the wrong line, the bit swapping performed when writing to the buffer memory does not correspond to the bit swapping performed when reading, and the bit array of the code is restored. Absent. Therefore, in such a case, the image cannot be correctly reproduced when it is decoded at the receiving end, and it is possible to prevent the image from leaking between the lines.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to examples.

FIG. 1 shows an outline of a circuit configuration of a multiplex facsimile signal processing apparatus according to an embodiment of the present invention.
In FIG. 1, the same parts as those in FIG. 3 are designated by the same reference numerals,
These descriptions will be omitted as appropriate.

In this multiplex facsimile signal processing apparatus, the first bit exchange circuit 21 is arranged between the facsimile encoding circuit 14 and the shared bus 11, and the data encoded by the facsimile encoding circuit 14 is word by word. Bits are swapped. The mode of bit exchange is different for each line. The exchanged facsimile image signal thus created is stored in the image signal buffer memory 16 for each line.

On the other hand, between the parallel / serial conversion circuits 17-1 to 17-N and the shared bus 11 which are prepared in the number corresponding to the lines, the second bit replacement circuits 22-1 to 22-N are respectively arranged. There is. The facsimile image signal read out from the image signal buffer memory 16 has the second bit replacement circuits 22-1 to 22-2.
Bits are input to a circuit corresponding to the line to be sent out of -N, and bit exchange is performed here so that the bit exchange processing in the direction opposite to the bit exchange processing of the first bit exchange circuit 21 is performed. The facsimile image signal after bit replacement is converted into serial data by the parallel / serial conversion circuits 17-1 to 17-N, modulated by the modulation circuits 18-1 to 18-N, and sent to the target line.

FIG. 2 is for explaining the operation of bit exchange in the multiplex facsimile signal processing apparatus of this embodiment. Dozui shows the one-word data outputted from the facsimile coding circuit 14 (FIG. 1) (a ₀ ~a _7). This coded facsimile image signal for a certain line X is subjected to a bit changing process for this line X by the first bit changing circuit 21 (FIG. 2B). That is, in this example, the bit a ₁ is moved to the position of the bits a _4, bits a ₄ is moved to the position of the bit a _1. The word data subjected to the replacement processing in this manner is stored in the area for the line X of the image signal buffer memory 16. In reality, such an operation is sequentially repeated in word units.

On the other hand, the transmission of data to the line is executed by sequentially reading data from the image signal buffer memory 16 in word units. For example, line X (X is an arbitrary value)
In the case of a facsimile image signal to be sent to, the area for the line X of the image signal buffer memory 16 or the read word data (Fig. 2B) is supplied to the parallel / serial conversion circuit 17 for this line. Then, the bit swapping process is performed so that the operation is reverse to that of the first bit swapping circuit 21. That is, in the case of this line X, the processing for returning the bit a _{4 at} the position where the bit a ₁ should be returned to the original position, and the bit a ₄
Is performed such that the bit a _{1 at} the position to be returned to the original position returns to the original position (Fig. 2C). As a result, the word data shown in A of the figure and the word data shown in C of the figure completely match, and the image is reproduced correctly on the receiving side.

On the other hand, when the word data is erroneously written in an area other than the original area of the buffer memory or is erroneously read from another area, the word data in the state shown in FIG. It will be different from the word data shown in FIG. Therefore, even if this is sent to the line, the receiving side cannot reproduce it as a correct image after decoding.

〔The invention's effect〕

As described above, according to the present invention, since the bit swapping process is performed on the encoded image signal, the processing amount is smaller than that of the similar process on the unencoded image signal, and it is simple. It is possible to effectively prevent leakage of images between lines by performing various operations.

[Brief description of the drawings]

1 and 2 are for explaining one embodiment of the present invention, in which FIG. 1 is a block diagram showing a main part of a multiplex facsimile signal processing apparatus, and FIG.
FIG. 3 is an explanatory view showing a state of bit swapping processing of the bit swapping circuit when the operation of the apparatus is normally performed, and FIG. 3 is a block diagram showing a main part of a conventionally used multiplex facsimile signal processing apparatus. 12 ... Processor circuit, 13 ... Character pattern generation circuit, 14 ... Facsimile encoding circuit, 16 ... Buffer memory, 21 ... First bit replacement circuit, 221-222-N ... Second bit replacement circuit circuit.

Claims (1)

(57) [Claims] 1. A character pattern generating circuit for inputting a character code and outputting a character pattern, an image editing circuit for editing the character pattern output by the character pattern generating circuit and outputting a document image, and the image editing circuit. An encoding circuit that encodes the image edited by to make a facsimile image signal, a buffer memory that temporarily stores this facsimile image signal, and a data word when writing and reading the facsimile image signal to and from this buffer memory. A multi-facsimile signal processing apparatus, comprising, as a unit, data bit swapping means for performing bit swapping unique to each line so as to perform swap operations in opposite directions at the time of writing and reading.