JPH0476054U - - Google Patents
Info
- Publication number
- JPH0476054U JPH0476054U JP12058490U JP12058490U JPH0476054U JP H0476054 U JPH0476054 U JP H0476054U JP 12058490 U JP12058490 U JP 12058490U JP 12058490 U JP12058490 U JP 12058490U JP H0476054 U JPH0476054 U JP H0476054U
- Authority
- JP
- Japan
- Prior art keywords
- surface mount
- utility
- scope
- registration request
- connection terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第1図はこの考案の一実施例である表面実装用
ICを示す断面図、第2図は第1図の表面実装用
ICの底面図、第3図はこの考案の一実施例によ
る表面実装用ICを複数個実装した時の上面図、
第4図は従来の表面実装用ICを示す断面図、第
5図は従来の表面実装用ICを複数個実装した時
の上面図である。 図において、1はチツプ、2はモールド、3は
ワイヤ、4は内部リード、5は金属パターン、6
は実装基板、8は半田、9は接続端子、10はI
Cを示す。なお、図中、同一符号は同一、又は相
当部分を示す。
ICを示す断面図、第2図は第1図の表面実装用
ICの底面図、第3図はこの考案の一実施例によ
る表面実装用ICを複数個実装した時の上面図、
第4図は従来の表面実装用ICを示す断面図、第
5図は従来の表面実装用ICを複数個実装した時
の上面図である。 図において、1はチツプ、2はモールド、3は
ワイヤ、4は内部リード、5は金属パターン、6
は実装基板、8は半田、9は接続端子、10はI
Cを示す。なお、図中、同一符号は同一、又は相
当部分を示す。
Claims (1)
- IC底面に半田付け可能な金属で底面と同一面
上に接続端子を備えたことを特徴とする表面実装
用IC。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12058490U JPH0476054U (ja) | 1990-11-15 | 1990-11-15 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12058490U JPH0476054U (ja) | 1990-11-15 | 1990-11-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0476054U true JPH0476054U (ja) | 1992-07-02 |
Family
ID=31868483
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12058490U Pending JPH0476054U (ja) | 1990-11-15 | 1990-11-15 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0476054U (ja) |
-
1990
- 1990-11-15 JP JP12058490U patent/JPH0476054U/ja active Pending