JPH0474474A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0474474A
JPH0474474A JP18911490A JP18911490A JPH0474474A JP H0474474 A JPH0474474 A JP H0474474A JP 18911490 A JP18911490 A JP 18911490A JP 18911490 A JP18911490 A JP 18911490A JP H0474474 A JPH0474474 A JP H0474474A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
region
conductivity type
drain
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18911490A
Other languages
Japanese (ja)
Other versions
JP2713496B2 (en
Inventor
Yuji Yamanishi
山西 雄司
Hiroshi Tanida
宏 谷田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP2189114A priority Critical patent/JP2713496B2/en
Publication of JPH0474474A publication Critical patent/JPH0474474A/en
Application granted granted Critical
Publication of JP2713496B2 publication Critical patent/JP2713496B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To incorporate a device for surge protection without increasing a chip area, by making the thickness of a semiconductor substrate to thickness so that a depletion layer can easily get to the first conductive-type region under a semiconductor substrate. when the reverse voltage is impressed between a source and a drain. CONSTITUTION:The first conductive-type region 8 with higher concentration of impurities than that of a semiconductor substrate 2 is installed under the semiconductor substrate 2. When the reverse voltage is impressed between a drain substrate 10 and a source electrode 11, a depletion layer 12 spreads between an expanded drain region 5 and a semiconductor substrate 2, and finally gets to the first conductive-type region 8 under the semiconductor substrate 2. Expansion of the depletion layer 12 to the downward direction is restrained here, and the electric field at the junction of the bottom part of the expanded drain region 5 increases, and here the yield generates. The yield electric current flows to the arrow direction, as shown in the Fig. 2, and parasitic bi-polar transistor movement does not occur.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はイグナイタ用のパワー素子として使用する半導
体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device used as a power element for an igniter.

従来の技術 サージ対策用として用いられる半導体装置として代表的
なものにサージ保護用ダイオードがあり、以下従来の半
導体装置についてサージ保護用ダイオードを例として説
明する。
BACKGROUND OF THE INVENTION A typical semiconductor device used as a surge countermeasure is a surge protection diode, and the conventional semiconductor device will be described below using a surge protection diode as an example.

MOSFETをスイッチング素子としてイグナイタに使
用する場合のスイッチ部は第3図に示すようにMO8F
ET22のドレイン−ソース間にサージ保護用ダイオー
ド23が必要である。同図において、24は発火点、2
5はイグニッションコイルである。従来はこのようなサ
ージ保護ダイオードを集積回路の外で付加するいわゆる
外付けで使用していた。
When using MOSFET as a switching element in an igniter, the switch part is MO8F as shown in Figure 3.
A surge protection diode 23 is required between the drain and source of the ET 22. In the same figure, 24 is the ignition point, 2
5 is an ignition coil. Conventionally, such surge protection diodes have been used as so-called external devices added outside the integrated circuit.

発明が解決しようとする課題 まず最初にサージ保護用ダイオードを必要とする理由に
ついて説明する。
Problems to be Solved by the Invention First, the reason why a surge protection diode is required will be explained.

第4図(a)はイグナイタのMOSFETにサージ保護
用ダイオードがない場合の動作特性図、同図(b)はイ
グナイタのMOSFETにサージ保護用ダイオードを取
り付けた場合の動作特性図である。
FIG. 4(a) is an operating characteristic diagram when the igniter MOSFET does not have a surge protection diode, and FIG. 4(b) is an operating characteristic diagram when the igniter MOSFET is equipped with a surge protection diode.

第4図(a)に示すように、サージ保護用ダイオードが
ない場合、MO8FET22が動作状態26から停止状
態27に移る瞬間に正のサージ電圧32が発生する。こ
の場合サージ保護用ダイオードがないためサージ電圧3
2がMO3FET22のドレイン−ソース間の降伏電圧
28より高くなり、MO8FET22はドレイン−ソー
ス間て降伏する。
As shown in FIG. 4(a), if there is no surge protection diode, a positive surge voltage 32 is generated at the moment the MO8FET 22 changes from the operating state 26 to the stopped state 27. In this case, there is no surge protection diode, so the surge voltage is 3.
2 becomes higher than the drain-source breakdown voltage 28 of the MO3FET 22, and the MO8FET 22 breaks down between the drain and source.

一方第4図(b)に示すように、サージ保護用ダイオー
ド23を取り付けた場合はMO3FET22が動作状態
29から停止状態30に移る瞬間に正のサージ電圧33
が発生するが、そのサージ電圧33はサージ保護用ダイ
オードの働きでトレインソース間の降伏電圧31より高
(なることはない。
On the other hand, as shown in FIG. 4(b), when the surge protection diode 23 is installed, a positive surge voltage 33 is generated at the moment the MO3FET 22 changes from the operating state 29 to the stopped state 30.
However, the surge voltage 33 is higher than the breakdown voltage 31 between the train and source due to the function of the surge protection diode (it never becomes higher).

次にサージ保護用ダイオードがないときのMO8FET
22の内部の様子を第5図に沿って説明する。図に示す
ようにMO5FET22は第1導電形の半導体基板41
中に形成された第2導電形のソース領域42と第2導電
形のドレインコンタクト領域43との間に前記ドレイン
コンタクト領域43に接して第2導電形の延長ドレイン
領域44が形成され、この延長ドレイン領域44とソー
ス領域42との間の前記半導体基板41の表面をチャネ
ルとし、このチャネル領域の上にゲート酸化膜45を介
してゲート電極46が形成されたものである。なお、4
7は半導体基板41と接続するための基板コンタクト領
域、48はドレイン電極、49はソース電極である。こ
のようなMO3FET22のドレインコンタクト領域4
3からソース領域42に降伏電流が流れたとき、半導体
基板41の抵抗成分50による電位差か発生する。
Next, MO8FET when there is no surge protection diode
The inside of 22 will be explained with reference to FIG. As shown in the figure, the MO5FET 22 is connected to a semiconductor substrate 41 of the first conductivity type.
A second conductivity type extended drain region 44 is formed in contact with the drain contact region 43 between a second conductivity type source region 42 and a second conductivity type drain contact region 43 formed therein. The surface of the semiconductor substrate 41 between the drain region 44 and the source region 42 is used as a channel, and a gate electrode 46 is formed on this channel region with a gate oxide film 45 interposed therebetween. In addition, 4
7 is a substrate contact region for connection to the semiconductor substrate 41, 48 is a drain electrode, and 49 is a source electrode. The drain contact region 4 of such MO3FET 22
When a breakdown current flows from the source region 3 to the source region 42, a potential difference is generated due to the resistance component 50 of the semiconductor substrate 41.

この電位差によって寄生バイポーラトランジスタ51が
動作し、温度上昇を引き起こして熱破壊に至ることがあ
る。
This potential difference causes the parasitic bipolar transistor 51 to operate, causing a temperature rise, which may lead to thermal breakdown.

本発明は上記従来の課題を解決するもので、MOSFE
Tと同一チップ内に工程を追加することなく内蔵させる
ことのできる優れたサージ保護用の半導体装置を提供す
ることを目的とする。
The present invention solves the above-mentioned conventional problems.
It is an object of the present invention to provide an excellent semiconductor device for surge protection that can be built into the same chip as T without any additional steps.

課題を解決するための手段 この目的を達成するために本発明の半導体装置は、基本
的には第1導電形の半導体基板中に形成された横型MO
3FETであって、半導体基板の下に半導体基板よりも
不純物濃度の高い第1導電形の領域を有し、ソース領域
は半導体基板に接続され、かつ半導体基板の厚さをソー
ス−ドレイン間に逆電圧が印加されたときに空乏層が容
易に半導体基板下の第1導電形の領域に達する厚さとし
た構成を有している。
Means for Solving the Problems To achieve this object, the semiconductor device of the present invention basically consists of a lateral MO formed in a semiconductor substrate of a first conductivity type.
3FET, which has a first conductivity type region with higher impurity concentration than the semiconductor substrate under the semiconductor substrate, the source region is connected to the semiconductor substrate, and the thickness of the semiconductor substrate is reversed between the source and drain. The structure has a thickness such that the depletion layer easily reaches the first conductivity type region under the semiconductor substrate when a voltage is applied.

作用 この構成によって、従来イグナイタ用スイッチング素子
としてのMOSFETのソース−ドレイン間に外付けし
ていたサージ保護用の半導体装置をMOSFETのチッ
プ内にチップ面積を増加させることなく内蔵させること
ができる。
Effect: With this configuration, a semiconductor device for surge protection, which has conventionally been externally attached between the source and drain of a MOSFET as a switching element for an igniter, can be built into the MOSFET chip without increasing the chip area.

実施例 以下本発明の一実施例について、図面を参照しながら説
明する。
EXAMPLE An example of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例における半導体装置の断面図
である。
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

本発明の実施例の横型MO3FETIは第1導電形の半
導体基板2中に形成された第2導電形のソース領域3と
第2導電形のトレインコンタクト領域4との間に前記ド
レインコンタクト領域4に接して第2導電形の延長ドレ
イン領域5が形成され、この延長ドレイン領域5とソー
ス領域3との間の半導体基板2の表面をチャネル領域と
し、このチャネル領域の上にゲート酸化膜6を介してゲ
ート電極7が形成され、かつ半導体基板2の下に半導体
基板2よりも不純物濃度の高い第1導電形の領域8を設
けたものである。なお、9は半導体基板2と接続するた
めの基板コンタクト領域、10はドレイン電極、11は
ソース電極である。
The lateral MO3FETI of the embodiment of the present invention has a drain contact region 4 between a second conductivity type source region 3 formed in a first conductivity type semiconductor substrate 2 and a second conductivity type train contact region 4. An extended drain region 5 of the second conductivity type is formed in contact with the extended drain region 5. The surface of the semiconductor substrate 2 between the extended drain region 5 and the source region 3 is used as a channel region, and a gate oxide film 6 is formed on the channel region. A gate electrode 7 is formed therein, and a first conductivity type region 8 having a higher impurity concentration than the semiconductor substrate 2 is provided below the semiconductor substrate 2. Note that 9 is a substrate contact region for connection to the semiconductor substrate 2, 10 is a drain electrode, and 11 is a source electrode.

本実施例では、半導体基板2の不純物濃度は3×101
4cm″3、半導体基板2下の第1導電形の領域8の不
純物濃度はI X 1019側−3、延長ドレイン領域
5の不純物濃度は約3×10151015cとした。ま
た半導体基板2の厚さは、ドレイン−半導体基板間の降
伏電圧を400Vとするために15μmとした。
In this embodiment, the impurity concentration of the semiconductor substrate 2 is 3×101
4 cm''3, the impurity concentration of the first conductivity type region 8 under the semiconductor substrate 2 was set to IX1019 side -3, and the impurity concentration of the extended drain region 5 was set to approximately 3×10151015c.The thickness of the semiconductor substrate 2 was In order to set the breakdown voltage between the drain and the semiconductor substrate to 400V, the thickness was set to 15 μm.

このように構成された半導体装置において、ドレイン−
ソース間に逆電圧が印加されたときの空乏層12の広が
りを第2図に示した。ドレイン電極10とソース電極1
1との間に逆電圧が印加されると空乏層12は延長ドレ
イン領域5と半導体基板2の間に広がり、ついには半導
体基板2の下の第1導電形の領域8に達する。空乏層1
2の下方向への広がりはここで抑えられ、延長トレイン
領域5の底部の接合での電界が高くなり、ここで降伏が
生じる。このときの降伏電流は第2図の矢印の方向に流
れ、寄生バイポーラトランジスタ動作は起こらない。な
お、半導体基板2の下に第1導電形の領域8がない場合
のMOSFETの降伏電圧は450Vであり、トレイン
−半導体基板間の降伏電圧を400VとすることでMO
SFETの破壊が防止される。
In the semiconductor device configured in this way, the drain
FIG. 2 shows the expansion of the depletion layer 12 when a reverse voltage is applied between the sources. Drain electrode 10 and source electrode 1
1, the depletion layer 12 spreads between the extended drain region 5 and the semiconductor substrate 2, and finally reaches the region 8 of the first conductivity type below the semiconductor substrate 2. depletion layer 1
The downward spread of 2 is now suppressed and the electric field at the junction at the bottom of the extended train region 5 becomes high, where breakdown occurs. At this time, the breakdown current flows in the direction of the arrow in FIG. 2, and no parasitic bipolar transistor operation occurs. Note that the breakdown voltage of the MOSFET when there is no region 8 of the first conductivity type under the semiconductor substrate 2 is 450V, and by setting the breakdown voltage between the train and the semiconductor substrate to 400V, the MOSFET
Destruction of SFET is prevented.

発明の効果 以上のように本発明は、横型MO8FETが形成された
第1導電形の半導体基板の下に半導体基板よりも不純物
濃度の高い第1導電形の領域を設け、ソース領域は半導
体基板に接続し、かつ半導体基板の厚さをソース−ドレ
イン間に逆電圧が印加されたときに空乏層が容易に半導
体基板下の第1導電形の領域に達する厚さとするこおに
より、MOSFETと同一チップ内に工程を追加するこ
となく内蔵させることのできる優れたサージ保護用の半
導体装置を実現できるものである。
Effects of the Invention As described above, the present invention provides a region of the first conductivity type with a higher impurity concentration than the semiconductor substrate under the semiconductor substrate of the first conductivity type on which the lateral MO8FET is formed, and a source region is formed on the semiconductor substrate. By connecting and making the thickness of the semiconductor substrate such that the depletion layer easily reaches the region of the first conductivity type under the semiconductor substrate when a reverse voltage is applied between the source and drain, it can be made the same as a MOSFET. It is possible to realize an excellent semiconductor device for surge protection that can be built into a chip without adding any additional steps.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例における半導体装置の断面図
、第2図は同半導体装置のトレイン−ソース間に逆電圧
を印加したときの空乏層の広がりを示す図、第3図はM
OSFETをスイッチング素子としてイグナイタに使用
した場合の回路図、第4図(a)はイグナイタにサージ
保護用ダイオードがない場合の動作特性図、第4図(b
)はイグナイタにサージ保護用ダイオードを取り付けた
場合の動作特性図、第5図はサージ保護用ダイオードが
ないときに降伏電流が流れた場合のMOSFETの内部
の状態を示す図である。 2・・・・・・半導体基板、3・・・・・・ソース領域
、4・・・・・・ドレインコンタクト領域、5・・・・
・・延長ドレイン領域、6・・・・・・ゲート酸化膜、
7・・・・・・ゲート電極、8・・・・・・半導体基板
の下の第1導電形の領域、12・・・・・・空乏層。 代理人の氏名 弁理士 粟野重孝 ほか1名第4図 1・ 2g 千 第 51Y]
FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram showing the spread of the depletion layer when a reverse voltage is applied between the train and source of the semiconductor device, and FIG.
Figure 4 (a) is a circuit diagram when an OSFET is used as a switching element in an igniter, and Figure 4 (b) is an operating characteristic diagram when the igniter does not have a surge protection diode.
) is an operating characteristic diagram when a surge protection diode is attached to the igniter, and FIG. 5 is a diagram showing the internal state of the MOSFET when a breakdown current flows when there is no surge protection diode. 2...Semiconductor substrate, 3...Source region, 4...Drain contact region, 5...
... Extended drain region, 6... Gate oxide film,
7...Gate electrode, 8...Region of the first conductivity type under the semiconductor substrate, 12...Depletion layer. Name of agent: Patent attorney Shigetaka Awano and one other person Figure 4, 1, 2g, 1000th 51Y]

Claims (1)

【特許請求の範囲】[Claims]  第1導電形の半導体基板中に形成された第2導電形の
ソース領域と第2導電形のドレインコンタクト領域との
間に前記ドレインコンタクト領域に接して第2導電形の
延長ドレイン領域を有し、この延長ドレイン領域と前記
ソース領域との間の前記半導体基板表面をチャネルとし
、このチャネル領域の上にゲート酸化膜を介してゲート
電極を有する半導体装置であって、前記第1導電形の半
導体基板の下に不純物濃度が前記半導体基板より高い第
1導電形の領域を有し、ソース領域が前記半導体基板と
接続され、かつ前記半導体基板の厚さをドレインとソー
スの間に逆電圧を印加したときに広がる空乏層が前記半
導体基板の下の第1導電形の領域に容易に達する厚さと
したことを特徴とする半導体装置。
a second conductivity type source region and a second conductivity type drain contact region formed in a first conductivity type semiconductor substrate; a second conductivity type extended drain region in contact with the drain contact region; , a semiconductor device having a channel in the surface of the semiconductor substrate between the extended drain region and the source region, and having a gate electrode on the channel region via a gate oxide film, the semiconductor device having the semiconductor of the first conductivity type; A region of a first conductivity type having an impurity concentration higher than that of the semiconductor substrate is provided under the substrate, a source region is connected to the semiconductor substrate, and a reverse voltage is applied between the drain and the source to reduce the thickness of the semiconductor substrate. 1. A semiconductor device characterized in that the thickness of the depletion layer is such that when the depletion layer expands, it easily reaches a region of the first conductivity type below the semiconductor substrate.
JP2189114A 1990-07-16 1990-07-16 Semiconductor device Expired - Fee Related JP2713496B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2189114A JP2713496B2 (en) 1990-07-16 1990-07-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2189114A JP2713496B2 (en) 1990-07-16 1990-07-16 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0474474A true JPH0474474A (en) 1992-03-09
JP2713496B2 JP2713496B2 (en) 1998-02-16

Family

ID=16235616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2189114A Expired - Fee Related JP2713496B2 (en) 1990-07-16 1990-07-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2713496B2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57123726A (en) * 1981-01-23 1982-08-02 Hitachi Ltd Mis semiconductor device
JPS59100570A (en) * 1982-11-30 1984-06-09 Nissan Motor Co Ltd Mos transistor
JPS61116876A (en) * 1985-11-15 1986-06-04 Hitachi Ltd Large power insulated gate field effect semiconductor device
JPH0198262A (en) * 1987-10-12 1989-04-17 Nec Corp Insulated gate field-effect transistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57123726A (en) * 1981-01-23 1982-08-02 Hitachi Ltd Mis semiconductor device
JPS59100570A (en) * 1982-11-30 1984-06-09 Nissan Motor Co Ltd Mos transistor
JPS61116876A (en) * 1985-11-15 1986-06-04 Hitachi Ltd Large power insulated gate field effect semiconductor device
JPH0198262A (en) * 1987-10-12 1989-04-17 Nec Corp Insulated gate field-effect transistor

Also Published As

Publication number Publication date
JP2713496B2 (en) 1998-02-16

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