JPH0474426A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0474426A JPH0474426A JP18991690A JP18991690A JPH0474426A JP H0474426 A JPH0474426 A JP H0474426A JP 18991690 A JP18991690 A JP 18991690A JP 18991690 A JP18991690 A JP 18991690A JP H0474426 A JPH0474426 A JP H0474426A
- Authority
- JP
- Japan
- Prior art keywords
- nitride film
- plasma nitride
- vacuum
- degree
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims abstract description 38
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 14
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 6
- 230000002159 abnormal effect Effects 0.000 abstract description 15
- 239000012212 insulator Substances 0.000 abstract description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法に係り、さらに詳し
くは、プラズマ窒化膜の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a plasma nitride film.
第５図は、例えば従来のＰチャネル型アルミゲ１、 Ｍ
ＯＳ ）ランジスタを示す断面図であり、この図にお
いて、１はアルミ配線、２はプラズマ窒化膜、３はフィ
ールド酸化膜、４はゲート酸化膜、５はＰ＋ソース・ド
レイン領域、６はＮ基板である。また、第２図はプラズ
マ窒化膜を形成するためのシーケンスであり、第３図は
プラズマＣＶＤ装置の簡易配管図であるが、これらは後
述するこの発明の詳細な説明でも用いるものである。FIG. 5 shows, for example, a conventional P-channel type aluminum gate 1, M
OS) This is a cross-sectional view showing a transistor. In this figure, 1 is an aluminum wiring, 2 is a plasma nitride film, 3 is a field oxide film, 4 is a gate oxide film, 5 is a P+ source/drain region, and 6 is an N substrate. be. Further, FIG. 2 shows a sequence for forming a plasma nitride film, and FIG. 3 shows a simplified piping diagram of a plasma CVD apparatus, which will also be used in the detailed explanation of the invention to be described later.
次に、動作について説明する。Next, the operation will be explained.
第５図のプラズマ窒化膜２を生成するために、第３図の
プラズマＣＶＤ装置で、例えば炉温を３００℃、真空度
を２．５Ｔｏｒｒにして、ＳｉＨ４゜ＮＨ，ガスを流し
、ＲＦによるグロー放電を行う。In order to generate the plasma nitride film 2 shown in FIG. 5, in the plasma CVD apparatus shown in FIG. Perform discharge.
これは第２図のプラズマ窒化膜生成ンーケンスでいうと
、各ステップを経た後の“デボ生成“、つまりプラズマ
窒化膜２をデポジションするステップに当たる。この“
デボ生成パステップの前後には、第２図のように、′ボ
ートのローディング−“荒引き”−“高真空引き”−“
リークチエツク”→“炉温安定”→“ＲＦパワーチエツ
ク”→“高真空引き”−“デポ真空度設定”のステップ
や“高真空引き”−“バックフィル”−“ボートのアン
ローディングという各ステップがある。In the plasma nitride film production sequence shown in FIG. 2, this corresponds to the "debo formation" after each step, that is, the step of depositing the plasma nitride film 2. this"
Before and after the debo generation step, as shown in Fig.
Leak check → Furnace temperature stabilization → RF power check → High vacuum → Depot vacuum level setting and high vacuum → Backfill → Boat unloading. There is.
従来の半導体装置のプラズマ窒化膜２の生成は以上のよ
うな方法で形成されているので、例えば３００℃（比較
的低温） 、 ２．５Ｔｏｒｒ （比較的真空度が悪い
）で処理する場合、アルミ面積の広い部分（例えばＡ／
ターゲットｅｔｃ）領域や乙の領域の周辺部に“局部的
異常放電”の発生をもたらすことがあるという問題点が
あった。Since the plasma nitride film 2 of conventional semiconductor devices is formed by the method described above, for example, when processing at 300°C (relatively low temperature) and 2.5 Torr (relatively poor vacuum), aluminum Large areas (e.g. A/
There is a problem in that "local abnormal discharge" may occur in the periphery of the target etc. region or the region B.
この発明は、上記のような問題点を解消するためになさ
れたもので、アルミ面積の広い部分や、この領域の周辺
部に“局部的異常放電”の発生しない半導体装置の製造
方法を提供することを目的とする。This invention was made in order to solve the above-mentioned problems, and provides a method for manufacturing a semiconductor device in which "local abnormal discharge" does not occur in a large area of aluminum or in the periphery of this area. The purpose is to
この発明に係る半導体装置の製造方法は、プラズマ窒化
膜のデポレション生成ステップで、真空度２ Ｔｏｒｒ
未濁で第１のプラズマ窒化膜を１００〜３０００大にデ
ポジションし、その後、真空度２Ｔｏｒｒ以上で第２の
プラズマ窒化膜をデポジションするものである。In the method for manufacturing a semiconductor device according to the present invention, in the plasma nitride film deposition step, the vacuum level is 2 Torr.
A first plasma nitride film is deposited to a thickness of 100 to 3,000 in an unturbid state, and then a second plasma nitride film is deposited at a vacuum degree of 2 Torr or more.
この発明においては、問題となる“″局部的異常放電”
は、半導体装置のＡｌ領域との界面部にて発生するので
、Ａｌ領域との界面部とのデボ生成をまず真空度２ Ｔ
ｏｒｒ未渦の“′局部的異常放電“の発生しない条件で
デポジションすることで第１のプラズマ窒化膜、いわば
絶縁体が形成され、この絶縁体のため、その後、真空度
２ Ｔｏｒｒ以上において第２のプラズマ窒化膜を形成
しても異常なグロ放電は抑えられる。In this invention, the problematic "local abnormal discharge"
Since this occurs at the interface with the Al region of the semiconductor device, the formation of the deposit at the interface with the Al region is first performed at a vacuum level of 2 T.
The first plasma nitride film, so to speak, an insulator, is formed by deposition under conditions that do not cause "local abnormal discharge" with no vortices. Even if the plasma nitride film of 2 is formed, abnormal glow discharge can be suppressed.
以下、この発明の一実施例を図面について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図はこの発明による半導体装置の一実施例を示す断
面図である。第１図において、１はアルミ配線、２−１
は局部的異常放電を発生しない条件、すなわち真空度２
Ｔｏｒｒ以下、例えば１．５ Ｔｏｒｒてデポジション
した第１のプラズマ窒化膜、２２はこの第１プラズマ窒
化膜２−１の上に、真空度２ Ｔｏｒｒ以上、例えば２
，５Ｔｏｒｒでデポジションした第２のプラズマ窒化膜
、３はフィールド酸化膜、４はゲート酸化膜、５はＰ＋
ソース・ドレイン領域、６はＮ基板である、また、第２
図は、第１図の第１．第２のプラズマ窒化膜２−１およ
び２−２を生成するためのシーケンスである。また、第
３図は第１．第２のプラズマ窒化膜２−１８よび２−２
を生成するためのプラズマＣＶＤ装置の簡易配管図であ
る。第３図において、１１はノーマリクローズエアバル
ブ、１２はノーマリオープンエアバルブ、１３は流量計
、１４はロータリポンプ、１５はブローワポンプ、１６
は石英チュブ、１７はマスフローコントローラである。FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. In Figure 1, 1 is aluminum wiring, 2-1
is the condition that local abnormal discharge does not occur, that is, the degree of vacuum is 2.
A first plasma nitride film 22 is deposited at a vacuum of 2 Torr or less, for example 1.5 Torr, on top of the first plasma nitride film 2-1, at a vacuum level of 2 Torr or more, for example 2
, a second plasma nitride film deposited at 5 Torr, 3 a field oxide film, 4 a gate oxide film, 5 a P+
The source/drain region 6 is an N substrate, and the second
The figure is 1. This is a sequence for generating second plasma nitride films 2-1 and 2-2. In addition, Fig. 3 shows Fig. 1. Second plasma nitride film 2-18 and 2-2
FIG. 2 is a simplified piping diagram of a plasma CVD apparatus for generating . In FIG. 3, 11 is a normally closed air valve, 12 is a normally open air valve, 13 is a flow meter, 14 is a rotary pump, 15 is a blower pump, and 16 is a normally closed air valve.
is a quartz tube, and 17 is a mass flow controller.
次に、動作について説明する。Next, the operation will be explained.
第１図の半導体装置の第１のプラズマ窒化膜２−１を生
成するためにプラズマＣＶＤ装置で、例えば炉温を３０
０℃、真空度を１．５ Ｔｏｒｒにして、第３図に示し
た簡易配管図にあるＳｉＨ，、ＮＨ３を流し、ＲＦによ
るグロー放電を行う。これは第２図のプラズマ窒化膜生
成簡易シーケンスでいうと各ステップを経た後のパデボ
生成”ステップにあたる。この１．５ Ｔｏｒｒによる
デポジションを１００〜３０００六行い、さらに同一パ
デポ生成”ステップにおいて、真空度のみを１．５ Ｔ
ｏｒｒから２．５Ｔｏｒｒにしてデポジションを行い、
第２のプラズマ窒化膜２−２を生成する。In order to generate the first plasma nitride film 2-1 of the semiconductor device shown in FIG.
At 0° C. and a vacuum degree of 1.5 Torr, SiH, NH3 as shown in the simple piping diagram shown in FIG. 3 are flowed, and glow discharge is performed by RF. In the simple plasma nitride film production sequence shown in Fig. 2, this corresponds to the ``paddebo generation'' step after passing through each step.This 1.5 Torr deposition is performed for 100~30006 times, and then in the same paddepot generation'' step, Only the degree of vacuum is 1.5 T
Perform deposition from orr to 2.5 Torr,
A second plasma nitride film 2-2 is generated.
ここで、仮に“デボ生成”ステ・ツブにおいて、全て真
空度１．５ Ｔｏｒｒで行っても゛局部的異常放電″は
避けられるが、膜厚が１μｍを越えるとアルミ配線のボ
イド（欠損）発生という新たな問題を生してしまう。１
、５ Ｔｏｒｒ ”デボ生成”は２ 、５ Ｔｏｒｒ
による“デボ生成″より同一膜厚であれば圧縮側のスト
レスが掛かるためである。Here, in the "devo generation" stage, even if the vacuum level is 1.5 Torr, "local abnormal discharge" can be avoided, but if the film thickness exceeds 1 μm, voids (defects) will occur in the aluminum wiring. This creates a new problem.1.
, 5 Torr “debo generation” is 2 , 5 Torr
This is because, if the film thickness is the same, stress on the compression side will be applied due to "devo generation".
第４図に局部的異常放電発生データを示す。この発明に
よれば、２０００枚ウェハ処理中発生ウェハは零である
。Figure 4 shows local abnormal discharge occurrence data. According to this invention, the number of wafers generated during processing of 2000 wafers is zero.
なお、上記実施例ではＰチャネル型アルミゲートＭｏ５
ｔ、ランレスタを例にとったが、Ｎチャネル型シリコン
ゲー１− Ｍ ＯＳ Ｉ−ラノジスク等のＡＺおよびＡ
ｌ ／ Ｓ ｉおよびＡＩ／Ｓｉ／Ｃｕ配線を使うデ
バイスであってもよい。Note that in the above embodiment, the P-channel type aluminum gate Mo5
t, Lan Restor is taken as an example, but AZ and A
Devices using l/Si and AI/Si/Cu interconnects may also be used.
以上説明したように、乙の発明は、プラズマ窒化膜のデ
ポジショノ生成ステップで、真空度２以上Ｔｏｒｒ未満
で第１のプラズマ窒化膜を１００〜３０００六にデポジ
ションし、その後、真空度２Ｔｏｒｒで第２のプラズマ
窒化膜をデポジションするので、アルミ面積の広い部分
、例えばＡＩターゲット領域等やその周辺部に゛局部的
異常放電′″は発生しな（なるとともに、プラズマ窒化
膜ストレスによるアルミ配線のボイド（欠損）の発生も
ないという効果がある。As explained above, in the plasma nitride film deposition step, the first plasma nitride film is deposited at a vacuum level of 100 to 30,006 Torr at a vacuum level of 2 Torr or more, and then the first plasma nitride film is deposited at a vacuum level of 2 Torr or more and Since the plasma nitride film described in step 2 is deposited, "local abnormal discharge" does not occur in areas with large aluminum areas, such as the AI target area and its surrounding areas (and at the same time, the aluminum wiring due to stress on the plasma nitride film is prevented). This has the effect that voids (deficiencies) do not occur.
第１図はこの発明の一実施例によるＰチャネル型アルミ
ゲ−１−Ｍ ＯＳ ＋−ラノジスタを示す断面図、第２
図はプラズマ窒化膜生成簡易シーケンスを示す図、第３
図はプラズマＣＶＤ装置の簡易配管図、第４図は局部的
異常放電発生データを示す図、第５図は従来のＰチャネ
ル型アルミゲ−１−Ｍ ＯＳ Ｉ、ランジスタを示す断
面図である。
図において、１はアルミ：配線、２−１．２−２は第１
．第２のプラズマ窒化膜、３はフィールド酸化膜、４は
ゲート酸化膜、５はＰ＋ソース、ドレイン領域、６はＮ
基板である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）第１図
第３図
′）Ｉ４
ＮＨ３シト４１１す２ Ｎ２
Ｉ６ Ｎ墨板
第
図
局部的異常放電発生データ
第
図FIG. 1 is a sectional view showing a P-channel type aluminum gate 1-M OS +-lanogistor according to an embodiment of the present invention, and FIG.
The figure shows a simple sequence for plasma nitride film production, Part 3.
The figure is a simplified piping diagram of a plasma CVD apparatus, FIG. 4 is a diagram showing local abnormal discharge occurrence data, and FIG. 5 is a sectional view showing a conventional P-channel type aluminum gate 1-MOS I transistor. In the figure, 1 is aluminum: wiring, 2-1.2-2 is the first
．． 2nd plasma nitride film, 3 is field oxide film, 4 is gate oxide film, 5 is P+ source and drain region, 6 is N
It is a board. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 3') I4 NH3 site 411s2 N2 I6 N Ink board Figure Local abnormal discharge occurrence data Figure
Claims (1)
ラズマ窒化膜を生成する方法において、前記プラズマ窒
化膜のデポジション生成ステップで、真空度２Ｔｏｒｒ
未満で第１のプラズマ窒化膜を１００〜３０００Åにデ
ポジションし、その後、真空度２Ｔｏｒｒ以上で第２の
プラズマ窒化膜をデポジションすることを特徴とする半
導体装置の製造方法。In a method for producing a plasma nitride film on aluminum wiring of a semiconductor device using a plasma CVD apparatus, in the plasma nitride film deposition step, the vacuum degree is 2 Torr.
1. A method for manufacturing a semiconductor device, comprising depositing a first plasma nitride film to a thickness of 100 to 3000 Å at a vacuum level of 2 Torr or more, and then depositing a second plasma nitride film at a vacuum level of 2 Torr or higher.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2189916A JP2504306B2 (en) | 1990-07-16 | 1990-07-16 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2189916A JP2504306B2 (en) | 1990-07-16 | 1990-07-16 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0474426A true JPH0474426A (en) | 1992-03-09 |
| JP2504306B2 JP2504306B2 (en) | 1996-06-05 |
Family
ID=16249357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2189916A Expired - Lifetime JP2504306B2 (en) | 1990-07-16 | 1990-07-16 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2504306B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0617200A (en) * | 1992-10-19 | 1994-01-25 | Sumitomo Special Metals Co Ltd | Tetragonal rare earth element-iron-boron type compound |
| US7579264B2 (en) | 2005-03-10 | 2009-08-25 | Oki Semiconductor Co., Ltd. | Method for manufacturing an electrode structure of a MOS semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63155626A (en) * | 1986-12-18 | 1988-06-28 | Oki Electric Ind Co Ltd | Surface-protective film for semiconductor device and formation thereof |
| JPS6447032A (en) * | 1987-08-18 | 1989-02-21 | Oki Electric Ind Co Ltd | Formation of surface protective film for semiconductor device |
| JPS6468967A (en) * | 1987-09-09 | 1989-03-15 | Fujitsu Ltd | Thin film transistor |
-
1990
- 1990-07-16 JP JP2189916A patent/JP2504306B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63155626A (en) * | 1986-12-18 | 1988-06-28 | Oki Electric Ind Co Ltd | Surface-protective film for semiconductor device and formation thereof |
| JPS6447032A (en) * | 1987-08-18 | 1989-02-21 | Oki Electric Ind Co Ltd | Formation of surface protective film for semiconductor device |
| JPS6468967A (en) * | 1987-09-09 | 1989-03-15 | Fujitsu Ltd | Thin film transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0617200A (en) * | 1992-10-19 | 1994-01-25 | Sumitomo Special Metals Co Ltd | Tetragonal rare earth element-iron-boron type compound |
| US7579264B2 (en) | 2005-03-10 | 2009-08-25 | Oki Semiconductor Co., Ltd. | Method for manufacturing an electrode structure of a MOS semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2504306B2 (en) | 1996-06-05 |
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