JPH0473687A - Graphic pattern processor - Google Patents

Abstract

PURPOSE:To efficiently obtain the rotation and the mirror image, etc., of a graphic pattern at a high speed by deciding a method for rearranging a graphic pattern outputted from a storing part by a row address in accordance with the instruction of an instructing means and rearranging it. CONSTITUTION:The row address of the storing means 2 is generated by a row address generating part 22 based on the instruction of the instructing means for instructing to perform the rotation and the mirror image of the graphic pattern from the storing means 2 in which each row of the graphic pattern, namely, a dot and matrix type graphic pattern is stored in the state that each row is rearranged in a different way and instructing to read out from the storing means 2. And by deciding the method for rearranging the graphic pattern read out from the storing means 2 by specifying the row address in accordance with the instruction of the instructing means and rearranging the graphic pattern by a rearranging means, the graphic pattern which has been processed for the rotation or the mirror image is outputted. Thus, the rotation and the mirror image, etc., of the graphic pattern are efficiently obtained at high speed.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to an information processing device, and in particular, for example,
The present invention relates to a graphic pattern processing device. E. Prior Art] For example, when writing a character pattern into a memory as image information or into a frame memory for display, a graphic pattern processing device reads the character pattern from a character pattern storage section and writes it into these memories. I have to. Conventionally, the character pattern storage unit 140 of a graphic pattern processing device has a configuration as shown in FIG. 14, and when a character code and a line (raster) are specified, the part of that line of the character pattern corresponding to the character code is output. Ru. Therefore, when writing a character pattern expanded into a memory using such a character pattern storage section 140, the process shown in the flowchart of FIG. 16 is performed. For example, consider the case where the character pattern 150 shown in FIG. 15 is an 8x8 dot character "R" and is read out and written into the memory. First, specify the character code and line (RA2
．． If RAI, RAO) = (0, 0, 0) is specified in the character pattern storage unit 140, the output Q of #7 in the storage unit 140
From output Q6 of #6, the dot at the left end of the first line of the letter "R" shown in FIG. The third dot from the left of the first line of the letter "R" is obtained from the output Q5 of #0, and the right dot of the first line of the letter "R" is obtained in the same way from the output QO of #0. , character ratio cover turn 141 is,
(07,06,05,04゜03.02,01,00
) = 0 such that (0,1,1,1,1,0,0,0)
Next, (RA2.RAI, RAO) = (0,0°1)
If you specify (07, 06, 05, 04, 03, 02
゜0! ,00) = (0,1,0,0,0,1,0
, 0) is output. The second line pattern of these letters "R" is written to the next portion of memory via the register. In this way, line specification (RA2.RAI, RAO)
By outputting = (o, o, o) to (1, 1, 1) and sequentially writing each output character pattern 141 to the memory, eight lines of patterns of the character "R" are read out.
written. Next, let us consider the case where, for example, a character pattern 170 as shown in FIG. 17, which is obtained by rotating the pattern of the letter "R" shown in FIG. 5, is written into the memory. Conventionally, there are two main methods: one is a software method, and the other is a method that uses dedicated hardware. First, the software method will be explained using the flowchart of FIG. 18(A). First, a character code and a line designation i (i=o to 7) are specified in the character pattern storage unit 140 (5202), and one line of the character pattern 150 shown in FIG. 15 is read out as an example, and stored in the register i (S2
03). By repeating this eight times, registers 0 to
7 stores all character patterns shown in FIG. 15 (S 2
02 to 5205), then shift register 0 to the left by 1 bit, put the leftmost bit of the pattern in register C (1-bit register) (S208), and
As shown in FIG. 18(B), register C and register 8 are shifted one bit to the right so that the value of is shifted into the most significant bit (MSB) (b, ) of register 8 (S209 ), similarly, next shift register l to the left by 1 bit, and then shift register 8 to the right by 1 bit.
When bit shifted, the leftmost bit of the pattern data stored in register 1 is shifted into the MSB of register 8. If this is repeated up to register 7, as a result, register 8 will record the leftmost bit (MSB) of each pattern stored in registers 0 to 7, and the contents of registers 0 to 7 will all be on the left. It is in a state where it is shifted by 1 bit to . When the contents of register 8 at this time are written to memory, 1 of pattern 170 in FIG.
This means that the row 1 has been written to the memory (S212). Furthermore, by performing the shift operation of registers O to 7 and register 8 eight times in steps 8208 to 5211, in step 5212, the memory is written as shown in FIG. The pattern data 170 shown is written. In this way, pattern data obtained by rotating the character pattern 150 in FIG. 15 by 90 degrees to the right is formed in the memory. On the other hand, if dedicated hardware is provided, its circuit configuration will be as shown in FIG. 19, and FIG. 21 shows a flowchart of rotation processing by the write/read control section. This hardware is a pattern rotator 190 that rotates the pattern 90' to the right. First, line designation i (i=o
-7) and read out the pattern S302-53
03) By activating the write control signal WR to write the contents to the register block #l of the pattern rotator, one line of pattern data is written to the register block #i (S304). , each register block 192 is as shown in FIG. 20, and has an 8-bit register 200. After activating the write control signal WR+ (i=o~7) and writing all the character patterns into the register blocks 191, the read control signal RD is activated to write the data recorded in these register blocks 191. At this time, RD is read. When activated, the contents (8 bits) of bit 7 (most significant bit) of register 200 of each register block are output from each register block and sent to data bus 193, resulting in the rotation shown in FIG. The pattern for the first line of characters is obtained. Similarly, if the read control signal RD is activated and data is read, the first
The second line of the rotated character pattern in Figure 7 is obtained. In this way, by sequentially activating the read control signals RD and -RDy and writing the read data into the memory, the rotation operation is completed (5307 to 5311), and finally the character pattern 170 shown in FIG. 17 is obtained. [Problems to be Solved by the Invention] However, the above conventional example has the following drawbacks. Obtaining a pattern of rotated/mirrored characters (rotated 90' to the right in the above example) requires either software processing or hardware processing; the former requires a bus mask (e.g. CP
U) becomes thick (and the processing speed becomes significantly slower than obtaining the original character pattern.In addition, in the latter case, the configuration of the hardware (pattern rotator 190) becomes complicated, especially when the character pattern size As the number of bits increases, the number of bits in the register, the selector circuit in the register block, and the circuit configuration of the write/read control section increase.
The processing speed is slightly slower than the original character processing speed. Also, in order to reduce the hardware scale of the pattern rotator,
If multiple pattern rotators with a bit number smaller than the character pattern size are used, there is no single character pattern (it must be divided into several parts, increasing processing time. It is impractical to register a character code with a different character code and store it in the character storage unit, as it would lead to a drastic increase in storage capacity. (For example, rotation/
An object of the present invention is to provide a graphic pattern processing device that can obtain a mirror image or the like. [Means for Solving the Problems] In order to achieve the above object, a graphic pattern processing device of the present invention has the following configuration. That is, it is a graphic pattern processing device having a graphic character pattern storage section, a storage means for storing a graphic pattern in a dot matrix format in a form in which each row is rearranged differently, and a graphic pattern processing device that rotates and/or mirrors the graphic pattern. , an instruction means for instructing to read from the storage means, a row address generation section for generating a row address of the storage means according to the instruction of the instruction means, and a graphic pattern output from the storage section according to the row address. A graphic pattern processing device characterized in that it has a rearranging means for determining a rearranging method and rearranging the shapes according to an instruction from the instruction means.

[Effect]

With the above configuration, the present invention rotates and/or mirrors a graphic pattern in a dot matrix format from a storage means in which each row of the graphic pattern is stored in a differently rearranged form. , a row address generating section generates a row address of the storage means based on an instruction from the instruction means to read from the storage means, and generates the graphic pattern to be read from the storage means according to the designation of the row address. A sorting method is determined in accordance with instructions from the instruction means, and the sorting means operates to rearrange the graphic patterns and output graphic patterns subjected to rotation and/or mirror image processing. [Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an example of an information processing device, in which l is CP
U, a bus mask that occupies the buses of the graphic controller, DMA controller, etc., 2, a character pattern storage unit that stores character patterns, and 3, a character pattern storage that mediates between the character pattern storage unit 2 and each bus. part interface (1/F) part, 4 is character pattern storage part 2
An image memory unit that stores image information such as character patterns and image data read from a computer, such as the frame memory of a bitmap display, information read by a scanner, or printer output information. 501 is a control bus, 502 is an address bus, and 503 is a data bus, such as an image buffer. In this embodiment, a case will be considered in which the bus master 1 reads out a rotated/mirror image character pattern. The line specification and character code are specified by the address output to the address bus 502, and the rotation and
Assuming that the mirror image is designated by register settings based on data output to the data bus 503, the character pattern storage I/F section 3 has the configuration shown in FIG. First, in order to set the rotation/mirror image specification in the rotation/mirror image specification register 33, the bus master 1 sends the address of the register to the address bus 502 and the data to be written to the data bus 50.
3 respectively. The decoder & control unit 32 decodes the address via the address buffer 31,
If it corresponds to the rotation/mirror image specification register 33, a latch signal is issued to the register 33 through the latch signal line 504 in accordance with the signal on the control bus 501 (for example, address strobe),
The contents of the data bus 503 at that time are latched and sent to the character pattern storage section 2. Next, the bus master 1 issues an address corresponding to the character code and line designation in order to read the character pattern from the character pattern storage section 2. The character pattern I/F section 3 outputs a portion of the address corresponding to the character code and a portion corresponding to the line designation to the character pattern storage section 2, respectively. In the decoder & control section 32,
When the read address corresponding to the character pattern storage section 2 is input from the bus master 1, an enable signal is sent to the data buffer 34 through the enable signal line 505, and the character pattern from the character pattern storage section 2 is sent to the data bus 503. . The bus master 1 receives the contents of the data bus 503 and writes the contents of the character pattern into the image memory section 4 as is or with modification. The character pattern written here is processed according to the rotation/mirror image specification. Next, the structure of the character pattern storage section 2 that generates such a rotated/mirror image pattern of a character pattern will be described in detail. An example of the configuration when the character pattern is 8x8 dots is shown in FIG. A row address generation unit 23 generates a row address 24 for 21, and a rearrangement unit 23 determines how to rearrange the outputs 25 of the storage unit 21 from the row designation and rotation/mirror image designation. The differences from the conventional example described above are the way character patterns are stored in the storage section 21 and the presence of the line address generation section 22 and rearrangement section 23. Conventionally, as shown in FIG. 15, character patterns are stored as they are; for example, the storage unit 140#7 in FIG.
In this example, only the information in the first column of each row of the character pattern is stored, #6 is stored in the second column, and so on, but in this embodiment, the storage unit 21 stores the information in the form in which the character pattern is rearranged for each row. I remember that. Various rearrangement methods can be applied, but as an example, let us consider a case where the data are rearranged and stored as shown in FIG. 4(A). Here, ~b0 represents the dots in each line of the character pattern. This sorting method is as follows. For each row, row designation signal RA2=1
The row with 4 bits on the left side and 4 bits on the right side are swapped, and R
The row with A2=0 does not perform the swap, and furthermore, the row with RA
In the row where 1 = 1, the 1st to 2nd bits, the 3rd to 4th bits, the 5th to 6th bits, and the 7th bit from the left
~ Swap two of each of the 8th bits and write RA
The row where 1=0 does not perform the swapping. Furthermore, R.A.O.
The row where =1 is the 1st bit and the 2nd bit, the 3rd bit and the 4th bit, the 5th bit and the 6th bit, and the 7th bit and the 8th bit when viewed from the left. The rows with RAO=0 are not replaced. Therefore, the first line of the original character pattern is R
Since A2 to RAO are all 0, no rearrangement is performed, and since RA2 to RAO are all 1 in the 8th row, the left and right sides are reversed as a result. For convenience of explanation, for each row sorting (however, one is not sorted at all),
swap SI S253 (SI S2
Each S3 is given a value of 0 or 1). swapoo: (b7.bG, b5.b4.b3
．． b2. bl, bO) → (b7.bG, b5.b4.b
3. b2. bl, bO) swapool: (b7.
bG, b5. b4. b3. b2. bl, bO)-(bG
, b7. b4. b5. b2. b3. bo, bl)
swapolo: (b7.bG, b5.b4
．． b3. b2. bl, bG) → (b5.b4.b7.b
G, bl, bO, b3. b2) swapoll: (
b7. bG, b5. b4. b3. b2. bl, bO)→
(b4.b5.be, b7.bo, bl, b2.b3)
swaploo: (b7.bG, b5.b4.b3
．． b2. bl, bO) → (b3.b2.bl, bO, h
7. bG, b5. b4) swaplol: (b7.
bG, b5. b4. b3. b2. bl, bO) → (b2
．． b3. bO, bl, bG, b7. b4. b5swap
Ho: (b7.bG, b5.b4.b3.b2
．． bl, bO → (bl, bo, b3.b2.b5.b4
．． b7. b6swapHl: (b7.bG, b
5. b4. b3. b2. bl, bD → (bo, bl, b
2. b3. b4. b5. bG, b7 With this rearrangement, the rearranged first row pattern is stored in the storage units 21 #7 to #0 at the row address 24 (A2.Al, AO) =
(0, 0, 0), and the second line pattern is (A2.
Store as AI, AO) = (0, 0, 1). Below, the fourth
As shown in Figure (A). FIG. 4(B) considers the pattern of the letter "R" as an example. In other words, by changing (A2.Al. AO) = (0, 0, 0) to (1, 1, 1), the output 25 of the storage section 21 is changed to Fig. 4 (B).
A pattern 400 shown on the right side is obtained, and the actual character pattern 150 is obtained by rearranging each line in the rearranging unit 23. FIG. 6 and FIG. 7(A) are diagrams showing configuration examples of the row address generation section 22 and rearrangement section 23, respectively, corresponding to the rearrangement method of FIG. 4. (RA2°RA 1, RAO)
is a row specification, and (0, 0, 0) to (1, 1, 1) specify the 1st to 8th rows. Rotation/mirror image specification signal (mode
2. ll1odel, modeO), Figure 5 (A
) can be specified. FIG. 5(B) is a diagram showing a specific example of how actual rotation/mirror image is performed based on a rotation/mirror image designation signal, taking the letter "R" as an example. The pit swapper 70 in FIG. 7 is input 2 from in7 to inO.
5 in the swapping method specified by swap S2 SI So and output to output cuff 1 of out7 to □utO, and the actual swapping method is swaps2 SI SO defined earlier. As can be seen from the logical expression shown in FIG. 7(B), this pit swapper 70 has a configuration including eight data selectors 8-1 (indicating that one data is selected from eight input data). 0° specification (no rotation) - Consider the case without mirror image. At this time (mode2.model, +nodeO) =
Since it is (0, 0, 0), line specification RA2, RAI, RA
For O, the output 24 of the row address generator 22 is as shown in FIG. 8(A). This applies to all (A2.
This can be seen from the fact that Al, AO) = (RA2.RA1. RAO). Therefore, for row designation, the output 25 of the storage unit 21 is as shown in the pattern 400 in FIG. = 0, so the pit swapper input (S2.Sl,
SO) = (RA2. RA 1 , RAO), so the sorting method for the row specification is shown in Figure 8 (B) 8
01, and the character pattern obtained from output cuff 1 of the sorting unit 23 is as shown by 401 in FIG. 8(B). In addition, in the case of O0 specification and mirror image, one of the rotation/mirror image specification signals, ll1modeO, is modeO = 1.
Therefore, only the sorting method in the sorting unit 23 is changed, as shown at 802 in FIG. 8(B), and as a result, a mirror image as shown at 402 in FIG. 8(B) is obtained. Next, consider the case of specifying 90" on the left. Without mirror image, (
mode2. model, mode) = (0,
1, 1), at this time, the output 24 of the row address generation unit 22 is different for each storage unit 21 #7 to #0, and as shown in FIG.
become that way. Therefore, the output 25 of the storage unit 21 for the row designations RA2 to RAO becomes as shown by 901 in FIG. 9(B). Since modeO=1, (32, Sl
, 5o) = (RA2.RAI, RAO), so the 9th
The character pattern rearranged by the rearrangement unit 23 is output as shown by 903 in FIG. 3(B). With mirror image, m
Since odeO only changes from 1 to 0, Figure 9 (B)
As shown in 904, only the rearrangement method is changed, and a character pattern 905 is obtained. The same goes for 180° rotation and 270' left rotation, as shown in Figure 10 (A
), Figure 10 (B), Figure 11 (A), Figure 11 (B)
An explanatory diagram is shown in each. As described above, even when reading a rotated/mirror image character pattern, the bus master l sets the rotation/mirror image specification register 33 in exactly the same way as when reading an original character pattern. The character pattern storage unit 2 is read out 8 times (
When the character pattern is 8x8 dots), the desired character pattern can be obtained. Of course, no special software processing is required. [Other Embodiments] When character patterns are stored in the storage unit 21, the rearrangement may be performed by storing patterns of different columns in each row for each of #7 to #O of each storage unit 21. For example, as shown in FIG. 12(A), the first line is left as is, the second line is rotated by 1 bit to the right, the third line is rotated by 2 bits to the right, and the following 8 lines are rotated in the same manner. eyes to the right7
According to the rearrangement pattern of FIG. 12(A), which may be stored by rotating the bits, the letter "R" is
) are sorted as shown. In this case, the row address generation section 22 and rearrangement section 23 need to be modified to accommodate this arrangement. In addition, although the rotation/mirror image specification register 33 was provided in the above-mentioned embodiment, if the address space of the bus master 1 allows, rotation/mirror image specification can be made as part of the address in the same way as character code and line specification. Can be assigned. At that time, the character pattern storage section IZF section 3 becomes as shown in FIG. In this case, there is no need to designate rotation or mirror image prior to the character pattern readout operation, which results in improved processing speed and eliminates the need for a 3-bit register. As described above, according to this embodiment, the processing speed when handling a rotated/mirror image pattern as image information can be made the same as when handling a conventional original pattern. Although this embodiment has been described with reference to the case of obtaining the rotation and mirror image of a character pattern, the present invention is not limited to this. can also be applied. [Effects of the Invention] As explained above, according to the present invention, there is an effect that it is possible to obtain, for example, a rotation or a mirror image of a graphic pattern, with a simple configuration and at high speed and efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the information processing apparatus of this embodiment, FIG. 2 is a block diagram of the character pattern storage I/F section, and FIG. 3 is a block diagram of the character pattern storage. FIG. 4(A) is an explanatory diagram of how to store character patterns; FIG. 4(B) is a diagram showing an example of rearranging the letter "R" according to the character rearranging pattern of FIG. 4(A); Figure (A) is an explanatory diagram of specifying rotation/mirror image, and Figure 5 (B)
) is a diagram showing a specific example of rotating and mirroring a character pattern using the letter "R" as an example, Figure 6 is a circuit diagram of the row address generation section, Figure 7 (A) is a block diagram of the rearrangement section, and Figure 7 Diagram (B)
are logical formulas corresponding to the rearrangement method. FIGS. 8 to 11 are explanatory diagrams of the operation of the character pattern storage unit. FIG. 12 (A) is an explanation of how to store character patterns in another embodiment. Figure 12 (B) is a diagram showing an example of rearranging the character "R" according to the character rearrangement pattern of Figure 12 (A), Figure 13 is a character pattern storage I/F section of another embodiment. 14 to 21 are explanatory diagrams of the conventional example. In the figure, 1... Bus mask, 2... Character pattern storage section, 3... Character pattern storage I/F section, 4... Image memory section, 21... Storage section, 22. . . . row address generation unit, 23 . . . rearrangement unit, 33 . . . rotation/mirror image specification register. Patent applicant Canon Co., Ltd. agent patent attorney
Yasunori Otsuka (and 1 other person) g; - To Shikireki Kunimi Riki-nami - \ wap wap SWa! swaIl: wap wap wap wap To the armpit # 7 patterns of chimney output length Fig. 12 (A) Fig. 14 Fig. 15 Fig. 7 Fig. 6 Fig. 18 (B)

Claims (1)

[Scope of Claims] A graphic pattern processing device having a graphic character pattern storage section, comprising: a storage means for storing graphic patterns in a dot matrix format in a form in which each row is rearranged differently; and a rotation of the graphic pattern and/or Do a mirror image,
an instruction means for instructing to read data from the storage means; a row address generation section for generating a row address of the storage means according to the instruction from the instruction means; and a graphic pattern output from the storage section based on the row address. A graphic pattern processing apparatus comprising a rearrangement means for determining a rearrangement method and rearranging the rearrangement according to an instruction from the instruction means.