JPH02201641A - Memory access controller for display - Google Patents

Abstract

PURPOSE:To enable an access even to memory for display in memory constitutions of both a plane constitution and a pixel constitution by providing a flag to instruct whether the constitution is the pixel type or plane type in an address for the access to the memory for the display. CONSTITUTION:A flag 101 to instruct whether the constitution is the pixel or plane is provided in an address 10 for the access to a memory 13 for display. When the fact that the flag instructs the pixel is detected, a decoder 11 decodes a dot address 104 of X, it is supplied to a selecting circuit 12, and the data of bits are read or written. In the case of the plane constitution, a plane selected input is supplied to the decoder 11, an output to select one plane corresponding to the input among plural planes is supplied to a controller 14, and only the specific plane is accessed from the controller 14. Thus, the access can be executed even to the memory for the display in the memory constitutions of both plane constitution and pixel constitution.

Description

[Detailed Description of the Invention] [Summary] Regarding a display memory access control device that accesses a memory plane that holds display data such as colors and gradations in either a pixel type or a plane type, a plane configuration and a pixel configuration are provided. The purpose of the present invention is to provide a display memory access control device that can access display memory with both types of memory configurations. , Y coordinate, and a decoder that decodes the dot address in the X coordinate when it detects that the address is pixel type, and a selection circuit that selects the corresponding 1 bit in the read or write data based on the output of the decoder. reads or writes 1-bit data, and when the address is a plane type, reads or writes data of a predetermined width of the corresponding plane using the plane selection input and the Y coordinate and the X coordinate excluding the dot address. Configure it to do so.

[Field of Industrial Application] The present invention relates to a display memory access control device that accesses a memory plane that holds display data such as color and gradation data in either a pixel type or a plane type.

In recent years, image processing technology has come into use in various fields, and is used in workstations equipped with bitmap displays, and it is expected that processing for color images will continue to develop in the future.

However, image data is stored in a display memory, and when performing image processing, the display memory is accessed, necessary data is retrieved, and the processed results are written into the display memory.

In this case, as data to be processed, there are cases where data of a certain length is processed all at once, and data of each pixel is processed, and each is used depending on the purpose. That is, handling data of a fixed length is suitable for processing the display screen as a surface, and is used when processing data corresponding to each color at once, and processing is performed by accessing each plane. On the other hand, when processing is performed pixel by pixel, it is necessary to access a specific pixel in the display memory for processing.

As described above, since the methods for accessing the display memory differ depending on the different processing formats, it is desired to be able to efficiently execute access control for both types.

[Conventional technology] FIG. 3 is an explanatory diagram of a conventional example.

FIG. 3A shows a memory in a plane configuration.

In the plane configuration, planes 1 to 4 are for each color (R, G
, B, etc.), and when each plane has one focus, four planes represent 16 colors (-24). In each plane, a color gradation code is stored at a position corresponding to each pixel. In this case, the memory space is as shown in the figure.
Memory addresses in each plane represent the same pixel position on the display screen if the relative address from the top position of each plane is the same. This kind of arrangement is one plane per plane.
It is called a "slice" type because it looks like the Hiso 1~ is sliced into each sheet. For example, the first pitch of plane 1 is 1-rl.
J is the first pitch 1-r of plane 2 and plane 3
Together with lJ, the color information of the first dot in the upper left corner of the screen is displayed using a total of 3 bits.

In such a plain configuration, in normal usage,
Process data for multiple dots by color.

The number of bits of that data corresponds to one word of memory, and when accessing memory, the number of bits of that data corresponds to two-dimensional coordinates (X, Y
) to a one-dimensional memory address =4.

Next, B in FIG. 3 shows a memory having a pixel configuration. In this case, the depth of each plane in the memory space appears to be concentrated as shown in the figure for the planes representing the gradation codes of each color. That is, bits 1-4 of pixels at the same relative position in planes 1-4 are sequentially stored in the same word (2) of the memory, and bits of adjacent pixels 5-8 are stored in word (2).

When accessing the memory with this pixel configuration, the address of the desired pixel is created from the two-dimensional address of the X and Y coordinates of the image. Therefore, conventionally, as shown in C0 in FIG. 3, when the width of the screen's X axis is m, m * Y
Obtain the address corresponding to the position of the pixel by calculating + Getting pixel data. Third
In the example of Figure B, the second bit of the second plane (marked as 6) is 4 bits per memory word, and the memory address is the bit of brain 2 of the word at address 2. 6 is obtained by addressing its second bit.

[Problems to be Solved by the Invention] As mentioned above, when processing conventional color gradation codes, it is difficult to obtain addresses when using a plain configuration as the display memory configuration and when using a pixel configuration. A processing unit (C
PU), calculations had to be made. Furthermore, in the case of pixel calculations, it was necessary to change the calculation formula depending on the word (or byte) length of the memory.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display memory access control device that can access display memories with both plane and pixel memory configurations.

[Means to solve the problem] FIG. 1 is a basic configuration diagram of the present invention.

In FIG. 1, 10 represents an address configuration, 11 a decoder, 12 a selection circuit, 13 a display memory, and 14 a controller.

The present invention includes a flag indicating whether it is a pixel or a plane in the address for accessing the display memory, and the X and Y coordinates, as well as an X dot address in the X coordinate to address the pixel, and corresponds to the address. , which performs access control corresponding to the pixel configuration and plane configuration.

[Operation] The address 10 includes a flag (indicated by P/F) 101) that instructs whether to access a memory space with a pixel configuration or a memory space with a plane configuration, an X coordinate 102,
A dot address 104 consisting of a plurality of bits is provided at the lower end of the X coordinate table.

When this address is input to the address bus 15, the flag 101 and the X dot address 104 therein are supplied to the decoder 11. When the decoder detects that the flag points to a pixel, it selects the dot address 10 of X.
4 is decoded and the result is supplied to the selection circuit I2.

In the case of a write operation to the display memory 3, input 1-bit data (only 1 bit out of n bits is significant, the others are irrelevant) is sent from the data bus 16 to the selection circuit 1.
2, and in the selection circuit 12, it is outputted to the selected focus position in the data bus 17 by the output of the decoder 1, and written to the corresponding position 1 of the display memory 3. Next, in the case of reading in the pixel configuration, a word at a specific address is accessed based on the Y coordinate and the X coordinate (address excluding the X dot address) and output to the data bus 17. In this case, game) 18 and 19 are prohibited, and n bits are input to the selection circuit. Since the 1/n decode output is inputted from the decoder 11 at this time, one bit on the data bus 17 is selected based on the output and output on the data bus 16. Other bit positions on the data bus 17 are then not output.

Next, in the case of a plane configuration, a plane selection input is supplied to the decoder 11, an output for selecting a plane corresponding to this input from among a plurality of planes is supplied to the controller 14, and the controller 14 only selects a specific plane. access.

Gates 18, 19 are also opened in response to a read or write operation of the plane configuration.

Address 10, which indicates the plane configuration, is address bus 1.
5, it is detected that the flag 101 indicates plane configuration, and the decoder 11 does not operate, and at the same time, the selection circuit 12 also does not operate. Then, the Y coordinate address and the X coordinate address (the X dot address is not used) are supplied to the display memory, and in the case of a read operation, word width (n bits) data is output from the corresponding plane. The signal is output from the data bus 17 to the data bus 16 through the gate 18 . For write operations,
The n-focus data input to the data bus 16 is sent to the data bus 17 through the gate 19 and is sent to the display memory 13.
is written to the corresponding word.

[Example] FIG. 2 is a configuration diagram of an embodiment of the present invention.

In Figure 2, 20 indicates the address configuration, the first bit is a flag bit (P/F) indicating whether it is a plane configuration or a pixel configuration, followed by 12 bits of the Y address excluding unused bits, and the X address is , consists of 7 bits of the X word address and 5 bits of the X dot address.

In the configuration of the access control device, a decoder (D
E COD E R), 22 is the selector (SE
(displayed with LECTER), 23 is the DRAM controller,
24 represents a memory constituted by DRAM, and 25 represents a multiplexer (indicated by MPX).

Memory: 8 x 256K x 4 dual port memory
2 configuration, and used as two banks 241 and 242. Frame memory is 4096 x 40
Since 96 dosotos are used as one plane, 12 bits are required for both the X and Y coordinates.

As shown in the figure, address assignment is performed using address bus 2.
6, the flag bit and the X dot address (5 bits) are input to the decoder 21, 9 bits of the Y address are input to one input end of the multiplexer 25, and the 7 bits of the X word address and the Y address are input to the other input side. Two of the remaining three bits of the address, a total of nine bits, are input and input from the multiplexer 25 to the address line of the memory.

The remaining 1 bit of Y address is bank select (8 x
2), the input is input to the DRAM controller 23, and the RAS (random
access strobe) signal.

When address 20 is input from address bus 26, when the flag bit indicates a pixel access (“1”),
Decoder 21 decodes the 5 bits of the X dot address and generates a 1/32 selection output. This X dot address indicates the number of the dot I in the data expressed by 32 bits (1 word). The output 28 (32 bits) of this decoder 21 is supplied as a mask input for the mask bit write of the dual port memory when writing data (1 bit) for IF sorting, and is input from the data bus 27. The 1-bit data is masked with the other 31 bits and written to the corresponding address in the memory 24.

When performing pixel access (reading),
The gate 29 is closed by a control signal 211 from the decoder, and the output of the 32-bit read data output from the memory 24 is prohibited. The read data from the memory 24 is input from the data bus 28 to the selector 22, and the corresponding 1 out of 32 bits is selected by the selected output of the decoder 21.
Select PITSU I and output it to the data bus 27. In that case, nothing is output to the other 31 bits.

In the case of plane access, it is detected that the flag bit is '0', the input of the X dot address (5 bits) is ignored, and the output of the plane selection register 33 is decoded. When the plane configuration has four planes, 2 bits are set in the plane selection register 33, and the decoder 21
selects one plane and determines whether it is his own plane to access), supplies it to the DRAM controller 23, and accesses the corresponding plane there.

During plain access, 1 word of 32-bit data read by a read operation is output from the data bus 27 via the gate 29, and in the case of a write operation, 32-bit data input from the data bus 27 is output from the gate 29. 30 to the memory 24 and written to the corresponding address.

[Effects of the Invention] According to the present invention, it is possible to directly access the display memory without performing calculations for converting coordinates into addresses, so that access to the display memory can be made faster.

[Brief explanation of the drawing]

FIG. 1 is a basic block diagram of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of a conventional example. In Figure 1, 10 near address configuration 11: Decoder 12: Selection circuit 13: Display memory 14: Controller Patent applicant Pfn Co., Ltd. Sub-agent Patent attorney Hosaka Airiko 5

Claims (1)

[Claims] In a display memory access control device that accesses a memory plane that holds display data such as colors and gradations in either a pixel type or a plane type, the display memory (13) is accessed. Address (10)
A flag indicating whether it is pixel type or plane type, and X, Y
a decoder (11) that decodes the dot address in the X coordinate when it detects that the address is of pixel type;
A selection circuit (1) selects a corresponding one bit in the read or write data based on the output of the decoder (11).
2) reads or writes 1-bit data, and if the address is a plane type, use the plane selection input (15).
1. A display memory access control device that reads or writes data of a predetermined width in a corresponding plane based on a Y coordinate and an X coordinate excluding a dot address.