JPH04282778A - Image processor - Google Patents

Abstract

PURPOSE:To sharply improve a processing speed. CONSTITUTION:Plural RAMs 102a to 102d corresponding to respective colors are simultaneously accessed, the data of the RAMs 102a to 102d can be read out/written only by one data and each of the RAMs 102a to 102d is provided with a pattern setting register (a register 200 is prepared for the RAM 102a). For instance, AND operation between data to be written in the RAM 102a and data from the register 200 is executed by an AND circuit 202, data already written in the RAM 102 are selected when data to be written in the RAM 102a is '0', or the result of the AND circuit 202 is selected when the data to be written in the RAM 102a is '1' and development to the RAM corresponding to a specified color is executed without executing arithmetic processing by a CPU.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus that is equipped with a memory for output information for each color and outputs a multicolor image.

0002

2. Description of the Related Art Conventionally, multicolor image processing devices, for example, develop character information including color codes sent from a host computer or the like into an internal memory as a bit image, and then read out and output this bit image. Color printers have memories corresponding to three or four colors, and can display multiple colors by combining the colors.

0003

[Problems to be Solved by the Invention] Therefore, in the conventional example described above, the CPU (central processing unit) in the device
Since the process is repeatedly executed for each color dot to be displayed or recorded, it has the disadvantage that the processing speed decreases. The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and an object of the present invention is to provide an image processing apparatus that can significantly improve processing speed.

0004

[Means for solving the problem] Solving the above problems,
In order to achieve the object, an image processing apparatus according to the present invention includes a storage means for storing data of a plurality of colors, a simultaneous access means for simultaneously writing and reading data access to the storage means for each color, and a simultaneous access means for simultaneously accessing data for each color. The present invention is characterized by comprising an updating means for updating data for each color for each color when the means simultaneously reads and writes simultaneously.

[0005]

[Operation] According to such a configuration, the storage means stores data of a plurality of colors, the simultaneous access means performs data write and read access to the storage means simultaneously for each color, and the update means simultaneously reads data with the simultaneous access means. When writing simultaneously, data for each color is updated for each color.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 2 is a block diagram showing a schematic configuration of an embodiment of an image processing apparatus according to the present invention. In FIG. 2, 100 is a CPU (central processing unit),
Controls the entire device. Reference numeral 103 denotes a ROM (read only memory) in which a control program for the CPU 100 is built-in. 102 is RAM (random access memory)
and stores output information for each color. A memory read/write circuit 101 executes read/write control of the RAM 102 . A data input unit 104 inputs data such as character information. A data output section 105 outputs data input from the data input section 104. This data output unit 105 corresponds to a color printer. FIG. 1 is a circuit diagram showing the configuration of the memory read/write circuit 101 of FIG. 2. As shown in FIG.

In FIG. 1, arrows indicate signals or information, and numbers written with diagonal lines in the middle of the arrows indicate how many bits the signal or information consists of. Reference numeral 1 denotes a timing generation circuit, which is activated by an activation signal 2 and a read/write (R/W) signal 3 from the CPU 100 in FIG. 2, and performs memory read/write timing control. 102a, 102b, 102c, and 102d are yellow (Y), magenta (M), cyan (C), respectively.
This is a RAM that stores output information for each color of black (K). For example, a bit image is expanded, and the lower two bits of each address are A0, A1, 00, 10, 01.
, 11. 8 are RAMs 102a, 102b, 102c, and 10 supplied from the timing generation circuit 1.
2d memory read/write signal, H (High
) level is used to read data, and data is written at L (Low) level. 4 is a selector, R
Output data 9a, 9b, 9c, and 9d of AM102a, 102b, 102c, and 102d are read and selected by the lower two bits A0 and A1 of the address. 5 is a bit processing unit, which includes RAMs 102a, 102b, 102c,
Output data 9a, 9b, 9c, 9d of 102d and CPU
100 data on the data bus 7, and as a result output data 10a, 10b.
, 10c, 10d are RAM 102a, 102b, 102
c, 102d. This bit processing unit 5
The data for each color is updated by . 6 is CPU
100 shows a control signal output to the selector 4 and RAM 102.

FIG. 3 is a circuit diagram showing the detailed internal structure of the bit processing unit 5 of FIG. 1. RAM12a in Figure 3
An example corresponding to the other RAM 12b, 12c, 12 is shown.
Since d also has a similar configuration, illustration and description thereof will be omitted. In FIG. 3, 200 is a register which is set by the CPU 100. 202 is an AND circuit, register 2
The output 205 of 00 and the data bus 7 of the CPU 100 are ANDed. 201 is an inverter circuit, and CPU100
The data on the data bus 7 is inverted. 203 is an AND circuit that connects the output 206 of the inverter circuit 201 and the RAM 12.
A logical AND is performed with the data 9a read from a. 204
is an OR circuit, and the output 207 of the AND circuit 202 and the AN
The logical OR with the output 208 of the D circuit 203 is taken.

Next, the operation of the bit processing unit 5 will be explained based on FIGS. 1, 3, and 4. FIG. 4 is a diagram showing an example of bit processing in this embodiment, and FIG. 5 is a flowchart explaining the operation of this embodiment. Note that Figure 5 shows the CPU
This is an explanation that includes the operation of 100 and the operation of each part. CPU
100 first sets a pattern such as a dither pattern in the register 200 through the data bus 7 ((a) in FIG. 4).
:Step S1). Next, the CPU 100 outputs the character pattern to be developed on the RAM 102 to the data bus 7 (
FIG. 4(b): Step S2). Also, at this time, CPU1
00 outputs the activation signal 2 to the timing generation circuit 1 (step S3). The timing generation circuit 1 sets the memory read/write signal 8 to H level for read designation, and
Simultaneous data read operations are started for AMs 102a, 102b, 102c, and 102d (step S4). After a certain memory access time has passed (step S5), R
The determined data is output to the output data 9a, 9b, 9c, and 9d of the AMs 102a, 102b, 102c, and 102d ((d) in FIG. 4: step S6). RAM10
The Y color processing of 2a will be explained as a representative example of the AND circuit 20.
3, the inverted data 206 ((e) in FIG. 4) of the data from the CPU 100 is ANDed with the output data 9a from the RAM 102a, and the result is output as (f) in FIG. . Further, the AND circuit 202 performs a logical product between the register 200 and the data 7 from the CPU 100, and outputs the result as shown in FIG. 4(c). O
In the R circuit 204, a logical sum is taken between the outputs of the AND circuits 202 and 203, and the result is (g) in FIG.
02a is output as input data 10a (step S7).

[0010] The timing generation circuit 1 has memory read/
The write signal 8 is set to a write signal, that is, L level, and R
Write data to AM102a, b, c, d at the same time,
An end signal 1 is sent to the CPU 100 at the same time as writing ends.
1 is output (step S8). Upon receiving this termination signal 100, the CPU 100 terminates access to the RAMs 102a to 102d (step S9).

In the above-described embodiment, a register is used as a means for setting a dither pattern, etc. However, a memory that can be read cyclically such as a FiFo (first-in/first-out) memory may also be used. By providing this, it is also possible to set a matrix pattern such as an 8×8 dot dither pattern.

The present invention may be applied to a system consisting of a plurality of devices, or to a device consisting of one device, or by supplying a program to the system or device. Needless to say, it can also be applied to cases where the goal is achieved.

[0013]

[Effects of the Invention] As explained above, according to the present invention,
It is equipped with a means for setting a pattern such as a dither pattern for each color, and embeds the set pattern only in the part of the memory that will form the pattern of the character pattern that will be developed from now on. Regarding the part, since a series of bit processing that leaves data that is already missing in memory is automatically performed, it has a significant effect on improving the speed of the CPU.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a memory read/write circuit 101 in FIG. 2. FIG.

FIG. 2 is a block diagram showing a schematic configuration of an embodiment of an image processing apparatus according to the present invention.

3 is a circuit diagram showing a detailed internal configuration of the bit processing unit 5 of FIG. 1. FIG.

FIG. 4 is a diagram showing an example of bit processing in this embodiment.

FIG. 5 is a flowchart explaining the operation of this embodiment.

[Explanation of symbols]

1 Timing generation circuit 2 Start signal 5 Bit processing unit 100 CPU 101 Memory read/write circuit 102a, 102b, 102c, 102d RAM1
03 ROM 104 Data input section 105 Data output section

Claims (1)

[Claims] 1. A storage means for storing data of a plurality of colors; a simultaneous access means for simultaneously writing and reading data to and from the storage means for each color; and when reading and writing at the same time with the simultaneous access means,
An image processing device comprising: an updating unit that updates data for each color for each color.