JPH0470657B2 - - Google Patents

Info

Publication number
JPH0470657B2
JPH0470657B2 JP57171072A JP17107282A JPH0470657B2 JP H0470657 B2 JPH0470657 B2 JP H0470657B2 JP 57171072 A JP57171072 A JP 57171072A JP 17107282 A JP17107282 A JP 17107282A JP H0470657 B2 JPH0470657 B2 JP H0470657B2
Authority
JP
Japan
Prior art keywords
signal
memory
address
controller
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57171072A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58137199A (ja
Inventor
Bii Jonson Robaato
Emu Nibii Junia Chesutaa
Aaru Sarasu Edowaado
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HANEIUERU INFUOOMEISHON SHISUTEMUSU Inc
Original Assignee
HANEIUERU INFUOOMEISHON SHISUTEMUSU Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HANEIUERU INFUOOMEISHON SHISUTEMUSU Inc filed Critical HANEIUERU INFUOOMEISHON SHISUTEMUSU Inc
Publication of JPS58137199A publication Critical patent/JPS58137199A/ja
Publication of JPH0470657B2 publication Critical patent/JPH0470657B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Hardware Redundancy (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP57171072A 1981-10-01 1982-10-01 自動再構成を有するメモリシステム Granted JPS58137199A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US30754281A 1981-10-01 1981-10-01
US307542 1981-10-01
US413631 1982-09-03

Publications (2)

Publication Number Publication Date
JPS58137199A JPS58137199A (ja) 1983-08-15
JPH0470657B2 true JPH0470657B2 (cs) 1992-11-11

Family

ID=23190200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57171072A Granted JPS58137199A (ja) 1981-10-01 1982-10-01 自動再構成を有するメモリシステム

Country Status (2)

Country Link
JP (1) JPS58137199A (cs)
AU (1) AU557694B2 (cs)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1330596C (en) * 1986-11-19 1994-07-05 Yoshiaki Nakanishi Memory cartridge and data processing apparatus
US7082127B1 (en) * 2000-07-28 2006-07-25 Marconi Intellectual Property (Ringfence), Inc. Synchronous dynamic register updating across a distributed system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1006973B (it) * 1974-01-18 1976-10-20 Honeywell Inf Systems Apparato di riconfigurazione di memoria
JPS5380929A (en) * 1976-12-27 1978-07-17 Nec Corp Memory unit
JPS54121623A (en) * 1978-03-15 1979-09-20 Hitachi Ltd Auxiliary bank switching system for main memory unit
JPS5528101A (en) * 1978-08-08 1980-02-28 Nec Corp Constitution control system of main memory
JPS5552600A (en) * 1978-10-13 1980-04-17 Nec Corp Main memory unit

Also Published As

Publication number Publication date
AU557694B2 (en) 1987-01-08
JPS58137199A (ja) 1983-08-15
AU8811182A (en) 1983-04-14

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