JPH0469756A - Address bus check device - Google Patents

Abstract

PURPOSE:To more surely check an address bus is normal or abnormal by inverting the data accessed to a register in any case of write and read-out, in the case a check inversion address is designated. CONSTITUTION:To a RAM 2 being a peripheral element, a memory block MBO of its uppermost stage is allocated as a register, and in accordance with the address designation, data is written and read out. In an OR gate 6 being a register designating means, in the case outputs of address lines A0 - A2 are all '000', an address designated by an address coder 4 is set as a check address, and in the case they are all '111', the address is set as a check inversion address, and in both cases, the memory block MBO of the uppermost stage is subjected to address designation. Subsequently, in the case the check inversion address is designated, an inverter 8 inverts the data accessed to the register in any case of write and read-out. In such a way, abnormality of an address bus is checked surely.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to an address bus check device that checks whether the address bus of a peripheral element accessed from a CPtJ is normal or abnormal.

<Prior Art> Conventionally, in order to check whether peripheral elements such as RAM and parallel interfaces placed around the CPU are being accessed correctly by the CPU, the CPU
Check data is once written to one peripheral element by specifying an address, and then the CPU reads data at the same address from the peripheral element. This is done by comparing both the written and read data and checking whether they match or do not match.

<Problem to be solved by the invention> However, with this conventional method of checking,
In some cases, it was not possible to sufficiently detect whether the address bus was normal or abnormal. For example, when the target is a RAM that is addressed by three address lines, an 8-byte address from OI (~7H) is assigned as shown in Figure 3 (not shown in Figure 2). Assuming that the address line of B is disconnected, T (when viewed from AM, this address line is always at a low level. Therefore, CI) U is 1.i-1' (“001 Even if you intend to write data to I(A, M) by specifying the address of ``000'', the address of orr(``000'') will actually be specified and the data will be written there.

Next, CP tJ is the same + 1. ,,((“001”)
Even if you intend to read data by specifying the address of
In reality, the data is read by specifying the address 011 (OOO"). Here, although the write and read addresses are different from the contents specified by the CPU, the written data and the read data are Since the contents match, the CPU cannot detect an abnormality in the address bus.

Similarly, if the center address line is broken, C
Even if the PU specifies the address of 2I (“oio”), it will actually specify the address of OII (“000”), but the contents of the data being written and read will not change, so the CPU cannot detect address bus abnormalities.

The present invention has been made in view of the above circumstances, and provides a method for checking the correct status of the address bus more reliably than in the past. It is something to do.

Therefore, the address bus check device of the present invention uses a register in which data is written or read according to address specification and one address specified by the address bus as a check address, and this check address and this check address. In either case, a register specifying means for addressing the register and, when the inverted check address is specified, write or read data accessed to the register. and data inversion means for inverting data in both cases of output.

In the configuration mentioned above, when the CPU specifies a check address and writes data D, the data D is written as is to the register, and then the data is written by specifying an inverted check address. When reading, data I is an inverted version of what was written by the data inverting means]
3. Conversely, when writing data D by specifying an inverted address for checking, the data D inverted by the data inverting means is written to the register, and then the data D is written by specifying the address for checking. When reading out data b, data b written in the register is read out as is.

Therefore, if the address bus is normal, the CPU specifies the check address (check inversion address) and writes data, and then specifies the check inversion address (check address) and writes the data. When read, the written data and the read data have an inverted relationship with each other.

On the other hand, if the address bus is abnormal, after specifying the check address (inverted check address) and writing data, the CPU then specifies the inverted check address (check address). Even if the data is read out using C
Since it does not match the check inversion address (check address) specified by PU, the read data does not match the inverted version of the written data. This makes it possible to detect that the address bus is abnormal.

<Embodiment> FIG. 1 is a circuit diagram that does not show the configuration of an address bus check device according to an embodiment of the present invention. In the figure, reference numeral I indicates the entire address bus check device, and 2 indicates C (not shown).
RA as a peripheral element accessed by PU, M
It is.

The address of this RAM 2 is designated by an 8-byte addressing signal from OH to 7H outputted from the address recorder 4 in accordance with the three address lines AO to A2 that constitute the address bus. . Also, R
AM2 has seven memory blocks from MBO to M+26, and each memory block MI30 to MI36.
8-bit data is stored in each in accordance with the address designation in -1-. In the figure, the memory block MBO at the lowest stage (-4th stage) is designated as a register Wj'l' in the claims.

Reference numeral 6 is an OR gate as a renostar specifying means in the claims. In this example, address line A
When the outputs of O to Δ2 are all 'ooo', the address OH designated by the address recorder 4 is used as the check address, and the outputs of the address lines AO to A2 are all '11.
1", addresses 7 I-I specified by the address recorder 4 are set as inverted addresses for checking, and in both addresses OH and 71-1, the topmost memory block MBO is An inverter 8 inverts the level of the write/read permission signal output from the CPU in response to data writing/reading.

r (CO to RC7 are inverted addresses for checking (in this example, address 7). When T (-'''11 bits) is specified, data accessed to the memory block MBO at the lowest stage is written and read. It is an inverting circuit as a data inverting means that inverts in any case of R, A, M
The data lines I) are provided corresponding to each of the data lines I to D7. Each inversion circuit RCO~IIRC7
have the same configuration and consist of first and second exclusive OR circuits 10, 2, 11th and 2nd gates 14 and 16, etc.

Note that the check address and the inverted check address are bit-inverted with respect to each other (“000” OH is “
111°”-71T).
The two match only when all of the address lines AO to A2 are disconnected, and although it is rare that such a situation occurs, the address lines AO to A2 are disconnected. This is because if all the wires are disconnected, the RAM2 cannot be accessed at all, so the abnormality can be easily detected.

Next, the operation of the address bus check device 1 having the configuration described in "2" will be explained.

(i) When address lines AO to A2 are all normal When checking the ATO I NOS bus, the CPU
Check address OH (-” 000
”) and sends data D. (for example, OO) (). In this case, the address 0 [(
Since only the output of (at l female 1.
I-1 to 7H are all low level), and the topmost memory block MBO of RAM 2 is addressed. Additionally, the CPU sends a high-level write permission signal Wl.
E[TB can be obtained, so each inverting circuit RCO~
As the first gate 14 of RC7 opens, the second gate 1
6 closes.

However, data I] is sent out from CP IJ via data lines DO to D7. (00tl) passes through the first exclusive OR circuit 1o and first gate 14 of each inverting circuit RCO-RC7 as it is and is allocated to the uppermost memory drive [1] MF30.

Next, the CPU reads the data inversion address 71 ((
-"ill") and sends out a low-level read permission signal READ. As a result, only the output of the address 7H of the address recorder 4 becomes high level, so in this case as well, the uppermost memory block MI30 of the RAM 2 is addressed, and at the same time, the first gate 14 of each inversion circuit RCO-RC7 is closed. With,
The second gate 16 opens. Therefore, data D stored in the top row of RA, M2. The level of (-〇〇I-■) is inverted by the second exclusive OR circuit 12. (=
FFI-I), and this inverted data I]. (=
After FF H) passes through the second gate 16, it is taken into the CPU via the data line Do-07.

In addition, in the case of "2" etc., on the contrary, CI)U first specifies the check inverted address 7[■(-"Ill") and writes the data (
For example, when writing F F H), the data is inverted by the inverting circuit ICO-R, C7 and 00 T ( is written, and then the check address 0H (OOO") is specified and the data is read. Since you can get OOI-1 without going out,
In this case as well, the read data is the level-inverted version of the write data.

In this way, each address line AO constituting the address bus
~A2, if everything is normal, the CPU first checks address 01 for check (or inverted address 7 for check).
H) and write data, then write the check inverted address 7H (or check address OH)
When data is read by specifying , the written data and the read data have an inverted relationship with each other, so at this time, CPtJ determines that the address bus is normal.

(11) When a part of address lines AO to A2 is abnormal For example, if the address line of A2, which is the least significant bit, is disconnected, when viewed from RA, M2, this address line A2 is always It is at a low level.

The CPU first checks the check address 0I ((000”)
Specify data D. When writing (for example, 001-1), the address 0H of the address recorder 4 becomes high level regardless of whether or not the address line A2 is disconnected. (-〇〇I]) is the inverting circuit RC
It passes through O to RC7 as it is and is written to the second-most memory block MBO of RAM2.

Next, the CPU selects the check inverted address 7H, (11
F), but in this case, the actual address line is 6
1-1. (-“+ +, 0”), so
Only the output of address 61-1 of address recorder 4 becomes high level. Therefore, the data stored in the lowest memory block MB6 of RAM2 is read out,
After this data passes through the inversion circuits RCO to RC7 as it is, it is taken into the CPU via the data lines DO to D7. Therefore, unless the data stored in the lowest memory block MB6 happens to be F F H, the write data and the read data will not have an inverted level relationship.

CPUIJ<Changing the contents of the data written to RAM 2" By repeating the above two operations multiple times, the probability of a coincidental coincidence becomes extremely small, and it is possible to eliminate incorrect judgments.

In this way, if a part of the address lines A and O-A 2 has an abnormality such as a disconnection, check the check address 0.
■After writing data by specifying 4 (or inverted check address 7H), the CPU next reads data by specifying inverted check address 7H (or check address 0) (). Since the actually specified read address does not match the check inversion address 7H (check address OH) specified by the CPU, the read data does not match the inverted version of the previously written data. This allows the CPU to determine that the address bus is abnormal.

Note that in this embodiment, the case where the RAM 2 is used as the peripheral element has been described, but the present invention is not limited to this.
In addition, the present invention can be widely applied to peripheral elements such as parallel interfaces that occupy multiple address spaces with respect to the CPU. Furthermore, in this example, 0H (-"000") is set as the check address, and 7H (-'"111") is set as the inverted check address, but this is not limiting. If there is such a relationship, one of them can be set as a check address, and the other can be set as an inverted check address.

<Effects of the Invention> According to the present invention, when the address bus is normal, when data is written by first specifying a check address, and then data is read by specifying an inverted check address. (Or, conversely, when you first specify an inverted check address and write data, then specify a check address and read the data), you will get data that has an inverted relationship with each other. If the address bus is abnormal, even if you write and read data as described above, you will not get data that is inverted to each other, so this allows you to reliably check whether the address bus is normal or abnormal. It becomes like this.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an address bus check device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing the configuration of an address bus check device according to an embodiment of the invention.
It is an explanatory diagram when accessing M. 1 Atres bus check device, 2. RAM (peripheral element), MBO/memory block (register), 6... OR gate (register designation means), r (CO~RC7 inversion circuit (data inversion means). Applicant: Company Representative Patent Attorney Oka II Kazuhide Data

Claims (1)

[Claims] (1) A device that checks the normality or abnormality of an address bus for peripheral elements accessed by a CPU, which includes a register to which data is written or read according to address specification, and one address specified by the address bus. A check address, and in both cases of this check address and an inverted check address obtained by inverting this check address, register specifying means for addressing the register, and when the inverted check address is specified, 1. An address bus check device comprising: a data inverting means for inverting data accessed to a register both in writing and reading.