KR970076886A - RAM error checking method - Google Patents

RAM error checking method Download PDF

Info

Publication number
KR970076886A
KR970076886A KR1019960018020A KR19960018020A KR970076886A KR 970076886 A KR970076886 A KR 970076886A KR 1019960018020 A KR1019960018020 A KR 1019960018020A KR 19960018020 A KR19960018020 A KR 19960018020A KR 970076886 A KR970076886 A KR 970076886A
Authority
KR
South Korea
Prior art keywords
address
ram
cell
error checking
checking method
Prior art date
Application number
KR1019960018020A
Other languages
Korean (ko)
Other versions
KR100186418B1 (en
Inventor
이기복
Original Assignee
구자홍
Lg 전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 구자홍, Lg 전자 주식회사 filed Critical 구자홍
Priority to KR1019960018020A priority Critical patent/KR100186418B1/en
Publication of KR970076886A publication Critical patent/KR970076886A/en
Application granted granted Critical
Publication of KR100186418B1 publication Critical patent/KR100186418B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

본 발명은 램의 에러 체크방법에 관한 것으로, 종래에는 어드레스를 일방적으로 지정하고 해당하는 셀에 데이타를 쓰고 읽어들여 각 셀의 비트동작 상태만 체크함에 따라 체크가 가능하였으나 어드레스 디코드에 관계없이 동작할 수 있기 때문에 오류를 범하게 되는 문제점이 있다. 따라서 본 발명은 초기에 셀의 각각 비트동작을 체크함과 아울러 어드레스 라인 디코드상태를 체크하여 시스템의 오동작을 미연에 방지할 수 있도록 한다.The present invention relates to a method of checking an error of a RAM. In the related art, an address is unilaterally designated and data can be written and read in a corresponding cell and checked only by checking a bit operation state of each cell. There is a problem that makes an error. Therefore, the present invention initially checks each bit operation of a cell and also checks an address line decode state to prevent malfunction of the system.

Description

램의 에러 체크방법RAM error checking method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명 램의 에러 체크방법에 대한 동작 흐름도.2 is a flowchart illustrating an error checking method of the RAM according to the present invention.

Claims (2)

시스템 초기화 이후에 지정된 어드레스에 해당하는 셀에 55 Hex와 AA Hex를 라이트 및 리드하여 셀의 각 비트동작이 정상적인지 아닌지를 체크하는 제1단계와; 상기 제1단계에서 비정상적이면 램 에러로 판단하고 정상적이면 어드레스를 클리어한 후 어드레스를 하나씩 증가시켜 마지막까지 셀을 체크하는 제2단계와; 상기 제2단계에서 마지막 어드레스까지 셀 체크를 완료하게 되면 다시 초기의 어드레스와 초기의 어드레스 +2n까지 증가시켜 '0’부터 ‘n’까지 라이트하는 제3단계와; 상기 제3단계에서 라이트완료시 램을 다시 초기화하고 각각의 어드레스에서 이전에 라이트 했던 값을 읽어들여 두 어드레스값을 비교하여 다르면 램 어드레스 디코드에러로 판단하고 같으면 램체크를 종로하는 제4단계로 이루어짐을 특징으로 하는 램의 에러 체크방법.A first step of writing and reading 55 Hex and AA Hex into a cell corresponding to a designated address after system initialization to check whether each bit operation of the cell is normal or not; A second step of determining that the RAM error is abnormal in the first step, and if the address is normal, clearing the address and incrementing the addresses one by one to check the cell until the end; A third step of increasing the initial address and the initial address +2 n and writing from '0' to 'n' once the cell check is completed to the last address in the second step; In the third step, when the write is completed, the RAM is reinitialized, and the previously written values are read from each address, and the two address values are compared. Error checking method of the RAM, characterized in that. 제1항에 있어서, n은 램 어드레스 최대비트수보다 하나 적은 수(램어드레스 최대 비트수-1)임을 특징으로 하는 램의 에러 체크방법.The method of claim 1, wherein n is one less than the maximum number of bits of the RAM address (the maximum number of bits of the RAM address-1). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960018020A 1996-05-27 1996-05-27 Error checking method for ram KR100186418B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960018020A KR100186418B1 (en) 1996-05-27 1996-05-27 Error checking method for ram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960018020A KR100186418B1 (en) 1996-05-27 1996-05-27 Error checking method for ram

Publications (2)

Publication Number Publication Date
KR970076886A true KR970076886A (en) 1997-12-12
KR100186418B1 KR100186418B1 (en) 1999-04-15

Family

ID=19459826

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960018020A KR100186418B1 (en) 1996-05-27 1996-05-27 Error checking method for ram

Country Status (1)

Country Link
KR (1) KR100186418B1 (en)

Also Published As

Publication number Publication date
KR100186418B1 (en) 1999-04-15

Similar Documents

Publication Publication Date Title
KR880010362A (en) Address line error test method
WO1994022085A1 (en) Fault tolerant memory system
KR920001344A (en) Control method of cache memory provided between CPU and main memory
US5825682A (en) Cache memory capable of using faulty tag memory
KR890004326A (en) Semiconductor memory device
KR900013621A (en) Semiconductor device
KR880000960A (en) Semiconductor memory
KR910014819A (en) Dual-Port Cache Tag Memory
KR970076886A (en) RAM error checking method
US4514847A (en) Key storage error processing system
JP3866345B2 (en) Semiconductor memory device and method for testing semiconductor memory device
US6535992B1 (en) DRAM auto-swapping device
JPS623520B2 (en)
KR910017284A (en) Parity check method and device for memory chip
JPS5769599A (en) Checking method of memory device
JP4773343B2 (en) Method and apparatus for recognizing errors for cache memory, and cache memory
JPS63239546A (en) Semiconductor memory circuit
KR920022313A (en) Memory address and data bus test method
JPS6123242A (en) Check system of parity check circuit
JPS61211786A (en) Ic card
JPS61214040A (en) Parity circuit of memory
KR100300040B1 (en) Memory test circuit in one chip micro computer
JPH02143352A (en) Memory error detection and correction system
JPS60549A (en) Memory testing system
KR930003166A (en) Memory test method

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20061129

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee