JPH046869A - Manufacture of complementary mos semiconductor device - Google Patents

Abstract

PURPOSE:To make performance of transistors in a wafers and between the wafers uniform and to perform miniaturization by eliminating an irregularity in thickness of a sidewall film, and obviating an irregularity in the diffusion length of first P- and N-type diffused layers. CONSTITUTION:A gate electrode 6 is formed on an N-type single crystal Si substrate 1 through a gate oxide film 5. Then, a thin oxide film 7 for light oxidation is formed in an oxidative atmosphere, and a first P-type diffused layer 8 and a first N-type diffused layer 9 are formed by selective ion implantation. Thereafter, it is light oxidized in the oxidative atmosphere, a polycrystalline silicon film 10 is formed thereon, polycrystalline silicon side-wall films 11 are formed at both sides of a gate electrode from above by anisotropically ion etching, and a second P-type diffused layer 12 and a second N-type diffused layer 13 are formed by selective ion implantation. The polycrystalline silicon film of the side-wall film is removed by an isotropic dry etching method or with nitric fluoric acid solution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing complementary MOS semiconductor devices, and provides an improved method of self-alignment process such as silicon gate and a new structure based thereon. The purpose is to respond to miniaturization.

[Conventional technology]

As the gate width of MOS transistors used in VLSI becomes smaller, the voltage applied to the drain becomes concentrated near the gate, and hot carriers are injected into the gate electrode, resulting in deterioration of device characteristics. It became so.

From 1.2μm to 1.3μm process to LDD (Lig
Transistors with a doped drain (hereinafter referred to as LDD) structure have become mainstream. Its main structure and manufacturing method will be explained.

FIG. 2(a) to FIG. 2(d) are schematic cross-sectional views of the process steps, and the prior art will be described below.

As shown in FIG. 2(a), NWej122 and PweN, l! are present in the N-type single crystal 81 substrate 21. After forming 23,
A LOCO5 oxide film 24 is formed by selective oxidation.

A gate oxide film 25 is formed in a region other than the region where the LOGO3 oxide film 24 is formed, a polycrystalline silicon layer is formed thereon, and then N° diffusion is performed to form an N'' polycrystalline silicon layer.

Selectively etching N1 polycrystalline silicon to form gate electrode 2
form 6. Thereafter, light oxidation is performed in an oxidizing atmosphere to form a thin oxide film 27.

As shown in FIG. 2(b), by selectively implanting boron ions, a first P-type diffusion layer 28 is formed as a source and drain diffusion layer of a P-channel transistor. The driving energy at that time was 20Ke.
v-40Kev, implant density is 5 x 10'2/
cd ~ 5 x 10''/d is slow. Then, by selectively implanting phosphorus ions, a first N-type diffusion layer 27 is formed as a source and drain diffusion layer of an N-channel transistor. The implanting energy at that time is 30 Kev to 60 Kev, and the implanting density is preferably 5 X 1012/cd to 5 X 1013/cJ.

After that, light oxidation is performed in an oxidizing atmosphere, and then CVD is applied on top of the light oxidation.
5102 film 30 is formed. Film thickness is 2000A~400A
It is between 0A.

As shown in FIG. 2(c), sidewall films 31 are formed on both sides of the gate electrode by etching away the CVD 5i02 film 30 and thin oxide 11!27 from above by anisotropic etching.

By selectively implanting boron ions, a second P-type diffusion layer 32 is formed as the source and drain diffusion layers of the P-channel transistor. The implantation energy at this time is preferably 20Kev to 60Kev, and the implantation concentration is preferably 1x10''/c~1x1016/C-.After that, by selectively implanting arsenic ions, the source of the N-channel transistor, A second N-type diffusion layer 33 is formed as a drain diffusion layer.The implantation energy at this time is 40Kev to 80Kev.
Ke v, implantation density I x 10''/cj ~ 1
X 1.016/c-That's so scary.

As shown in Figure 2(d), CVD5 i02 is placed on top of it.
MB2 is formed, and the contact portion of the diffusion layer is selectively etched to form a contact hole. AL on top of that
Wiring 35 is formed.

As described above, according to the conventional method, there are various methods for forming the CVDSiO2 film, which is the source of the sidewall films attached to both sides of the gate electrode, including a reduced pressure method, a plasma formation method, and an ordinary pressure method. With the method described above, it is also difficult to form a uniform film thickness over the entire surface of a 5'φ wafer or a 6'φ wafer, or to form a film with a desired thickness. There is a variation of about ±20% of the target film thickness, and a variation of about 15% over the entire surface of the wafer, and within the wafer there is a variation of 900 people for the film thickness of 3000 people.
There is a total variation of 1,200 people between wafers.

Due to such large variations in film thickness, there are large variations in the thickness of the sidewall film formed. If the widths are different, the lengths of the first P-type and N-type diffusion layers with a thin concentration will vary, and this will act as a resistance in the transistors in the series, resulting in variations in the performance of the transistors.

As miniaturization progresses and the gate electrode length becomes even shorter, the size of the resistance (the length of the first P-type and N-type diffusion layers) included in this series will of course deteriorate the performance, but the variation will increase. This causes problems and is unsuitable for miniaturization.

[Problem to be solved by the invention]

The present invention eliminates variations in the thickness of the sidewall film, eliminates variations in the diffusion length of the first P-type and N-type diffusion layers, uniformizes the performance of transistors within a wafer and between wafers, and further miniaturizes the transistors. It was designed so that it could be used against people.

[Means to solve the problem]

The means of the present invention uses a polycrystalline silicon film that has little variation in film thickness between wafers, within wafers, and between batches when formed, and has excellent processing uniformity, and uses a polycrystalline silicon film that is formed on both sides of the electrode. As the wall film, the first P
By controlling the lengths of the type and N-type diffusion layers, it is possible to equalize the performance of transistors within a wafer, between wafers, and between hatches, and also to respond to miniaturization.

〔Example〕

FIG. 1(a) to FIG. 1(d) are schematic cross-sectional views showing the order of steps, and the method of the present invention will be described below.

As shown in FIG. 1(a), N
After forming the well 12 and Pwell 13, a LOGO6 oxide film 4 is formed using a selective oxidation method.

After forming a gate oxide film 5 in a region other than the region where the LOCOS oxide film 4 is formed and forming a polycrystalline silicon layer thereon, N" diffusion is performed to form an N" polycrystalline silicon layer 3.
Make 2 layers. selectively etching the N° polycrystalline silicon layer;
A gate electrode 6 is formed.

Thereafter, light oxidation is performed in an oxidizing atmosphere to form a thin oxide film 7.

As shown in FIG. 1(b), by selectively implanting boron ions, a first P-type diffusion layer 8 is formed as a source and drain diffusion layer of a P-channel transistor. The driving energy at that time was 20Kev.
~40Kev, implant density is 5 x 1012/c-
~5 x 1013/c- is desirable. Thereafter, by selectively implanting phosphorous ions, first N-type diffusion layers 9 are formed as source and drain diffusion layers of the N-channel transistor. At that time, the implanting energy is preferably 30 Kev to 60 Kev, and the implanting concentration is preferably 5 x 1012/cl# to 5 x 1013/c-.

Thereafter, light oxidation is performed in an oxidizing atmosphere, and a polycrystalline silicon film 10 is formed thereon. Film thickness is 1゜00A ~ 400A
It is between 0A.

As shown in FIG. 1(c), the polycrystalline silicon film 10 is etched away from above by anisotropic etching to form polycrystalline silicon sidewall films 11 on both sides of the gate electrode.

Thereafter, by selectively implanting boron ions, a second P-type diffusion layer 12 is formed as a source and drain diffusion layer of a P-channel transistor.

The driving energy at that time is 20Kev ~ 6QKev
So, the implantation density is 1×10′5/cd ~I×1
016/cd or something.

Thereafter, by selectively implanting arsenic ions, a second N-type diffusion layer 13 is formed as the source and drain diffusion layers of the N-channel transistor. The implantation energy at that time was 40Kev to 80Kev, and the implantation density was 1 x 1015/cd to I x 1015.
/c- is noisy.

As shown in Figure 1(d), isotropic dry etching method or
The polycrystalline silicon film serving as the sidewall film is removed by etching with a nitric-fluoric acid solution. After light oxidation in an oxidizing atmosphere, a PSG film 14 is formed, and after annealing,
A contact hole is formed by partially etching away the PSG film 14 and thin oxide film 7 in the contact portion. An AL wiring 15 is formed thereon.

〔Effect of the invention〕

According to the method of the present invention, the variation in polycrystalline silicon film thickness is within ±5% between wafers, within ±3% within a wafer, and within ±7% between lots.

Furthermore, the thicknesses of the flat portion and the side surfaces on both sides of the gate electrode are almost the same. On the other hand, the CVDSiO2 film tends to be thinner on the side surfaces, and the shape is deformed (the shape is different between the upper and lower sides).

Since the polycrystalline silicon film has a uniform thickness as described above, the thickness of the sidewall formed on the side surface of the gate electrode becomes uniform, and the length of the first P-type and N-type diffusion layers becomes uniform. becomes uniform, the series resistance of the transistor becomes uniform, and therefore the performance of the transistor becomes uniform.

It is also suitable for responding to miniaturization.

Furthermore, compared to the CVD SiO2 film, polycrystalline silicon has better dry etching processability, and the end point can be detected using a thin oxide film as the base, so more uniformity can be achieved.

In addition, the CV D Si O2 film may remain on the thick film or thin diffusion layer as a sidewall and contain dirt.
However, in the method of the present invention, the sidewall film of the polycrystalline silicon film is removed later, so there is no such drawback.

[Brief explanation of drawings]

FIGS. 1(a) to 1(d) are schematic cross-sectional views of the process steps according to the method of the present invention. FIGS. 2(a) to 2(d) are schematic cross-sectional views of the steps of a conventional method. Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Kizobe Suzuki (and 1 other person) $l f
thef 1.1m (α) thickness 2mm) 4/ Broom 2kaku (d)

Claims (1)

[Claims] (1) In a method for manufacturing a complementary MOS semiconductor device having a plurality of P-channel MOS transistors and a plurality of N-channel MOS transistors each in a semiconductor substrate, (a) forming a gate electrode by forming a gate insulating film on the semiconductor substrate; (b) forming a thin insulating film on the gate electrode and the source and drain; (c) performing a first P-type diffusion on the source and drain of the P-channel MOS transistor; (d) (e) Performing oxidation in an oxidizing atmosphere; (f) Forming a polycrystalline silicon film on the semiconductor; (g) performing first N-type diffusion in the source and drain of the N-channel MOS transistor; ) etching the polycrystalline silicon film by anisotropic etching so as to leave at least a portion on the side of the gate electrode; (h) etching a second P-type film on the source and drain of the P-channel MOS transistor; (i) performing a second N-type diffusion into the source and drain of the N-channel MOS transistor; (j) isotropically etching the polycrystalline silicon film remaining on the side of the gate electrode; or a step of removing by etching with a liquid.