JPH0468569A - Mis semiconductor device - Google Patents

Abstract

PURPOSE:To suppress a decrease in resistance to pressure due to impact ionization by causing the channel region of this MIS type transistor element conduct with a polycrystal semiconductor film in contact with one of adhered semiconductor substrates through an opening formed on a separation insulating film in a semiconductor on insulator(SOI). CONSTITUTION:A SiO2 film 33 of a first silicon substrate 31 is selectively etched to form an opening 34. Then, a p-type impurity region 35 and a p+ polycrystal silicon film 36 are formed. Next, a second semiconductor substrate, for example, a silicon substrate 37, is adhered. Next, a first silicon substrate 31 is ground and polished, and a SOI substrate 38 is formed. Thereafter, a gate electrode 41 is formed using polycrystal silicon. An n-type source region 42 and a drain region 43 are formed. The source region 42 and the drain region 43 are formed so that a channel region 44 is made to conduct with the p<+> polycrystal silicon film 36 and the silicon substrate 37 through an opening 34 of the SiO2 film 33.

Description

[Detailed Description of the Invention] This industrial field of application: The present invention relates to so-called SOI (semiconductor on
The present invention relates to an MTisTi trench device in which a semiconductor element having an MIS structure is formed using a substrate.

[Summary of the invention]

In an MIS semiconductor device, the present invention provides MI
By forming an S-type transistor element and configuring the channel region of this element to be electrically connected to the polycrystalline semiconductor film in contact with one of the bonded semiconductor substrates through the opening of the isolation insulating film in the SOI substrate, the SOI substrate The present invention aims to improve the reliability of this type of MIS semiconductor device by suppressing the deterioration in resistance due to impact and ionization, which is a drawback of M r S type semiconductor devices formed in It has been made possible.

= Conventional technology Recently, MIS field effect transistors (hereinafter referred to as IJi SFET) using SOI substrates have high alpha ray resistance, are latch-up free, and can achieve high speeds due to reduced parasitic capacitance. With these advantages, research and development are actively progressing.
FETs are usually made by forming an island-shaped silicon thin film (2) on an insulating layer (1) such as 5i02 as shown in Figure 3.
A 102 substrate (3) is used, and this NRICON thin film (2) is provided with a source region and a drain region of the first conductivity type, in the illustrated example, high concentration regions (4a), (5a) and low concentration regions (
4b), (5b)
An n-type source region (4) and drain region (5) with a tightly doped drain structure are formed, and a silicon thin film (
2) A gate electrode (7) made of, for example, polycrystalline silicon is formed on top via a gate insulating film (6) made of, for example, Sin. (8) is a source electrode, and (9) is a drain electrode.

However, I used the S○■ board (3)! ,+IS
F[, T(10) has a drawback that the source-drain breakdown voltage in the OFF state, that is, the source-drain breakdown voltage is low.

This is the old S FET (10) as shown in Figure 3.
At gate voltage V, ≦threshold voltage Vth, the electric field at the drain end under the gate electrode (7) becomes considerably high, so that the channel current (11) across the source region (4) increases.
The electrons injected into the drain region (5)
These electrons (e) cause impact ionization in the high electric field region (12) at the end of the drain, generating electron-hole pairs, of which the holes flow into the channel region (11). caused by flowing inside. In other words, in a normal bulk type j (I 5FET, the hole h (so-called hole current I) flowing in the channelel escapes as a substrate current through the substrate, but in this SOI substrate), Since the sample (3) is surrounded by the SiO□ film (1) and the holes are allowed to escape:';5), the holes are transferred to the channel region (11) near the source region ). This accumulated holes lower the energy barrier between the source and the channel.
As a result, the source region acts as an electron emitter, and in addition to the normal electron flow (channel current L) flowing through the channel region (11), the bipolar-operated electron current I
. occurs. This electron current I. again causes a positive feed puncture phenomenon in which a hole current I is generated in the high electric field region (12), causing a rapid increase in the drain current and, as a result, lowering the source-drain breakdown voltage.

That is, ■ in Figure 4. -■ As shown in the 0 curve diagram, at a high gate voltage V q H, the source-drain withstand voltage becomes as shown in curve (I) and there is no problem, but when the gate voltage is low at V 92, the source-drain breakdown voltage becomes as shown in curve (II). The drain-to-drain breakdown voltage decreases.

A structure shown in FIG. 5 has been proposed as a method for suppressing the reduction in source-drain breakdown voltage caused by such impact ionization. This MIS FE
For example, T(14) is formed by forming an element formation region (17) made of a silicon thin film separated by an 8102 film (16) on a p-type semiconductor substrate (15), and in which an η-type source region (4) is formed. ), a drain region (5), a gate insulating film (6), and a gate electrode (7)! An Al5FET element is formed, and the channel region (11) is connected to the contact region (19) of the well region (18) through the opening (16^) of the bottom 5in2 film (16). (20>, (21) are M electrodes (1988 Autumn Proceedings of Japan Society of Applied Physics, No. 657)
See page 5a-B-8 "C1.103) Run Disc Using TOLE"). This IJIS FET (14)
In this case, the hole current I generated by impact ionization flows into the well region (18) of the substrate (15), thereby improving the source-drain breakdown voltage. The SOI structure of this MISFET is formed by combining NRICON's selective epitaxy growth technology and selective polishing technology. In this case, the well region is formed by performing ion implantation three times, the first implantation forming the contact region (19) of the well region (18), and the second implantation forming the contact region (18a) of the well region (18). In the third implantation, the transistor characteristics (the impurity concentration of the channel region (11)) are controlled.

:Problem to be solved by the invention By the way, in the above-mentioned IJIS FET (14),
The manufacturing process is unavoidably complicated, as it requires formation of the well region (18), selective epitaxial, selective polishing, and three ion implantations.

In view of the above-mentioned points, this development has developed an MIS type semiconductor device that can suppress the drop in breakdown voltage caused by impact and ionization, improve the reliability of the semiconductor device itself, and can be manufactured easily and with high precision. This is what we provide.

[Means for Solving the Problems 2] The present invention provides a source region (4) on a bonded SOI substrate (38) bonded via a polycrystalline semiconductor film (36).
2) MIs having a drain region (43) and a gate part
A channel region (44) of this MIS type transistor element is formed on an S○■ substrate (38).
The polycrystalline semiconductor film (36) in contact with one of the bonded semiconductor substrates (37) is configured to be electrically connected through an opening (34) formed in the isolation insulating film (33).

[Effect]

According to the configuration of the present invention, a bonding type SOI substrate (
The channel region (44) of the MIS transistor element is opened through the opening (34) of the isolation insulating film (33) in
) is electrically connected to the polycrystalline semiconductor film (36) in contact with one of the bonded semiconductor substrates (37), so the channel region (4) is electrically connected by impact ionization.
4) Carriers generated within (for example, n-th mannel-(1
In the case of a 15FET, holes) can be released as substrate current through the polycrystalline semiconductor film (36), and a decrease in source-drain breakdown voltage can be suppressed. Moreover, since the S○■ group 1 (38) of the bonding method is used, the S
An opening (34) is formed in the isolation insulating film (33) during the OI substrate creation process.
) Just add the process to form the desired one! JIS
FETs can be manufactured easily and with high precision.

:Example〕 Hereinafter, the present invention will be described in detail with reference to the drawings.

Figure 1 shows n channel! , '1lSFET, and will be explained along with its manufacturing method.

In this example, first, as shown in FIG.
A semiconductor substrate (31), that is, a silicon substrate (31), is selectively etched on its main surface so that a convex portion (32) is formed in the area that will later become an element formation region, and then isolation and insulation are formed on the entire main surface. A film, for example, a 5in2 film (33) is formed.

Next, as shown on the first day, the Si opening and the film (33) are selectively etched to form an opening (34) in a portion corresponding to the convex portion (32). This aperture (34) is connected to the n-channel 1. It is provided in a portion corresponding to the channel region of the IIs FET element.

Next, as shown in FIG. 1C, a slightly higher p-type impurity region (actual impurity concentration I
Q18cm-3 order) (35) is formed, and then,
Polycrystalline silicon film (36) including the inside of the opening (34)
Form the adhesion. This p shadow region (35) is provided to prevent the depletion layer induced in the gate and drain from reaching the silicon (32)-polycrystalline silicon (36) interface. Note that this p shadow region (35) can also be formed by impurity diffusion from the p polycrystalline silicon film 36).

Next, as shown in the first diagram, a p゛゛crystalline silicon film (
36) and bonded with a second semiconductor substrate, such as a silicon substrate (37), and then, as shown in FIG. By grinding and polishing until the 5102 film is completely exposed, the element formation area (32A
) An SOI substrate (38) is formed.

After that, a normal device process is carried out (however, impurities in the p-polycrystalline silicon film (36) are removed from the channel region (44).
) It is necessary to use a low-temperature process to prevent the liquid from entering. ) to the element formation area (32A).
An IS type transistor element is formed. That is, a gate electrode (41) made of, for example, polycrystalline silicon is formed on the surface of the element formation region (32A) via a gate insulating film (40) made of 8102 or the like, and an n-type source region (42) is formed.
and a drain region (43). In this example, the source region (42) and drain region (43) are, for example, high concentration regions (42a), (43a) and low concentration regions (42).
b), (43b). Then, this source region (42) and drain region (43)
) is formed such that the channel region (44) is electrically connected to the p-polycrystalline silicon film (36) and the silicon substrate (37) through the opening (34) of the 8102 film (33). (
45) and (46) are a source electrode and a drain electrode. In this way, the desired n-channel MIS FE
Configure T(47).

Note that a power supply voltage V dd and a ground voltage are applied to the drain electrode (46) and the source electrode (45), and a ground potential is applied to the silicon substrate (37).

Such a configuration! , t's FET (47), the hole current I, generated by impact ionization, flows through the isolated Si (], the opening (34) of the membrane (33).
) can be released as a substrate current from the p-polycrystalline silicon film (36) and the silicon substrate (37), and a decrease in source-drain breakdown voltage can be suppressed.

In addition, during manufacturing, we use a bonding method SOI substrate (3
In step 8), after forming the isolation 5i02 film (33), an opening (34) is formed and the p-polycrystalline silicon film (33) is formed.
Since the second silicon substrate (37) is bonded to the second silicon substrate (36) via the second silicon substrate (36), the process is simple, and therefore the desired MIS FET (47) can be manufactured easily and accurately.

The upper side is an n channel! , IIs FET, but p-channel M! It can also be applied to 5FET. However, in a p-channel old S FET using an SOI substrate, the hole impact ionization rate is low, so the problem of the source-drain breakdown voltage drop described above is less likely.

Figure 2: Well, a complementary type constructed with this point in mind! JIS
This is an example of FET. In this example, an n-channel \++s FE is formed in the first element formation region (32A) by using an SOr group vi (3g) by a bonding method.
T (4T) has the same configuration as shown in FIG. , Nnel! , IIs FET (48) are formed in a second element formation region (32B) surrounded on all sides and bottom by a 5iC12 film (33) as before. Note that (51) and (52) are p-type source and drain regions, (53) is a gate insulating film made of Sl, 02, etc., (54) is a gate electrode made of, for example, polycrystalline silicon, (55) and (56) ) are the source and drain electrodes.

In addition, although the silicon substrate (37) is connected to the ground potential on the upper side, as shown by the broken line, the p-crystalline silicon (36)
Using this p polycrystalline silicon peritoneum 36 as a wiring,
) with f! ! ! It may also be connected to a potential.

According to this configuration, it is a highly reliable complementary type that is easy to manufacture and suppresses the drop in pressure resistance due to impact ionization! According to the present invention, MIS formed using an SOI substrate
The reduction in breakdown voltage due to impact ionization can be suppressed without sacrificing the advantages of the MIS type semiconductor device, and the reliability of the MIS type semiconductor device itself can be improved. Further, since it can be manufactured using a bonding type SOT substrate, this type of MIS type semiconductor device can be manufactured easily and accurately.

[Brief explanation of the drawing]

1A to 1F are cross-sectional views showing an example of a MIS type semiconductor device according to the present invention in the order of manufacturing steps, FIG. 2 is a configuration diagram showing an example of a complementary MIS type semiconductor device according to the present invention, and FIG. S
FIG. 4 is a block diagram of a general MIS type semiconductor device using an OI substrate, and shows drain current I and -drain voltage V with gate voltage as a parameter. Characteristic curve diagram, Figure 5 is the conventional MI
FIG. 2 is a configuration diagram showing an example of an S-type semiconductor device. (32A) is an element formation region, (33) is an insulating film,
(34) is an opening, (36) is a polycrystalline silicon film, (42)
) i;! Source region, (43) is drain region, (4
4) is the Chi-Ding-I-L region. Substitute Hitomatsu Hide Mori Jz convex gi l Kotomi cavity 0 engineering tumor reduction r surface y Figure 1 J2A cloak shape test 411 area

Claims (1)

[Claims] A MIS type transistor element is formed on a bonded type SOI substrate bonded via a polycrystalline semiconductor film, and a channel region of the MIS type transistor element is formed in the isolation insulating film of the SOI substrate. A MIS type semiconductor device which is electrically connected to the polycrystalline semiconductor film which is in contact with one of the semiconductor substrates bonded through an opening.