JPH0467633A - Wiring formation in semiconductor device - Google Patents

Abstract

PURPOSE:To make up the stepped parts between a wiring and an insulating film for improving the reliability upon the wiring by a method wherein a conductive layer is formed on the insulating film on a semiconductor substrate to perform the patterning step for wiring formation using the conductive layer as a mask and then ions are implanted into the patterned region so as to insulate the non-wiring regions. CONSTITUTION:BPSG as an interlayer insulating film is laminated on a semiconductor substrate 6 having a source 1, a drain 8 and a gate 5; the patterning step laminated with a photoresist 7 is performed; a contact hole communicating the source 1 and the drain 8 with each other is made; Al as a metallic layer 4A is formed by sputtering step; furthermore, the photoresist 7 is laminated to perform the wiring pattern step. Next, oxygen is ion-implanted into the parts only not masked with the photoresist 7 so that the parts may be oxidized thereby enabling the parts of the layer 4A to be insulated into non-wiring regions 3. Next, the photoresist 7 is patterned to make another contact hole communicating with the gate 5. Through these procedures, a surface flattened semiconductor device can be manufactured.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for forming wiring in a semiconductor device,
In particular, the present invention relates to a method for forming wiring that improves planarization of a semiconductor device.

[Conventional technology]

Conventionally, the method for forming wiring in a semiconductor device has been to form a wiring layer over the entire surface of an insulating film of a semiconductor substrate, and then selectively etching non-wiring areas using lithography technology. For this reason, there was a problem in that the difference between the wiring and the insulating film was large.

Particularly, in the case of a semiconductor device having a multilayer wiring structure, the difference increases synergistically because further wiring layers are repeatedly formed on the base where the difference has occurred. For this reason,
There have been problems in that the reliability of the wiring is reduced, such as cracks tending to occur in the wiring at the difference portions, resulting in widening of the disconnection, and the inability to form a wiring layer uniformly.

Therefore, in order to planarize a semiconductor device, a conventional example is known in which wiring is formed on an insulating film and then steps are eliminated by a known SOG method or the like.

[Problem to be solved by the invention]

However, in the conventional example, after the wiring is formed on the insulating film, the process of providing a special film for planarization is increased, which reduces productivity and increases costs, especially in the case of multilayer wiring. The problem was that the impact was large.

In order to solve these problems, the present invention provides a wiring formation method that can achieve planarization of a semiconductor device without removing non-wiring areas by etching or the like or providing a special film for planarization. The purpose is to provide

[Means to solve the problem]

To achieve this object, the present invention includes a step of forming a conductive layer on an insulating film of a semiconductor substrate, a step of patterning the conductive layer using a mask to form wiring, and a step of insulating the conductive layer in the patterning region. Introducing ions that cause
The present invention provides a method for forming wiring in a semiconductor device, the method comprising the step of insulating a non-wiring region.

[Effect]

According to the method for forming wiring in a semiconductor device according to the present invention, the steps include: forming a conductive layer on an insulating film of a semiconductor substrate; patterning the conductive layer using a mask to form wiring; By including the step of introducing ions that insulate the conductive layer, a wiring region (conductive layer) and a non-wiring region (insulated layer) can be continuously formed on the same wiring layer. As a result,
The difference between the wiring and the insulating film can be significantly reduced, and planarization can be achieved without providing a special film for planarization.

〔Example〕

Next, one embodiment of the present invention will be described based on the drawings.

1 to 6 are cross-sectional views showing the manufacturing process of the wiring according to this embodiment. In this embodiment, a method for manufacturing a MOSFET will be explained as an example.

In the process shown in FIG. 1, the source 1, drain 8 and gate 5 are
As an interlayer insulating film 2 on a semiconductor substrate 6 having a BPS
Stack G.

Next, in the step shown in FIG. 2, a photoresist is layered and patterned using lithography technology on the glabellar insulating film 2 obtained in the step shown in FIG. 1, and the source 1,
A contact hole communicating with the drain 8 is made.

Thereafter, in the step shown in FIG. 3, a metal layer (conductive layer) 4A is applied to the entire surface of the glabella insulating film 2 obtained in the step shown in FIG. 2 and the contact hole.
Then, Al2 is formed by sputtering the entire surface. next,
A photoresist is laminated on the metal layer 4A and patterned to form wiring.

Next, in the step shown in FIG. 4, oxygen ions were implanted into the photoresist 7 obtained in the step shown in FIG. 3 as ions for insulating the metal layer 4A. At this time, oxygen is removed from the photoresist 7.
It is implanted only in the areas that were not masked (non-wiring areas).

Next, as shown in FIG. 5, the part into which oxygen was ion-implanted in the step of FIG. The portion becomes 3 non-wiring areas.

Next, in the process shown in FIG. 6, the twisted photoresist is patterned using lithography technology, and a contact hole communicating with the gate 5 is formed.

Through the above steps, a semiconductor device with excellent planarization was obtained.

Note that by further repeating the steps shown in and after FIG. 1 on the semiconductor device shown in FIG. 6, a semiconductor device having multilayer wiring can be obtained.

Next, an actual MOSFET was formed according to this example, and the level difference in the obtained MOSFET was measured.

The results are shown in Table 1.

Table 1 For conventional products, the size of the difference is equal to the wiring layer thickness (A
(100% of the thickness of the wiring layer occurs), but
In this embodiment, for example, oxygen ions are implanted into the /l wiring layer, and when changing from Af to A 1 z O3, the volume changes to Al.
Since the thickness is 1.27 to 1.42 times that of 2, there is a difference of 27% to 42% of the thickness of the Al wiring layer between the wiring layer and the non-wiring layer, which is different from that of conventional products. It is possible to significantly reduce the difference in comparison.

In this embodiment, B is used as the glabellar insulating film 2 in the process shown in FIG.
PSG was used, but in addition, LTO, PSG, P-3i
Various insulating films such as n, etc. can be used.

Furthermore, although Af was used as the metal layer 4A, A1-3t
Any metal can be used as long as it has conductivity and becomes an insulating nonmetallic compound when an insulating ion is introduced, such as Cu or the like. In this embodiment, the wiring layer is formed by sputtering, but the wiring layer is not limited to this, and may be formed by CVD or the like.

Further, as a method for introducing insulating ions into areas other than the mask region in the step shown in FIG. 4, in addition to ion implantation, a diffusion method or the like may be used. In the process shown in Figure 4, oxygen was introduced as an ion to insulate the metal layer to insulate it, but if nitrogen or other ions are introduced into a metal, the metal becomes an insulating non-metal compound. Can be used. Also,
Two or more types of ions having the above characteristics may be introduced.

In the case of Affi, the amount of ions introduced to insulate the conductive layer is preferably 90 to 95% by weight based on the layer to be introduced.

〔Effect of the invention〕

As described above, the method for manufacturing wiring in a semiconductor device according to the present invention includes the steps of forming a conductive layer on an insulating film of a semiconductor substrate, patterning the conductive layer using a mask to form wiring, By including the step of introducing ions for insulating the conductive layer into the patterning region and insulating the non-wiring region, it is possible to insulate a part of the conductive layer as it is. Therefore, a wiring area and a non-wiring area can be continuously formed on the same conductive layer, and the wiring area can be formed without removing the non-wiring area by etching or providing a special film for planarization. It is possible to significantly reduce the difference that occurs between the film and the insulating film. As a result, cranks caused by the difference can be prevented, and the wiring layer can be formed uniformly, so that the reliability of the wiring can be improved.

[Brief explanation of drawings]

1 to 6 are cross-sectional views showing the manufacturing process of wiring of a semiconductor device according to the present invention. In the figure, 1 is a source, 2 is an insulating film between the eyebrows, 3 is a non-wiring, 4 is a wiring, 4A is a metal layer, 5 is a gate, 6 is a substrate, 7 is a photoresist, and 8 is a drain. Two forty! ○2 2 Figure 15 Figure M 6 Figure 3

Claims (1)

[Claims] (1) A step of forming a conductive layer on an insulating film of a semiconductor substrate, a step of patterning the conductive layer using a mask to form a wiring, and introducing ions to insulate the conductive layer into the patterning region to form a non-conductive layer. 1. A method for forming wiring in a semiconductor device, comprising the step of insulating a wiring region.