JPH0467375B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase control circuit configured to digitally control the phase by outputting a signal having a predetermined phase relationship with respect to a reference signal.

BACKGROUND ART Phase control circuits that digitally control the phase have conventionally been incorporated into various electrical devices. In this case, a phase control method as shown in FIG. 1 is typically used. That is, in synchronization with the signal generated by the reference signal generation circuit 1, a differential pulse twice as large as the reference signal is generated in the differentiation circuit 2, and the sawtooth wave generation circuit 3 uses a capacitor or an operational amplifier using this differential pulse. A sawtooth wave is generated by charging and discharging the integrator. The comparator 4 compares the error signal of the detection circuit 6 with the sawtooth wave and outputs a signal whose pulse width is controlled according to the output of the detection circuit 6. This signal whose pulse width is controlled is converted into a phase shift signal φB synchronized with the same frequency as the reference signal in a conversion circuit 5 constituted by a flip-flop, and is output. The detection circuit 6 is a detection circuit that detects the phase difference between φA' and φB' as a voltage. That is, normally, the phase difference between the feedback signals φA' and φB' from the phase-controlled circuit whose phase is controlled by the output signals φA and φB from the phase control circuit and the feedback signals φA' and φB' is detected as a voltage.

Therefore, in the case of such a circuit configuration, in order for the main circuit to perform analog operation, it is necessary to take measures such as adjusting the temperature drift of the circuit components and the level of the sawtooth wave. This technique had the disadvantage of being complicated to operate because it required analog adjustment.

In addition, in order to improve control accuracy, the detection circuit 6
Increasing the gain of the control loop causes a phase shift in the control loop, and the control amount becomes too large, making the entire control system unstable and causing hunting, which exposes disadvantages such as unstable phase control operation. I'll come. Therefore, there was a problem in that highly accurate phase control was difficult.

An object of the present invention is to eliminate these drawbacks and obtain a phase control circuit that can be controlled with high precision.

The present invention includes a first frequency divider that divides the frequency of a signal from the reference signal generation, a gate circuit that receives the signal from the reference signal generator and controls the number of pulses, and a frequency divider that divides the output of the gate circuit. comprising a second frequency divider, a gate control circuit that controls the gate circuit, and an oscillation circuit that controls the operating time of the gate circuit,
The invention is characterized in that the gate circuit is controlled by a phase shift signal detected by the gate control circuit.

Next, preferred embodiments of the digital phase control circuit according to the present invention will be described in detail with reference to the accompanying drawings.

Therefore, in FIG. 2, reference numeral 10 indicates a reference signal generator, and reference numerals 11 and 12
respectively indicate frequency dividers. A gate circuit 13 is interposed between the reference signal generator 10 and the frequency divider 12, and controls the number of trigger pulses of the frequency divider 12.
The frequency divider 12 generates an output signal φB, and the frequency divider 11 generates an output signal φA. The output sides of AND gates 16 and 17 are connected to the gate circuit 13. The output side of the detection circuit 20 connected to the controlled circuit 19 which generates the feedback signals φB' and φA' substantially indicating the operating state is connected to the comparator 1, respectively.
Connect to one of input terminals 4 and 15. The other input terminal of the comparator 14 has a + reference voltage +
Vref is input, and the negative reference voltage -Vref is input to the other input terminal of the comparator 15. These comparators 14 and 15 are the detection circuit 2
Converts an output voltage of 0 to a lead or lag signal. The output side of the oscillator 18 is connected to an AND gate 1, respectively.
It is connected to the other input terminal of 6 and 17.

In such a circuit configuration, the reference signal generator 10 uses a crystal oscillator or the like to generate a frequency sufficiently higher than the output frequency, divides the frequency in the frequency divider 11, and outputs the frequency as the output signal φA. on the other hand,
The output signal φB is divided and outputted by the gate circuit 13 and the frequency divider 12 when the phases of the feedback signals φA' and φB' are balanced, but when the phases of the feedback signals φA' and φB' are unbalanced, the output signal φB is divided and output by the gate circuit 13 and the frequency divider 12. 13, the number of input pulses of the frequency divider 12 is increased or decreased, and the output signal φA
The phase difference between and φB is controlled. That is, the third
As shown in the figure, the gate circuit 13 constitutes a synchronous differential circuit including a flip-flop 21 and two cascade-connected D-type flip-flop groups 22 and 23. Therefore, when the output is balanced, the frequency of the input pulse is divided by 1/2 by the flip-flop and supplied to the frequency divider 12. Therefore, when the phase of the output φB advances, the comparator 14 becomes "H" level. On the other hand, since the signal from the oscillator 18 is introduced into the AND gate 16, the AND gate 16 goes high in synchronization with the signal from the oscillator 18. As a result, in the gate circuit 13, the flip-flop 21 is stopped by one pulse of the output signal of the reference signal generator 10 by the operation of the synchronous differentiation circuit. Therefore, the output signal φB is delayed by one pulse (see FIG. 4a). Similarly, when the phase of φB is delayed, the comparator 15 and the gate circuit 17 go to "H" level, the gate circuit 13 stops the flip-flop 21 by one pulse, and the simultaneous reference signal generator 1
One pulse of the output signal of 0 is directly input to the frequency divider 12. As a result, the input pulse of the frequency divider 12 increases by one pulse, so that the phase of the output φB advances by one pulse of the reference signal generator 10 (see FIG. 4b). In this way, the phase shift operation is performed for each operating frequency of the oscillator 18 until the phases of the feedback signals φA' and φB' are balanced.

According to the present invention, since the reference signal is divided into the required frequency as described above, the phase control accuracy depends on the reference oscillation frequency, and when the output frequency is the same, increasing the reference frequency increases the frequency division stage. This increases the resolution per pulse, making it possible to improve control accuracy. In this case, the amount of phase shift per pulse is determined by the oscillation frequency of the reference signal generator 10, and the detection circuit itself is independent of the amount of phase shift, so the gain of the detection circuit can be made sufficiently high. In addition, by making the operating frequency of the oscillator lower than the controlled output frequencies φA and φB, the phase shift operation is made into an intermittent operation, and the rate of change in the amount of phase shift during the phase control operation time is made gradual, thereby optimizing the control amount. can be achieved. Therefore, this operation causes a phase shift in the control loop,
It is possible to prevent unstable operation of the control loop due to an over control amount due to an excessive response.

Note that due to the low operating frequency of the oscillator 18, the response time of the control loop is reduced, and a considerable amount of time may be required until the output reaches an equilibrium state, such as during startup. However, in this case, the response time can also be improved by selecting a high operating frequency of the oscillator 18.

As described above, according to the present invention, it is possible to digitally process the analog operation part that the conventional technology had, and this eliminates the need to consider variations in characteristics of circuit components, temperature drift, etc. Analog adjustments such as gain can also be made unnecessary.

Moreover, according to the present invention, the detection accuracy, control amount, and response can be set individually, so that highly accurate phase control can be achieved.

Furthermore, there is an advantage that a highly accurate synchronous operation device can be obtained by using an external signal from a commercial power supply or the like as a reference signal for the detection circuit.

Although the present invention has been described above with reference to preferred embodiments, the present invention is not limited to these embodiments, and various modifications and improvements can be made without departing from the gist of the present invention. Of course.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional embodiment, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a diagram showing a specific example of the gate circuit in Fig. 2, and Fig. 4 is an explanation of its operation. It is a diagram. DESCRIPTION OF SYMBOLS 1... Reference signal, 2... Differentiation circuit, 3... Sawtooth wave generation circuit, 4... Comparator, 5... Conversion circuit, 6... Detection circuit, 10... Reference signal generator, 11, 12... Frequency divider, 13... Gate circuit, 14, 15... Comparator, 16, 17...
...AND circuit, 18 ... oscillator, 20 ... detection circuit, 21 ... flip-flop, 22, 23 ...
D type flip-flop group.

Claims (1)

[Scope of Claims] 1. A first frequency divider that divides the frequency of the signal from the reference signal generator, a gate circuit that receives the signal from the reference signal generator and controls the number of pulses, and an output of the gate circuit. a second frequency divider that divides the frequency of the gate circuit, a gate control circuit that controls the gate circuit, and an oscillation circuit that controls the operating time of the gate circuit, A digital phase control circuit characterized by controlling a gate circuit. 2. In the circuit described in claim 1,
The gate control circuit includes a detection circuit that detects a phase difference between two signals, two comparators that compare the output of the detection circuit with a reference voltage, and an AND circuit connected to each of the two comparators. A digital phase control circuit featuring: