JPH0467375B2 - - Google Patents

Info

Publication number
JPH0467375B2
JPH0467375B2 JP59070348A JP7034884A JPH0467375B2 JP H0467375 B2 JPH0467375 B2 JP H0467375B2 JP 59070348 A JP59070348 A JP 59070348A JP 7034884 A JP7034884 A JP 7034884A JP H0467375 B2 JPH0467375 B2 JP H0467375B2
Authority
JP
Japan
Prior art keywords
circuit
gate
frequency
output
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59070348A
Other languages
Japanese (ja)
Other versions
JPS60214116A (en
Inventor
Masuo Okazawa
Tsurashi Yamamoto
Toshio Myayama
Isao Masuzawa
Tsuneo Awano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nagano Nihon Musen KK
Tokyo Keiki Inc
Original Assignee
Tokyo Keiki Co Ltd
Nagano Nihon Musen KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Keiki Co Ltd, Nagano Nihon Musen KK filed Critical Tokyo Keiki Co Ltd
Priority to JP59070348A priority Critical patent/JPS60214116A/en
Publication of JPS60214116A publication Critical patent/JPS60214116A/en
Publication of JPH0467375B2 publication Critical patent/JPH0467375B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H03L7/0993Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider and a circuit for adding and deleting pulses

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【発明の詳細な説明】 本発明は基準信号に関して所定の位相関係をも
つた信号を出力させてデジタル的に位相制御する
ように構成した位相制御回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase control circuit configured to digitally control the phase by outputting a signal having a predetermined phase relationship with respect to a reference signal.

従来からデジタル的に位相を制御する位相制御
回路が各種電気機器に組み込まれている。この場
合、典型的には第1図に示すような位相制御方式
が使用されている。すなわち、基準信号発生回路
1で発生する信号に同期して微分回路2において
前記基準信号の2倍の微分パルスを発生させ、ノ
コギリ波発生回路3はこの微分パルスによりコン
デンサ、または演算増幅器を用いた積分器の充放
電を行つてノコギリ波を発生する。コンパレータ
4は検出回路6の誤差信号と前記ノコギリ波とを
比較して検出回路6の出力に応じてパルス幅の制
御された信号を出力する。このパルス幅が制御さ
れた信号をフリツプフロツプで構成する変換回路
5において基準信号と同じ周波数に同期させた位
相シフト信号φBに変換して出力する。検出回路
6はφA′とφB′との位相差を電圧として検出する
検出回路である。すなわち、通常、位相制御回路
からの出力信号φAおよびφBによつて位相制御さ
れる被位相制御回路からの帰還信号φA′および
φB′との位相差を電圧として検出している。
BACKGROUND ART Phase control circuits that digitally control the phase have conventionally been incorporated into various electrical devices. In this case, a phase control method as shown in FIG. 1 is typically used. That is, in synchronization with the signal generated by the reference signal generation circuit 1, a differential pulse twice as large as the reference signal is generated in the differentiation circuit 2, and the sawtooth wave generation circuit 3 uses a capacitor or an operational amplifier using this differential pulse. A sawtooth wave is generated by charging and discharging the integrator. The comparator 4 compares the error signal of the detection circuit 6 with the sawtooth wave and outputs a signal whose pulse width is controlled according to the output of the detection circuit 6. This signal whose pulse width is controlled is converted into a phase shift signal φB synchronized with the same frequency as the reference signal in a conversion circuit 5 constituted by a flip-flop, and is output. The detection circuit 6 is a detection circuit that detects the phase difference between φA' and φB' as a voltage. That is, normally, the phase difference between the feedback signals φA' and φB' from the phase-controlled circuit whose phase is controlled by the output signals φA and φB from the phase control circuit and the feedback signals φA' and φB' is detected as a voltage.

そこで、このような回路構成の場合、主たる回
路がアナログ的な動作を行うために回路構成部品
の温度ドリフトの影響やノコギリ波のレベル調整
等を行なわなければならず、結極、この種の従来
技術ではアナログ的調節が必要であるために操作
が煩雑となる不都合があつた。
Therefore, in the case of such a circuit configuration, in order for the main circuit to perform analog operation, it is necessary to take measures such as adjusting the temperature drift of the circuit components and the level of the sawtooth wave. This technique had the disadvantage of being complicated to operate because it required analog adjustment.

また、制御精度を向上させるために検出回路6
のゲインを上げると、制御ループの位相ずれが惹
起したり、制御量が過大となるために制御系全体
が不安定となつてハンチングを生じ、位相制御動
作が不安定となる等の欠点が露呈してくる。従つ
て、高精度の位相制御が困難となる難点があつ
た。
In addition, in order to improve control accuracy, the detection circuit 6
Increasing the gain of the control loop causes a phase shift in the control loop, and the control amount becomes too large, making the entire control system unstable and causing hunting, which exposes disadvantages such as unstable phase control operation. I'll come. Therefore, there was a problem in that highly accurate phase control was difficult.

本発明はこれらの欠点を解消し高精度で制御可
能な位相制御回路を得ることを目的とする。
An object of the present invention is to eliminate these drawbacks and obtain a phase control circuit that can be controlled with high precision.

本発明は、基準信号発生からの信号を分周する
第1の分周器と、前記基準信号発生器からの信号
を受けパルス数を制御するゲート回路と、前記ゲ
ート回路の出力を分周する第2の分周器と、前記
ゲート回路を制御するゲート制御回路と、前記ゲ
ート回路の動作時間を制御する発振回路を備え、
前記ゲート制御回路で検出された位相ずれ信号に
より前記ゲート回路を制御するようにしたことを
特徴とする。
The present invention includes a first frequency divider that divides the frequency of a signal from the reference signal generation, a gate circuit that receives the signal from the reference signal generator and controls the number of pulses, and a frequency divider that divides the output of the gate circuit. comprising a second frequency divider, a gate control circuit that controls the gate circuit, and an oscillation circuit that controls the operating time of the gate circuit,
The invention is characterized in that the gate circuit is controlled by a phase shift signal detected by the gate control circuit.

次に、本発明に係るデジタル式位相制御回路に
ついて好適な実施例を挙げ、添付の図面を参照し
て以下詳細に説明する。
Next, preferred embodiments of the digital phase control circuit according to the present invention will be described in detail with reference to the accompanying drawings.

そこで、第2図において参照符号10は基準信
号発生器を示し、また、参照符号11並びに12
は、夫々、分周器を示す。基準信号発生器10と
分周器12との間にはこの分周器12のトリガー
パルス数を制御するゲート回路13が介装され、
前記の分周器12は出力φBを、また、前記分周
器11はφAの出力信号を発する。前記ゲート回
路13にはアンドゲート16並びに17の出力側
が接続する。実質的に作動状態を示す帰還信号
φB′、φA′を発する被制御回路19と接続された
検出回路20の出力側は、夫々、コンパレータ1
4,15の一方の入力端子と接続する。コンパレ
ータ14の他方の入力端子には+の基準電圧+
Vrefが入力され、また、コンパレータ15の他
方の入力端子には−の基準電圧−Vrefが入力さ
れる。このコンパレータ14,15は検出回路2
0の出力電圧を進み信号または遅れ信号に変換す
る。発振器18の出力側は夫々アンドゲート1
6,17の他方の入力端子と接続している。
Therefore, in FIG. 2, reference numeral 10 indicates a reference signal generator, and reference numerals 11 and 12
respectively indicate frequency dividers. A gate circuit 13 is interposed between the reference signal generator 10 and the frequency divider 12, and controls the number of trigger pulses of the frequency divider 12.
The frequency divider 12 generates an output signal φB, and the frequency divider 11 generates an output signal φA. The output sides of AND gates 16 and 17 are connected to the gate circuit 13. The output side of the detection circuit 20 connected to the controlled circuit 19 which generates the feedback signals φB' and φA' substantially indicating the operating state is connected to the comparator 1, respectively.
Connect to one of input terminals 4 and 15. The other input terminal of the comparator 14 has a + reference voltage +
Vref is input, and the negative reference voltage -Vref is input to the other input terminal of the comparator 15. These comparators 14 and 15 are the detection circuit 2
Converts an output voltage of 0 to a lead or lag signal. The output side of the oscillator 18 is connected to an AND gate 1, respectively.
It is connected to the other input terminal of 6 and 17.

このような回路構成において、基準信号発生器
10は水晶発振器等を用いて出力周波数に比較し
て十分に高い周波数を発生し、分周器11におい
て分周して出力信号φAとして出力する。一方、
出力信号φBは帰還信号φA′、φB′の位相が平衡状
態においてはゲート回路13および分周器12で
分周されて出力するが、帰還信号φA′、φB′の位
相が不平衡時にはゲート回路13を制御して分周
器12の入力パルス数が増減されて出力信号φA
とφBとの位相差が制御される。すなわち、第3
図に示すようにゲート回路13はフリツプフロツ
プ21および縦属接続された二つのDタイプフリ
ツプフロツプ群22,23による同期型微分回路
を構成している。従つて、出力平衡時は入力パル
スをフリツプフロツプにて1/2に分周して分周器
12へ供給する。そこで、出力φBの位相が進む
とコンパレータ14が“H”レベルとなる。一
方、発振器18の信号は、アンドゲート16に導
入されるために前記発振器18の信号に同期して
このアンドゲート16が“H”レベルとなる。こ
の結果、ゲート回路13では同期型微分回路の動
作により基準信号発生器10の出力信号の1パル
ス分だけフリツプフロツプ21を停止する。従つ
て、出力信号φBは1パルス分の遅れを生じる
(第4図a参照)。同様にφBの位相が遅れるとコ
ンパレータ15およびゲート回路17が“H”レ
ベルとなり、ゲート回路13はフリツプフロツプ
21を1パルス分停止し、同時基準信号発生器1
0の出力信号の1パルスを分周器12へ直接入力
する。この結果、分周器12の入力パルスは1パ
ルス分増加するので、出力φBの位相は基準信号
発生器10の1パルス分の進みを生ずる(第4図
b参照)。このようにして帰還信号φA′とφB′との
位相が平衡するまで発振器18の動作周波数毎に
位相シフト動作を行う。
In such a circuit configuration, the reference signal generator 10 uses a crystal oscillator or the like to generate a frequency sufficiently higher than the output frequency, divides the frequency in the frequency divider 11, and outputs the frequency as the output signal φA. on the other hand,
The output signal φB is divided and outputted by the gate circuit 13 and the frequency divider 12 when the phases of the feedback signals φA' and φB' are balanced, but when the phases of the feedback signals φA' and φB' are unbalanced, the output signal φB is divided and output by the gate circuit 13 and the frequency divider 12. 13, the number of input pulses of the frequency divider 12 is increased or decreased, and the output signal φA
The phase difference between and φB is controlled. That is, the third
As shown in the figure, the gate circuit 13 constitutes a synchronous differential circuit including a flip-flop 21 and two cascade-connected D-type flip-flop groups 22 and 23. Therefore, when the output is balanced, the frequency of the input pulse is divided by 1/2 by the flip-flop and supplied to the frequency divider 12. Therefore, when the phase of the output φB advances, the comparator 14 becomes "H" level. On the other hand, since the signal from the oscillator 18 is introduced into the AND gate 16, the AND gate 16 goes high in synchronization with the signal from the oscillator 18. As a result, in the gate circuit 13, the flip-flop 21 is stopped by one pulse of the output signal of the reference signal generator 10 by the operation of the synchronous differentiation circuit. Therefore, the output signal φB is delayed by one pulse (see FIG. 4a). Similarly, when the phase of φB is delayed, the comparator 15 and the gate circuit 17 go to "H" level, the gate circuit 13 stops the flip-flop 21 by one pulse, and the simultaneous reference signal generator 1
One pulse of the output signal of 0 is directly input to the frequency divider 12. As a result, the input pulse of the frequency divider 12 increases by one pulse, so that the phase of the output φB advances by one pulse of the reference signal generator 10 (see FIG. 4b). In this way, the phase shift operation is performed for each operating frequency of the oscillator 18 until the phases of the feedback signals φA' and φB' are balanced.

本発明によれば、以上のように基準信号を所要
周波数に分周していることから、位相制御精度は
基準発振周波数に依存し、出力周波数が同じ場
合、基準周波数を高めると分周段が増加し、1パ
ルス当たりの分解能が向上して制御精度を向上す
ることが可能となる。なお、この場合、パルスあ
たりの位相シフト量は基準信号発生器10の発振
周波数によつて決定され、検出回路自体は位相シ
フト量には無関係となるので検出回路のゲインを
十分高くできる。また、発振器の動作周波数を被
制御出力周波数φA、φBよりも低くすることによ
り位相シフト動作を間欠動作とし、位相制御動作
時間中における位相シフト量の変化率を緩やかに
して制御量の適正化を達成することができる。従
つて、この動作により制御ループの位相ずれや、
過大な応答による制御量のオーバー等に起因する
制御ループの不安定な動作の阻止が可能となる。
According to the present invention, since the reference signal is divided into the required frequency as described above, the phase control accuracy depends on the reference oscillation frequency, and when the output frequency is the same, increasing the reference frequency increases the frequency division stage. This increases the resolution per pulse, making it possible to improve control accuracy. In this case, the amount of phase shift per pulse is determined by the oscillation frequency of the reference signal generator 10, and the detection circuit itself is independent of the amount of phase shift, so the gain of the detection circuit can be made sufficiently high. In addition, by making the operating frequency of the oscillator lower than the controlled output frequencies φA and φB, the phase shift operation is made into an intermittent operation, and the rate of change in the amount of phase shift during the phase control operation time is made gradual, thereby optimizing the control amount. can be achieved. Therefore, this operation causes a phase shift in the control loop,
It is possible to prevent unstable operation of the control loop due to an over control amount due to an excessive response.

なお、発振器18の動作周波数が低いことによ
つて制御ループの応答時間が低下し、起動時のよ
うに出力が平衡状態に達するまで相当な時間が必
要となる場合もある。然しながら、その際には発
振器18の動作周波数を高く選択することによつ
て応答時間を良くすることもできる。
Note that due to the low operating frequency of the oscillator 18, the response time of the control loop is reduced, and a considerable amount of time may be required until the output reaches an equilibrium state, such as during startup. However, in this case, the response time can also be improved by selecting a high operating frequency of the oscillator 18.

以上、本発明によれば従来技術が有したアナロ
グ動作部分をデジタル的に処理することが可能と
なり、これによつて回路構成部の特性のばらつき
や温度ドリフト等の考慮が不要になると共にレベ
ルやゲイン等のアナログ的調整も不要とすること
ができる。
As described above, according to the present invention, it is possible to digitally process the analog operation part that the conventional technology had, and this eliminates the need to consider variations in characteristics of circuit components, temperature drift, etc. Analog adjustments such as gain can also be made unnecessary.

しかも、本発明によれば、検出精度、制御量お
よび応答性を夫々個別に設定できるので高精度の
位相制御が達成される効果を奏する。
Moreover, according to the present invention, the detection accuracy, control amount, and response can be set individually, so that highly accurate phase control can be achieved.

さらにまた、検出回路の基準信号として商用電
源等の外部信号を用いれば精度の高い同期運転装
置が得られる利点もある。
Furthermore, there is an advantage that a highly accurate synchronous operation device can be obtained by using an external signal from a commercial power supply or the like as a reference signal for the detection circuit.

以上、本発明について好適な実施例を挙げて説
明したが、本発明はこの実施例に限定されるもの
ではなく、本発明の要旨を逸脱しない範囲におい
て種々の変更、改良が可能であることは勿論であ
る。
Although the present invention has been described above with reference to preferred embodiments, the present invention is not limited to these embodiments, and various modifications and improvements can be made without departing from the gist of the present invention. Of course.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の実施例のブロツク図、第2図は
本発明の一実施例のブロツク図、第3図は第2図
におけるゲート回路の具体例を示す図、第4図は
その動作説明図である。 1……基準信号、2……微分回路、3……ノコ
ギリ波発生回路、4……コンパレータ、5……変
換回路、6……検出回路、10……基準信号発生
器、11,12……分周器、13……ゲート回
路、14,15……コンパレータ、16,17…
…アンド回路、18……発振器、20……検出回
路、21……フリツプフロツプ、22,23……
Dタイプフリツプフロツプ群。
Fig. 1 is a block diagram of a conventional embodiment, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a diagram showing a specific example of the gate circuit in Fig. 2, and Fig. 4 is an explanation of its operation. It is a diagram. DESCRIPTION OF SYMBOLS 1... Reference signal, 2... Differentiation circuit, 3... Sawtooth wave generation circuit, 4... Comparator, 5... Conversion circuit, 6... Detection circuit, 10... Reference signal generator, 11, 12... Frequency divider, 13... Gate circuit, 14, 15... Comparator, 16, 17...
...AND circuit, 18 ... oscillator, 20 ... detection circuit, 21 ... flip-flop, 22, 23 ...
D type flip-flop group.

Claims (1)

【特許請求の範囲】 1 基準信号発生器からの信号を分周する第1の
分周器と、前記基準信号発生器からの信号を受け
パルス数を制御するゲート回路と、前記ゲート回
路の出力を分周する第2の分周器と、前記ゲート
回路を制御するゲート制御回路と、前記ゲート回
路の動作時間を制御する発振回路を備え、前記ゲ
ート制御回路で検出された位相ずれ信号により前
記ゲート回路を制御するようにしたことを特徴と
するデジタル式位相制御回路。 2 特許請求の範囲第1項記載の回路において、
ゲート制御回路は、二つの信号の位相差を検出す
る検出回路と、前記検出回路の出力を基準電圧と
比較する二つのコンパレータと、前記二つのコン
パレータにそれぞれ接続されたアンド回路とから
構成することを特徴とするデジタル式位相制御回
路。
[Scope of Claims] 1. A first frequency divider that divides the frequency of the signal from the reference signal generator, a gate circuit that receives the signal from the reference signal generator and controls the number of pulses, and an output of the gate circuit. a second frequency divider that divides the frequency of the gate circuit, a gate control circuit that controls the gate circuit, and an oscillation circuit that controls the operating time of the gate circuit, A digital phase control circuit characterized by controlling a gate circuit. 2. In the circuit described in claim 1,
The gate control circuit includes a detection circuit that detects a phase difference between two signals, two comparators that compare the output of the detection circuit with a reference voltage, and an AND circuit connected to each of the two comparators. A digital phase control circuit featuring:
JP59070348A 1984-04-09 1984-04-09 Digital type phase control circuit Granted JPS60214116A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59070348A JPS60214116A (en) 1984-04-09 1984-04-09 Digital type phase control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59070348A JPS60214116A (en) 1984-04-09 1984-04-09 Digital type phase control circuit

Publications (2)

Publication Number Publication Date
JPS60214116A JPS60214116A (en) 1985-10-26
JPH0467375B2 true JPH0467375B2 (en) 1992-10-28

Family

ID=13428830

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59070348A Granted JPS60214116A (en) 1984-04-09 1984-04-09 Digital type phase control circuit

Country Status (1)

Country Link
JP (1) JPS60214116A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52104855A (en) * 1976-02-27 1977-09-02 Fujitsu Ltd Phase synchronization
JPS5419346A (en) * 1977-07-13 1979-02-14 Mitsubishi Electric Corp Digital phase synchronous system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52104855A (en) * 1976-02-27 1977-09-02 Fujitsu Ltd Phase synchronization
JPS5419346A (en) * 1977-07-13 1979-02-14 Mitsubishi Electric Corp Digital phase synchronous system

Also Published As

Publication number Publication date
JPS60214116A (en) 1985-10-26

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