JPH0466127B2 - - Google Patents

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Publication number
JPH0466127B2
JPH0466127B2 JP59231917A JP23191784A JPH0466127B2 JP H0466127 B2 JPH0466127 B2 JP H0466127B2 JP 59231917 A JP59231917 A JP 59231917A JP 23191784 A JP23191784 A JP 23191784A JP H0466127 B2 JPH0466127 B2 JP H0466127B2
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JP
Japan
Prior art keywords
input
differential
output
voltage
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59231917A
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Japanese (ja)
Other versions
JPS61109309A (en
Inventor
Tatsuo Hayakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP59231917A priority Critical patent/JPS61109309A/en
Publication of JPS61109309A publication Critical patent/JPS61109309A/en
Publication of JPH0466127B2 publication Critical patent/JPH0466127B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は差動入出力演算増幅器に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to differential input/output operational amplifiers.

〔従来の技術〕[Conventional technology]

第５図は差動入出力演算増幅器の従来例の回路
図で、入力端子I1，I2の信号を差動増幅して端子
Ｑ，に出力信号を得る差動増幅器１と、両出力
信号の出力電圧を抵抗R1，R2で分圧したものを
増幅して増幅器１の適当な場所に帰還させる差動
増幅器２で構成されている。 Fig . 5 is a circuit diagram of a conventional example of a differential input / output operational amplifier. The differential amplifier 2 is configured to amplify the output voltage divided by resistors R 1 and R 2 and feed it back to an appropriate location in the amplifier 1.

抵抗R1とR2の比は通常１：１に選ばれている
ので、増幅器２の入力端子１１の電位は、出力端
子Ｑ，の出力信号が差動、つまり対称の場合は
動かなく、出力端子Ｑ，の出力信号が、同相で
動いた時のみ帰還がかかる。これを同相帰還と呼
び、差動入出力演算増幅器の出力動作中に電圧を
増幅器２の他の入力端子１２の電位V1に保つ作
用を有する。 Since the ratio of resistors R 1 and R 2 is usually chosen to be 1:1, the potential at the input terminal 11 of the amplifier 2 does not change when the output signal at the output terminal Q, is differential, that is, symmetrical, and the output Feedback is applied only when the output signals of terminal Q move in the same phase. This is called common mode feedback, and has the effect of keeping the voltage at the potential V 1 of the other input terminal 12 of the amplifier 2 during the output operation of the differential input/output operational amplifier.

第６図は、第５図の差動入出力演算増幅器を帰
還増幅器として構成した例を示している。抵抗
R3，R4，R5，R6で帰還ループが形成されてい
る。ここで、増幅器３の電圧利得をＡで表わす
と、伝達特性Ｇは Ｇ＝R3／R3＋R4＋R6／R5＋R6／１／Ａ−R3／R3＋R4−
R5／R5＋R6……(1) ここで、R4／R3＝R6／R5、電圧利得Ａは無限
大であると仮定すると Ｇ＝−R4／R3（１＋R3＋R4／R3・１／Ａ ……(2) ＝−R4／R3 ……(3) となる。さらに、R4＝R3とするとＧ＝−１とな
る。 FIG. 6 shows an example in which the differential input/output operational amplifier of FIG. 5 is configured as a feedback amplifier. resistance
A feedback loop is formed by R 3 , R 4 , R 5 , and R 6 . Here, when the voltage gain of the amplifier 3 is represented by A, the transfer characteristic G is G=R 3 /R 3 +R 4 +R 6 /R 5 +R 6 /1/A-R 3 /R 3 +R 4 -
R 5 /R 5 +R 6 ...(1) Here, assuming that R 4 /R 3 =R 6 /R 5 and that the voltage gain A is infinite, G = -R 4 /R 3 (1 + R 3 +R 4 /R 3 · 1/A ... (2) = -R 4 /R 3 ... (3) Furthermore, when R 4 = R 3 , G = -1.

第７図１，２，３はこの場合（伝達特性Ｇ＝−
１）に、同相入力電圧としてVIC、差動入力電圧
としてVIDが加わつたときの増幅器３の各点の電
位を示す図である。 Fig. 7 1, 2, and 3 are in this case (transfer characteristic G=-
1) is a diagram showing the potential at each point of the amplifier 3 when V IC is added as the common-mode input voltage and V ID is added as the differential input voltage.

左端は、入力端子IN1，IN2の電圧、中央は増
幅器３の入力端子I1，I2の電圧、右端は出力端子
Ｑ，の電圧を表わしている。 The left end represents the voltage at the input terminals IN 1 and IN 2 , the center represents the voltage at the input terminals I 1 and I 2 of the amplifier 3, and the right end represents the voltage at the output terminal Q.

第７図１は、同相入力電圧VICが零の場合を示
しており、入力端子IN1，IN2の入力信号は増幅
器３の基準電圧V1に関してVID／２だけ対称で、
出力端子Ｑ，の出力信号はこれな入力信号を反
転したものとなつている。第７図２は基準電圧
V1より正側に同相入力電圧VICが入つた場合で前
述の同相帰還の作用により出力電圧の中心は基準
電圧V1に保たれ、差動電圧のみが増幅される。
第７図３は、基準信号V1より負側に同相入力電
圧VICが入つた場合を示しており、第７図２と同
様に出力電圧は基準信号V1を中心に、差動分の
み応答することがわかる。 FIG. 71 shows a case where the common mode input voltage V IC is zero, and the input signals at the input terminals IN 1 and IN 2 are symmetrical by V ID /2 with respect to the reference voltage V 1 of the amplifier 3,
The output signal at the output terminal Q is the inverted version of this input signal. Figure 7 2 is the reference voltage
When the common-mode input voltage V IC enters on the positive side of V 1 , the center of the output voltage is maintained at the reference voltage V 1 due to the action of the common-mode feedback described above, and only the differential voltage is amplified.
FIG. 7 3 shows a case where the common mode input voltage V IC is input to the negative side of the reference signal V 1 . Similar to FIG. 7 2 , the output voltage is centered around the reference signal V 1 and only the differential component You can see that it responds.

しかしながら、この従来の差動入出力演算増幅
器では、入力インピーダンスRIB、伝達特性Ｇが
それぞれ RIB＝R3＋R5 ……(4) Ｇ＝−R4／R3×１＋R6／R4×R3＋R4／R5＋R6／１＋
R5／R3×R3＋R4／R5＋R6……(5) のように４本の抵抗R3，R4，R5，R6の抵抗値に
より決定されるので入力インピーダンスRIBは、
せいぜい数100（ＫΩ）、利得精度はせいぜい0.1％
で、例えば、信号源インピーダンスが高い場合、
また高精度が要求される場合に問題であつた。 However, in this conventional differential input/output operational amplifier, the input impedance R IB and the transfer characteristic G are R IB = R 3 + R 5 ... (4) G = -R 4 /R 3 ×1 + R 6 /R 4 × R 3 +R 4 /R 5 +R 6 /1+
R 5 /R 3 ×R 3 +R 4 /R 5 +R 6 ...The input impedance R IB is determined by the resistance values of the four resistors R 3 , R 4 , R 5 , and R 6 as shown in (5 ). teeth,
A few hundred (KΩ) at most, gain accuracy at most 0.1%
For example, if the signal source impedance is high,
This was also a problem when high precision was required.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

したがつて、本発明の目的は、入力インピーダ
ンスが極めて高く、差動利得が抵抗比によること
なく高精度が得られる差動入出力演算増幅器を提
供することである。 SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a differential input/output operational amplifier that has an extremely high input impedance and that provides high accuracy without depending on the resistance ratio of the differential gain.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、第１、第２の入力端子と、第１、第
２の出力端子と、第１、第２の入力端子に各非反
転入力端が接続され、第１、第２の出力端子に各
出力端が接続された第１、第２の差動増幅器と、
第１の出力端子と第１の差動増幅器の反転入力端
の間に接続された第１の帰還抵抗と、第２の出力
端子と第２の差動増幅器の反転入力端の間に接続
された第２の帰還抵抗と、第１、第２の出力端子
間に直列に接続された第３、第４の抵抗と、第
３、第４の抵抗の接続点が一方の入力端に、基準
電圧が他方の入力端にそれぞれ接続され、両出力
がそれぞれ第１、第２の差動増幅器の反転入力端
に帰還されている伝達コンダクタンス型の第３の
差動増幅器とを備えたことを特徴とする差動入力
出力演算増幅器。 In the present invention, each non-inverting input terminal is connected to the first and second input terminals, the first and second output terminals, and the first and second input terminals, and the first and second output terminals are connected to the first and second input terminals. first and second differential amplifiers each having an output terminal connected to the
a first feedback resistor connected between the first output terminal and the inverting input terminal of the first differential amplifier; and a first feedback resistor connected between the second output terminal and the inverting input terminal of the second differential amplifier. a second feedback resistor connected in series between the first and second output terminals, and a connection point between the third and fourth resistors connected to one input terminal; and a transconductance type third differential amplifier in which a voltage is connected to the other input terminal, and both outputs are fed back to the inverting input terminals of the first and second differential amplifiers, respectively. A differential input-output operational amplifier.

したがつて、第１、第２の差動増幅器は各入力
端子の入力信号に対して、いわゆるボルテージフ
オロワの動作をする。また、第３の差動増幅器の
出力端子の出力が同相で動いたときにのみ同相帰
還がかかり、出力端子の中心電圧（平均電圧）を
第３の差動増幅器の基準電位に保つ。 Therefore, the first and second differential amplifiers operate as a so-called voltage follower with respect to the input signal at each input terminal. Further, common mode feedback is applied only when the outputs of the output terminals of the third differential amplifier move in the same phase, and the center voltage (average voltage) of the output terminals is maintained at the reference potential of the third differential amplifier.

以上のような構成により、本発明による差動入
出力演算増幅器のの伝達利得の精度が抵抗比によ
らず向上し、入力インピーダンスが極めて高い
（その理由について、後述の実施例を詳述する）。 With the above configuration, the accuracy of the transfer gain of the differential input/output operational amplifier according to the present invention is improved regardless of the resistance ratio, and the input impedance is extremely high (the reason will be explained in detail in the embodiments described later). .

〔実施例〕〔Example〕

本発明の実施例について図面を参照しながら説
明する。 Embodiments of the present invention will be described with reference to the drawings.

第１図は本発明による差動入出力増幅器の一実
施例の回路図である。 FIG. 1 is a circuit diagram of an embodiment of a differential input/output amplifier according to the present invention.

本実施例の差動入出力演算増幅器は、入力端子
IN3，IN4、差動増幅器２１，２２、出力端子Ｑ，
Ｑ、差動増幅器２１，２２の両出力の中点検出の
ための抵抗値が１：１の抵抗R9，R10、差動増幅
器２１の反転入力端子と出力端子Ｑの間に設けら
れた抵抗R7、差動増幅器２２の反転入力端子と
出力端子の間に設けられた抵抗R8、入力端子
２４，２５がそれぞれ抵抗R9とR10の接続点、基
準電圧V1に接続され、出力端子２６，２７がそ
れぞれ差動増幅器２１，２２の反転入力端子に接
続された差動増幅器２３とからなる。したがつ
て、差動増幅器２１は入力端子IN3の入力電圧に
対して、また、差動増幅器２２は、入力端子IN4
の入力電圧に対していわゆるボルテージ・フオロ
ワ動作をする。差動増幅器２３は、伝達コンダク
タンスアンプで、出力端子２６，２７の電流出力
がそれぞれ差動増幅器２１の反転入力端子I4、差
動増幅器２２の反転入力端子I5に同相帰還されて
いる。差動増幅器２３の入力端子２４の電位は、
出力端子Ｑ，の出力が差動、つまり対称の場合
動かなく、出力端子Ｑ，の出力が同相で動いた
時のみ動き同相帰還がかかり、出力端子Ｑ，の
中心電圧（平均電圧）を差動増幅器２３の他の入
力端子２５の基準電位V1に保つ。 The differential input/output operational amplifier of this example has an input terminal
IN 3 , IN 4 , differential amplifiers 21, 22, output terminal Q,
Q, resistors R 9 and R 10 with a resistance value of 1:1 are provided between the inverting input terminal of the differential amplifier 21 and the output terminal Q for detecting the midpoint of both outputs of the differential amplifiers 21 and 22. A resistor R 7 , a resistor R 8 provided between the inverting input terminal and the output terminal of the differential amplifier 22, and input terminals 24 and 25 are connected to the connection point of the resistors R 9 and R 10 and the reference voltage V 1 , respectively, It consists of a differential amplifier 23 whose output terminals 26 and 27 are connected to inverting input terminals of differential amplifiers 21 and 22, respectively. Therefore, the differential amplifier 21 is connected to the input voltage of the input terminal IN3 , and the differential amplifier 22 is connected to the input voltage of the input terminal IN4.
It performs a so-called voltage follower operation with respect to the input voltage. The differential amplifier 23 is a transconductance amplifier, and current outputs from output terminals 26 and 27 are fed back in-phase to the inverting input terminal I 4 of the differential amplifier 21 and the inverting input terminal I 5 of the differential amplifier 22, respectively. The potential of the input terminal 24 of the differential amplifier 23 is
If the output of output terminal Q, is differential, that is, symmetrical, it will not move, but it will move only when the output of output terminal Q, moves in the same phase, and common mode feedback will be applied, and the center voltage (average voltage) of output terminal Q, will be differential. The other input terminal 25 of the amplifier 23 is maintained at the reference potential V 1 .

第２図は第１図の差動入出力演算増幅器を帰還
増幅器２８として構成した場合の回路図である。 FIG. 2 is a circuit diagram when the differential input/output operational amplifier of FIG. 1 is configured as a feedback amplifier 28.

ここで、差動増幅器２１，２２の電圧利得を
μ1，μ2で表わすと、帰還増幅器２８の伝達利得Ｈ
は Ｈ＝１−１／μ1−１／μ2 ……(6) ＝１ ……(7) で表わされる。 Here, if the voltage gains of the differential amplifiers 21 and 22 are expressed by μ 1 and μ 2 , then the transfer gain H of the feedback amplifier 28 is
is expressed as H=1-1/μ 1 -1/μ 2 ...(6) =1 ...(7).

電圧利得μ1，μ2が通常、２×105程度とれるこ
とから、伝達利得Ｈのエラーは0.01％と極めて小
さく、かつ抵抗比によらない。したがつて、従来
のように抵抗比で制限された0.1％より１桁以上
精度が向上する。また、入力インピーダンスRIB
に関しては、差動増幅器２１，２２がいずれもボ
ルテージフオロワとして働いているため、入力イ
ンピーダンスRIBは極めて高い。差動増幅器２１，
２２の差動入力インピーダンスをそれぞれRIN，
RIN′で表わすと、入力インピーダンスRIBは、 RIB＝μ1RIN＋μ2RIN′ ……(8) で表わされる。 Since the voltage gains μ 1 and μ 2 are usually about 2×10 5 , the error in the transfer gain H is extremely small at 0.01% and does not depend on the resistance ratio. Therefore, the accuracy is improved by more than one order of magnitude compared to the conventional 0.1% limited by the resistance ratio. Also, the input impedance R IB
As for the differential amplifiers 21 and 22 both work as voltage followers, the input impedance R IB is extremely high. differential amplifier 21,
22 differential input impedances as R IN ,
When expressed as R IN ′, the input impedance R IB is expressed as R IB = μ 1 R IN + μ 2 R IN ′ (8).

通常差動入力インピーダンスRINが1MΩ程度、
電圧利得μ1，μ2が２×105であることを考えると、
入力インピーダンスRIBは無限大となり、従来の
数100KΩのRIBに比して極めて高い。したがつ
て、本実施例の差動入出力演算増幅器は大きな信
号源インピーダンスの信号に対しても高精度で増
幅できる。本発明の差動入出力演算増幅器はバラ
ンス型ボルテージフオロワーと呼ぶことができ
る。 Normally the differential input impedance R IN is about 1MΩ,
Considering that the voltage gains μ 1 and μ 2 are 2×10 5 ,
The input impedance R IB is infinite, which is extremely high compared to the conventional R IB of several 100KΩ. Therefore, the differential input/output operational amplifier of this embodiment can amplify with high precision even a signal with a large signal source impedance. The differential input/output operational amplifier of the present invention can be called a balanced voltage follower.

第３図１，２，３は本実施例の差動入出力演算
増幅器に同相入力電圧としてVIC、差動入力電圧
としてVIDが加わつたときの各点の電位を示す図
である。 3 are diagrams showing the potentials at each point when V IC is applied as the common mode input voltage and V ID is applied as the differential input voltage to the differential input/output operational amplifier of this embodiment.

左端は入力端子IN3，IN4の電圧、中央は反転
入力端子I4，I5の電圧、右端は出力端子Ｑ，の
電圧を表わす。 The left end represents the voltage at the input terminals IN 3 and IN 4 , the center represents the voltage at the inverting input terminals I 4 and I 5 , and the right end represents the voltage at the output terminal Q.

同図１は、同相入力電圧VICが零の場合で、出
力端子Ｑ，の電圧はそれぞれ入力端子IN3，
IN4の電圧に追随して動く。同図２は、基準電圧
V1より正側に同相入力電圧VICが入つた場合で、
前述の同相帰還作用により出力電圧の中心は基準
電圧V1に保たれ、差動分のみが出力端子Ｑ，
に現われる。同図３は基準電圧V1より負側に同
相入力電圧VICが入つた場合で、同図２と同様に
出力端子Ｑ，の電圧は基準電圧V1を中心に差
動分のみに応答することがわかる。 Figure 1 shows the case where the common-mode input voltage V IC is zero, and the voltages at the output terminals Q and I are respectively at the input terminals IN 3 and
It moves according to the voltage of IN 4 . Figure 2 shows the reference voltage
When the common mode input voltage V IC is on the positive side of V 1 ,
Due to the common mode feedback effect mentioned above, the center of the output voltage is kept at the reference voltage V 1 , and only the differential component is applied to the output terminals Q,
appears in Figure 3 shows the case where the common-mode input voltage V IC is on the negative side of the reference voltage V 1 , and as in Figure 2, the voltage at the output terminal Q responds only to the differential component around the reference voltage V 1 . I understand that.

第４図は本発明による差動入出力演算増幅器の
他の実施例の回路図である。 FIG. 4 is a circuit diagram of another embodiment of the differential input/output operational amplifier according to the present invention.

本実施例は第２図の実施例と、抵抗R9，R10が
それぞれ入力端子I4，I5と接地間に接続されてい
る点が異なる。この場合の伝達利得H′は、R9／
R7＝R11／R8と仮定すると、 H′＝１＋R7／R9 ……(9) と表わされ、１以上の利得が取れる。この際は、
入力インピーダンスは依然として著しく高いが、
利得精度は、抵抗比R7／R9で決定される。 This embodiment differs from the embodiment shown in FIG. 2 in that resistors R 9 and R 10 are connected between input terminals I 4 and I 5 and ground, respectively. The transfer gain H′ in this case is R 9 /
Assuming R 7 =R 11 /R 8 , it is expressed as H'=1+R 7 /R 9 (9), and a gain of 1 or more can be obtained. In this case,
Input impedance is still significantly higher, but
Gain accuracy is determined by the resistance ratio R 7 /R 9 .

〔発明の効果〕〔Effect of the invention〕

本発明は以上説明したように入力信号を差動増
幅する差動増幅器（第５図の差動増幅器１）を第
１、第２の差動増幅器と２個の差動増幅器で構成
し、これら差動増幅器の非反転入力端子に入力信
号を入力し、出力端子とこれら各差動増幅器の反
転入力端子の間に帰還抵抗を接続し、さらに反転
増幅器（第５図の反転増幅器２）が２つの出力を
有し、これらをそれぞれ第１、第２の差動増幅器
の反転入力端子に帰還させるように接続したもの
であるので、入力インピーダンスが極めて高く、
差動利得が抵抗比によることなく高精度になる。 As explained above, the present invention comprises a differential amplifier (differential amplifier 1 in FIG. 5) that differentially amplifies an input signal, and includes a first differential amplifier, a second differential amplifier, and two differential amplifiers. An input signal is input to the non-inverting input terminal of the differential amplifier, a feedback resistor is connected between the output terminal and the inverting input terminal of each of these differential amplifiers, and an inverting amplifier (inverting amplifier 2 in FIG. 5) is connected to the The input impedance is extremely high because it has two outputs, and these are connected so as to feed back to the inverting input terminals of the first and second differential amplifiers, respectively.
The differential gain becomes highly accurate regardless of the resistance ratio.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明による差動入出力演算増幅器の
一実施例を示す回路図、第２図は第１図の差動入
出力演算増幅器を帰還増幅器として示した図、第
３図１，２，３は第１図の差動入出力演算増幅器
に同相入力電圧とVIC、差動入力電圧としてVIDが
加わつたときの各点の電位を示す図、第４図は本
発明による差動入出力演算増幅器の他の実施例を
示す回路図、第５図は差動入出力演算増幅器の従
来例を示す回路図、第６図は第５図の差動入出力
演算増幅器を帰還増幅器として示した図、第７図
１，２，３は第５図の差動入出力演算増幅器に同
相入力電圧としてVIC、差動入力電圧としてVIDが
加わつたときの各点の電位を示す図である。 IN3，IN4：入力端子、Ｑ，：出力端子、２
１，２２，２３：差動増幅器、R7，R8：帰還抵
抗、R9，R10：抵抗、V1：基準電圧、I4，I5：反
転入力端子、２４，２５：差動増幅器２３の入
力、２６，２７：差動増幅器２３の出力。 FIG. 1 is a circuit diagram showing an embodiment of a differential input/output operational amplifier according to the present invention, FIG. 2 is a diagram showing the differential input/output operational amplifier of FIG. 1 as a feedback amplifier, and FIG. , 3 is a diagram showing the potential at each point when the common-mode input voltage and V IC and V ID are applied as the differential input voltage to the differential input/output operational amplifier of FIG. 1, and FIG. A circuit diagram showing another example of an input/output operational amplifier, Fig. 5 is a circuit diagram showing a conventional example of a differential input/output operational amplifier, and Fig. 6 shows an example of the differential input/output operational amplifier shown in Fig. 5 as a feedback amplifier. The diagrams shown in Figures 7, 1, 2, and 3 are diagrams showing the potential at each point when V IC is applied as the common-mode input voltage and V ID is applied as the differential input voltage to the differential input/output operational amplifier in Figure 5. It is. IN 3 , IN 4 : Input terminal, Q: Output terminal, 2
1, 22, 23: Differential amplifier, R 7 , R 8 : Feedback resistor, R 9 , R 10 : Resistor, V 1 : Reference voltage, I 4 , I 5 : Inverting input terminal, 24, 25: Differential amplifier 23 input, 26, 27: output of differential amplifier 23;

Claims (1)

【特許請求の範囲】[Claims] １ 第１、第２の入力端子と、第１、第２の出力
端子と、前記第１、第２の入力端子に各非反転入
力端が接続され、前記第１、第２の出力端子に各
出力端が接続された第１、第２の差動増幅器と、
前記第１の出力端子と前記第１の差動増幅器の前
記反転入力端の間に接続された第１の帰還抵抗
と、前記第２の出力端子と前記第２の差動増幅器
の前記反転入力端の間に接続された前記第２の帰
還抵抗と、前記第１、第２の出力端子間に直列に
接続された第３、第４の抵抗と、前記第３、第４
の抵抗の接続点が一方の入力端に、基準電圧が他
方の入力端にそれぞれ接続され、両出力がそれぞ
れ前記第１、第２の差動増幅器の前記反転入力端
に帰還されている伝達コンダクタンス型の第３の
差動増幅器とを備えたことを特徴とする差動入力
出力演算増幅器。1. Each non-inverting input terminal is connected to the first and second input terminals, the first and second output terminals, and the first and second input terminals, and the first and second output terminals are connected to the first and second input terminals. first and second differential amplifiers having respective output terminals connected;
a first feedback resistor connected between the first output terminal and the inverting input terminal of the first differential amplifier; and a first feedback resistor connected between the second output terminal and the inverting input terminal of the second differential amplifier. the second feedback resistor connected between the first and second output terminals; the third and fourth resistors connected in series between the first and second output terminals;
a transconductance in which a connection point of the resistors is connected to one input terminal, a reference voltage is connected to the other input terminal, and both outputs are fed back to the inverting input terminals of the first and second differential amplifiers, respectively. A differential input/output operational amplifier comprising a third differential amplifier of the type.
JP59231917A 1984-11-02 1984-11-02 Differential input and output operational amplifier Granted JPS61109309A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59231917A JPS61109309A (en) 1984-11-02 1984-11-02 Differential input and output operational amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59231917A JPS61109309A (en) 1984-11-02 1984-11-02 Differential input and output operational amplifier

Publications (2)

Publication Number Publication Date
JPS61109309A JPS61109309A (en) 1986-05-27
JPH0466127B2 true JPH0466127B2 (en) 1992-10-22

Family

ID=16931081

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59231917A Granted JPS61109309A (en) 1984-11-02 1984-11-02 Differential input and output operational amplifier

Country Status (1)

Country Link
JP (1) JPS61109309A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5117199A (en) * 1991-03-27 1992-05-26 International Business Machines Corporation Fully differential follower using operational amplifier
JP2004297762A (en) 2003-03-11 2004-10-21 Fujitsu Ltd Common-mode feedback circuit and differential operational amplifier circuit
JP5320503B2 (en) * 2010-09-10 2013-10-23 旭化成エレクトロニクス株式会社 Amplifier circuit

Also Published As

Publication number Publication date
JPS61109309A (en) 1986-05-27

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