JPH0465945A - Ami signal reception circuit - Google Patents

Abstract

PURPOSE:To surely receive an AMI signal with no adjustment even in an input level change over a wide range by connecting a delay circuit between an output of a comparator and a load input side. CONSTITUTION:With a waveform (i) inputted to an input terminal I, a waveform (j) with a DC bias voltage -V1 superimposed thereon is applied to a noninverting input side of a comparator P1. In this case, the output of a comparator P2 passes through a delay circuit D2 and is fed to a load input side of the comparator P1. Thus, even when an undershoot resulting from nonlinear equalization is, e.g. to a noninverting input side of the comparator P1 as a positive pulse, an input in excess to the input to the load input side is given to the input to allow the comparator P1 to detect an AMI signal accurately. Thus, undesired detection is inhibited without use of a filter of the like by selecting a constant of the delay circuit against an input level of the signal (i) changed over a wide range.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an AMI signal receiving circuit used in communication devices and the like.

[Conventional technology]

Conventionally, AM I (Alternate Mark I
(nversion) signal receiving circuit is configured as shown in FIG.

In FIG. 4, the signal i inputted from the input terminal 2 is inputted to the coil N3, and outputted from the coils Nl and N2.

Coils Nl, N2. N3 are electromagnetically coupled to each other to form a transformer T1.

The output from coils Nl and N2 is DC bias voltage -Vl
are respectively superimposed and input to the positive input side of the comparator PIP2, converted to an easily processed, for example, TTL signal level, and output from the output terminals M and L.

[Problem to be solved by the invention]

When the conventional AMI signal receiving circuit described above receives the non-linearly equalized A and MI signals, the undershoot waveform shown in the period t3 of the waveform j on the positive input side of the comparator P1 in FIG. , an unnecessary signal shown by period a of waveform m in the same figure is output from comparator P1.

In order to prevent the output of such unnecessary signals from the comparators Pi and P2, for example, the DC bias voltage -■1 in FIG. A method of reducing undershoot has been taken by providing a filter as shown in FIG.

However, the undershoot waveform for non-linear equalization varies greatly depending on the characteristics of the transmission path. Therefore,
If the DC bias voltage -1 or the filter characteristics are set with sufficient margin to avoid the influence of undershoot, there is a problem that the original signal cannot be detected at the lowest input level. Furthermore, since it is necessary to change the DC bias voltage V1 and the setting values of the filter, there is a drawback that adjustment components must be used on the circuit.

An object of the present invention is to provide an AMI signal receiving circuit that operates reliably without the need for any adjustment on the circuit even when the waveform of an input signal changes over a wide range.

[Means to solve the problem]

In the AMI signal receiving circuit of the present invention, both ends of the third coil of the transformer formed by the first, second, and third coils are input terminals, and one end of the first and second coils are connected to each other. are connected to each other, a DC bias voltage is supplied to this connection point, and one ends of the first and second coils that are not connected to each other are connected to first polarity input sides of the first and second comparators, respectively. AM connected
In the I signal receiving circuit, a first delay circuit connected between the output of the first comparator and a second polarity input side of the second comparator; and a second delay circuit connected between the second polarity input side of the first comparator. The first and second delay circuits may include a resistor connected in series on the input side and a capacitor connected in parallel on the output side.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The signal input from the input terminal ■ to the third coil N3 is the first
is output from the coil N1 and the second coil N2. Coils Nl, N2 and N3 are electromagnetically coupled to each other to form a transformer T1.

The coils N1 and N2 are connected at one end to the other, and are further applied with a DC bias voltage -Vo. Therefore,
A waveform obtained by superimposing the DC bias voltage -1 on the waveform at the input terminal 2 is input to the positive input sides of the first and second comparators P1 and P2 connected to the coils N1 and N2. However, the coils N1 and N2 are connected so that the alternating current components of the waveforms applied to the positive input sides of the comparators P1 and P2 have opposite polarities.

Further, a first delay circuit D1 is connected between the output of the comparator P1 and the negative input side of the comparator P2, and a second delay circuit D2 is connected between the comparator P2 and the negative input side of the comparator P1. There is. By connecting these delay circuits DI and D2, for example, when comparator P1 is detecting a level and outputting the result to output terminal M, the detection function of comparator P2 is
It is blocked after a delay with respect to the output of 1.

The outputs of the comparators P1 and P2 are easily processed, for example, at TTL level, and are outputted from output terminals M and L, respectively.

FIG. 2 is a circuit diagram of delay circuits D1 and D2 in FIG. 1. Resistors R1 and R2 and capacitor C in the same diagram
A delay determined by a constant of 1 is implemented. Furthermore, the amplitude characteristics are simultaneously controlled by the constants of the resistors R1 and R2.

FIG. 3 shows signal waveforms at various parts of the embodiment shown in FIG.

For example, when waveform i is input to input terminal (2), waveform j on which DC bias voltage - (1) is superimposed is applied to the positive input side of comparator P1. At this time, the output of the comparator P2 (waveform J2) is simultaneously applied to the negative input side of the comparator P1 through the delay circuit D2 (waveform k).

That is, the period t1 in the waveform is due to charging in the waveform, and the period t2 is due to discharging.

As shown in FIG. 3, even if an undershoot for nonlinear equalization is applied as a positive pulse (period d in waveform j) to the positive input side of comparator P1, for example,
By applying human power exceeding this (periods t1 and t2 in waveform k>) to the negative input side, comparator P1
can accurately detect the AMI signal (waveform m). The same applies to the operation of comparator P2.

A signal that prevents the detection of all positive polarity pulses (for example, period d in waveform j) that occur for the input level of signal i that varies over a wide range (for example, signals in periods t1 and t2 of waveform) By selecting the constants of the delay circuits Di and D2 such that the voltage is higher, unnecessary detection can be prohibited without using a filter or the like.

As explained above, this embodiment prevents malfunctions due to undershoot without using a filter or the like.
The absolute value of the DC bias voltage V1 for this purpose can also be reduced. Therefore, it is possible to handle input waveforms with a short transmission path and a large undershoot, and input waveforms with a long transmission path and a low signal level without any adjustment.

〔Effect of the invention〕

As explained above, the present invention connects the first delay circuit between the output of the first comparator and the negative input side of the second comparator, and connects the output of the second comparator and the negative input side of the first comparator. By connecting a second delay circuit between the input side and the configuration, the AMI signal can be reliably received without adjustment even under wide range input level changes and undershoots due to changes in transmission path conditions. There is.

FIG.

C1... Capacitor, Dl... First delay circuit, D
2...Second delay circuit, N1...First coil, N
2...Second coil, N3...Third coil, Pl
..., first comparator, P2... second comparator, R1, R2... resistor, T1... transformer, -
■1...DC bias voltage.

Claims (1)

[Claims] Both ends of the third coil of the transformer formed by the first, second, and third coils are input terminals, and one ends of the first and second coils are connected to each other. connected,
A DC bias voltage is supplied to this connection point, and one ends of the first and second coils that are not connected to each other are connected to the first polarity input sides of the first and second comparators, respectively. In the AMI signal receiving circuit, a first delay circuit connected between the output of the first comparator and the second polarity input side of the second comparator; the second polarity input side of the first comparator;
An AMI signal receiving circuit comprising: a delay circuit. 2. The AMI signal receiving circuit according to claim 1, wherein the first and second delay circuits include a resistor connected in series on the input side and a capacitor connected in parallel on the output side.