JPH0465526B2 - - Google Patents
Info
- Publication number
- JPH0465526B2 JPH0465526B2 JP58169889A JP16988983A JPH0465526B2 JP H0465526 B2 JPH0465526 B2 JP H0465526B2 JP 58169889 A JP58169889 A JP 58169889A JP 16988983 A JP16988983 A JP 16988983A JP H0465526 B2 JPH0465526 B2 JP H0465526B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency power
- etched
- high frequency
- capacitor structure
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000463 material Substances 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 22
- 238000001020 plasma etching Methods 0.000 claims description 18
- 239000003990 capacitor Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 description 16
- 230000015556 catabolic process Effects 0.000 description 13
- 239000004020 conductor Substances 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- -1 halogen cations Chemical class 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32174—Circuits specially adapted for controlling the RF discharge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/004—Charge control of objects or beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
- H01J2237/3341—Reactive etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体製造プロセスに用いられる反
応性イオンエツチング装置の制御方法に係り、特
に中間にシリコン酸化膜、窒化膜等の薄い絶縁膜
を挟んだコンデンサ構造を有する被エツチング材
をエツチングする際に用いられる制御方法に関す
る。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method of controlling a reactive ion etching device used in a semiconductor manufacturing process, and particularly relates to a method of controlling a reactive ion etching device used in a semiconductor manufacturing process. The present invention relates to a control method used when etching a material having a capacitor structure.
半導体集積回路の高密度化が進むにつれて、そ
のゲート材，配線材等のパターン寸法は1μ程度
以下となり、この様な微細なパターン想成にはレ
ジスト等マスク材のパターン寸法に忠実にエツチ
ングを行なう技術として反応性イオンエツチング
が不可欠となつている。この反応性イオンエツチ
ングは異方性エツチングが可能であり、その基本
的構成は第１図に示すようなものであり、その基
本的原理は次に述べるようなものである。即ち、
減圧下で相対向する平行平板電極間に高周波電力
を印加（たとえば上部電極１を接地し、これに平
行な下部電極２に高周波電源３からインピーダン
ス整合器４およびブロツキングコンデンサ５を介
して高周波電力を印加）すると、両電極１，２間
で放電が行われる。これによつて、両電極１，２
間に第１図中に示すような直流電位分布が発生
し、特に高周波電力印加側の下部電極２の近傍に
は大きな直流電位差（陰極降下電圧Vdc）が発生
する。上記直流電位分布ににおいて、Vpはプラ
ズマ電位であり、プラズマ側が＋（プラス），下部
電極側が−（マイナス）である。また、前記陰極
降下電圧Vdcは、前記放電の開始後に下部電極２
に流入する電子が陽イオンより多いために下部電
極２に電子が貯えられて発生し、その大きさはイ
オンと電子の易動度の差および両電極の面積の比
に応じて発生する。
As the density of semiconductor integrated circuits continues to increase, the pattern dimensions of gate materials, wiring materials, etc. have become approximately 1μ or less, and in order to create such fine patterns, etching must be performed faithfully to the pattern dimensions of mask materials such as resist. Reactive ion etching has become an essential technology. This reactive ion etching allows anisotropic etching, and its basic structure is as shown in FIG. 1, and its basic principle is as described below. That is,
High-frequency power is applied between parallel plate electrodes facing each other under reduced pressure (for example, the upper electrode 1 is grounded, and the lower electrode 2 parallel to this is supplied with high-frequency power from a high-frequency power source 3 via an impedance matching device 4 and a blocking capacitor 5). When electric power is applied), a discharge occurs between both electrodes 1 and 2. By this, both electrodes 1 and 2
In the meantime, a DC potential distribution as shown in FIG. 1 occurs, and a large DC potential difference (cathode drop voltage V dc ) occurs particularly near the lower electrode 2 on the high-frequency power application side. In the above DC potential distribution, V p is the plasma potential, with + (plus) on the plasma side and - (minus) on the lower electrode side. Further, the cathode drop voltage V dc is set at the lower electrode 2 after the start of the discharge.
Since there are more electrons flowing into the cation than positive ions, the electrons are stored in the lower electrode 2 and generated, and the size of the electrons is generated depending on the difference in mobility between the ions and the electrons and the ratio of the areas of the two electrodes.
このため、ハロゲンを主成分とする反応性ガス
雰囲気中で放電を行なうと、ハロゲンの陽イオン
が直流電場で加速されて高周波電力印加側電極２
乃至はその上に載置される被エツチング材６に垂
直に入射する。ここで、第２図を参照して詳述す
ると、被エツチング材６のうちその上にマスク材
７が存在する部分、つまりマスク材７の影になる
部分には反応性ガスのイオン８は入射せず、マス
ク寸法に忠実な異方性エツチングが達成される。
この場合のエツチング特性は高周波電力の大きさ
に関係するもので、エツチング速度は高周波電力
にほぼ比例し、また加工形状は高周波電力の減少
につれてアンダーカツトを伴なう等方性エツチン
グになつてくる。 Therefore, when a discharge is performed in a reactive gas atmosphere containing halogen as the main component, halogen cations are accelerated by the DC electric field and the high-frequency power application side electrode 2
Or, it is perpendicularly incident on the material to be etched 6 placed thereon. Here, to explain in detail with reference to FIG. 2, ions 8 of the reactive gas are incident on the portion of the material 6 to be etched on which the mask material 7 is present, that is, the portion that is in the shadow of the mask material 7. Anisotropic etching that is faithful to the mask dimensions is achieved.
In this case, the etching characteristics are related to the magnitude of high-frequency power, and the etching speed is approximately proportional to high-frequency power, and as the high-frequency power decreases, the etching shape becomes isotropic with undercuts. .
また、前記直流電位分布において、一般にプラ
ズマ電位Vpは小さく、このプラズマ電位Vpと下
部電極２の電位との差が陰極降下電圧Vdcとして
測定されており、この陰極降下電圧Vdcと高周波
電力との関係は第３図に示すようにほぼ正比例す
る。 In addition, in the DC potential distribution, the plasma potential V p is generally small, and the difference between this plasma potential V p and the potential of the lower electrode 2 is measured as the cathode drop voltage V dc , and this cathode drop voltage V dc and the high frequency The relationship with electric power is almost directly proportional as shown in FIG.
ところで、上述したような反応性イオンエツチ
ング方法において、被エツチング材６が半導体基
板上に薄膜の絶縁膜を介して導体が形成された三
層構造を有している場合、エツチング後の耐圧試
験で絶縁膜の絶縁破壊が検出されることがある。
この絶縁破壊の原因を追及したところ、エツチン
グ終了後に高周波電力の印加を停止したとき、前
述したように下部電極２に蓄積していた電荷が逆
流して被エツチング材６中に含まれる絶縁膜の両
側に集中し、この集中が著しい場合に絶縁破壊を
引き起こすことが判明した。たとえば高周波電力
500ワツトを印加してエツチングを行ない、その
まま高周波電力の印加を停止した場合、絶縁膜に
過渡的に加わる電圧のピークはほぼその時の陰極
降下電圧Vdc（第３図からほぼ225V）に相当し、
前記絶縁膜を十分破壊する値である。ここで、反
応性イオンエツチング方法における絶縁破壊頻度
の実測データを第４図ａに示し、これと比較する
ために電荷蓄積の生じないケミカルドライエツチ
ング方法における絶縁破壊頻度の実測データを第
４図ｂに示している。これらのデータは、シリコ
ンウエハ上に400Åのゲート酸化膜を介してリン
ドープポリシリコンが形成された被エツチング材
をエツチングした場合おけるゲート耐圧（厚さ１
cm当たり換算した降伏電界）と破壊したサンプル
の個数との関係を示している。これらのデータか
ら、明らかに反応性イオンエツチング方法の場合
はケミカルドライエツチング方法に比べて小さい
降伏電圧領域でサンプルの大多数がゲート絶縁膜
の破壊を起こすことが分る。
By the way, in the above-mentioned reactive ion etching method, when the material to be etched 6 has a three-layer structure in which a conductor is formed on a semiconductor substrate with a thin insulating film interposed therebetween, the withstand voltage test after etching Dielectric breakdown of the insulating film may be detected.
When we investigated the cause of this dielectric breakdown, we found that when the application of high-frequency power was stopped after etching was completed, the charges accumulated in the lower electrode 2 flowed back, causing the insulating film contained in the material to be etched 6 to be damaged. It was found that it concentrated on both sides and caused dielectric breakdown when this concentration was significant. For example, high frequency power
When etching is performed by applying 500 watts and then stopping the application of high-frequency power, the peak of the voltage transiently applied to the insulating film is approximately equivalent to the cathode drop voltage V dc at that time (approximately 225 V from Figure 3). ,
This is a value that sufficiently destroys the insulating film. Here, the measured data of the frequency of dielectric breakdown in the reactive ion etching method is shown in Fig. 4a, and for comparison, the measured data of the frequency of dielectric breakdown in the chemical dry etching method, which does not cause charge accumulation, is shown in Fig. 4b. It is shown in These data show the gate breakdown voltage (thickness 1
It shows the relationship between the breakdown electric field (converted per cm) and the number of destroyed samples. These data clearly show that the reactive ion etching method causes gate insulating film breakdown in the majority of samples in a smaller breakdown voltage region than the chemical dry etching method.
本発明は上記の事情に鑑みてなされたもので被
エツチング材中に含まれる薄い絶縁膜を破壊しな
いで被エツチング材の異方性エツチングを行い得
る反応性イオンエツチング装置の制御方法を提供
するものである。
The present invention has been made in view of the above circumstances, and provides a method for controlling a reactive ion etching apparatus that can perform anisotropic etching of a material to be etched without destroying the thin insulating film contained in the material to be etched. It is.
即ち、本発明は、真空容器内に設けられた相対
向する電極のうち、高周波電力印加側の電極上
に、コンデンサ構造を含む被エツチング材を載置
し、反応性ガス雰囲気中で前記相対向する電極間
に高周波電圧を印加して前記被エツチング材をエ
ツチングする反応性イオンエツチング装置の制御
方法において、エツチング終了後で前記高周波電
力の印加を停止する直前に、高周波電力印加側の
電極の近傍に発生する陰極降下電圧が、被エツチ
ング材に含まれる前記コンデンサ構造の耐圧以下
になるまで高周波電力を徐々に低減させる。この
のち高周波電力の印加を停止させる。そして、こ
の高周波電力の印加停止時に、高周波電力印加側
の電極に蓄積された電荷が逆流することによつて
前記コンデンサ構造に加わる電圧がその耐圧以下
となるように構成していることを特徴としてい
る。
That is, in the present invention, a material to be etched including a capacitor structure is placed on the high-frequency power application side of opposing electrodes provided in a vacuum container, and the material to be etched is placed on the opposing electrode in a reactive gas atmosphere. In a method for controlling a reactive ion etching apparatus in which a high frequency voltage is applied between electrodes to etch the material to be etched, immediately before stopping the application of the high frequency power after etching, The high frequency power is gradually reduced until the cathode drop voltage generated in the etching becomes less than the withstand voltage of the capacitor structure included in the material to be etched. Thereafter, the application of high frequency power is stopped. The present invention is characterized in that when the application of the high frequency power is stopped, the electric charge accumulated in the electrode on the high frequency power application side flows backward, so that the voltage applied to the capacitor structure becomes equal to or lower than its withstand voltage. There is.
上記構成の制御方法であると、被エツチング材
に含まれるコンデンサ構造が、高周波電力印加側
の電極に蓄積された電荷が逆流することによつ
て、前記コンデンサ構造の導体部に集中して生ず
る電圧により、破壊されることを防止できる。 In the control method having the above configuration, the capacitor structure included in the material to be etched generates a voltage that is concentrated on the conductor portion of the capacitor structure due to the reverse flow of charges accumulated in the electrode on the side to which high-frequency power is applied. This can prevent it from being destroyed.
〔発明の実施例〕
以下、図面を参照して本発明の一実施例を詳細
に説明する。[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
第５図は通常の反応性イオンエツチング装置の
一例を示しており、５０は真空容器、５１は反応
性ガスの導入孔、５２は排気孔、５３は接地され
た上部電極、５４は高周波電力が印加される下部
電極、５５は高周波電源、５６はブロツキングコ
ンデンサを内蔵したインピーダンス整合器、５７
は絶縁体である。そして、５８は前記下部電極５
４に載置された被エツチング材であり、本例では
単結晶シリコン基板表面を400Å酸化してゲート
酸化膜とし、その上にCVD（化学気相成長）法に
よつてポリシリコンを堆積し、更にこのポリシリ
コン中にリンを拡散したのち10mm2のレジストパタ
ーン（エツチングマスク）を形成したウエハを用
いた。 FIG. 5 shows an example of a conventional reactive ion etching apparatus, in which 50 is a vacuum container, 51 is a reactive gas introduction hole, 52 is an exhaust hole, 53 is a grounded upper electrode, and 54 is a high-frequency power source. 55 is a high frequency power supply, 56 is an impedance matching device with a built-in blocking capacitor, 57 is a lower electrode to which voltage is applied;
is an insulator. 58 is the lower electrode 5
In this example, the surface of the single-crystal silicon substrate is oxidized to 400 Å to form a gate oxide film, and polysilicon is deposited on it by CVD (chemical vapor deposition). Further, a wafer was used in which phosphorus was diffused into the polysilicon and a 10 mm 2 resist pattern (etching mask) was formed thereon.
上記装置を用いて反応性イオンエツチングを行
う場合、本発明に係わる制御方法によれば、先ず
真空ポンプにより排気孔５２を通じて真空容器５
０内に減圧を行なつて真空容器５０内を所定の真
空度（たとえば0.08Torr）に保ち、ガスス導入
孔５１より反応性ガス（本例ではCl2とH2の混合
ガス）を導入し、高周波電源５５からインピーダ
ンス整合器５６を通じて下部電極５４にたとえば
500ワツトの高周波電力を印加する。これによつ
て、両電極５３，５４間で放電が行われ、両電極
５３，５４間には前述したような直流電位分布が
発生し、特に下部電極５４の近傍には陰極降下電
圧Vdcが発生し、反応性ガスの陽イオンが加速さ
れて下部電極５４上のウエハ表面に垂直に入射
し、ウエハ上のリンドープポリシリコン（ゲート
材）がが異方的にエツチングされる。 When performing reactive ion etching using the above-mentioned apparatus, according to the control method according to the present invention, first, the vacuum container 5 is heated through the exhaust hole 52 by a vacuum pump.
The pressure inside the vacuum container 50 is maintained at a predetermined degree of vacuum (for example, 0.08 Torr) by reducing the pressure to within 0, and a reactive gas (in this example, a mixed gas of Cl 2 and H 2 ) is introduced from the gas introduction hole 51. For example, from the high frequency power source 55 to the lower electrode 54 through the impedance matching device 56.
Apply 500 watts of high frequency power. As a result, a discharge occurs between the electrodes 53 and 54, and a DC potential distribution as described above is generated between the electrodes 53 and 54, and a cathode drop voltage V dc is generated particularly near the lower electrode 54. The generated positive ions of the reactive gas are accelerated and are perpendicularly incident on the wafer surface on the lower electrode 54, so that the phosphorus-doped polysilicon (gate material) on the wafer is anisotropically etched.
そして、エツチング終了後で高周波電力の印加
を停止する直前に、高周波電力を50ワツト程度ま
で徐々に低減する。これによつて、ゲート絶縁膜
を挾んだコンデンサ構造に貯えられる電圧合計が
ゲート絶縁膜の耐圧（ゲート酸化膜が400Å程度
の場合には耐圧は30〜40Vである）より小さい値
になるまで低下する。こののち、高周波電力の印
加を停止すれば、ゲート酸化膜に過渡的な高電圧
が印加されることもなく、その絶縁破壊は殆んど
生じなくなる。ここで、高周波電力を上述のよう
に50ワツトに減少したときの陰極降下電圧Vdcは
第３図から分るようにほぼ25Vであり、こののち
高周波電力の印加を停止した場合における絶縁破
壊頻度の実測データを第６図に示す。このデータ
を従来例の反応性イオンエツチング方法における
第４図ａのデータと対比すれば明らかな通り、小
さい降伏電界でゲート絶縁膜の破壊を起こす個数
が圧倒的に減少しており、本発明方法は大変効果
的であることが分る。 Then, immediately before stopping the application of high-frequency power after etching, the high-frequency power is gradually reduced to about 50 watts. As a result, the total voltage stored in the capacitor structure sandwiching the gate insulating film becomes smaller than the withstand voltage of the gate insulating film (if the gate oxide film is about 400 Å, the withstand voltage is 30 to 40 V). descend. After that, if the application of high frequency power is stopped, no transient high voltage will be applied to the gate oxide film, and dielectric breakdown will hardly occur. Here, when the high frequency power is reduced to 50 Watts as mentioned above, the cathode drop voltage V dc is approximately 25 V as shown in Figure 3, and the dielectric breakdown frequency when the high frequency power is stopped after that is Figure 6 shows the measured data. Comparing this data with the data in Figure 4a for the conventional reactive ion etching method, it is clear that the number of gate insulating films that break down due to a small breakdown electric field is overwhelmingly reduced, and the method of the present invention turns out to be very effective.
なお、本発明方法は、上記実施例では絶縁膜が
窒化膜の場合でも上記実施例と同様に有効であ
り、更に被エツチング材がゲート絶縁膜の直上の
導体に限らず、絶縁膜の上に中間層をしてその上
に堆積された導体であつても絶縁膜を挾んだコン
デンサ構造を含んでいる場合には上記実施例と同
様に有効である。 Note that the method of the present invention is as effective as in the above embodiment even when the insulating film is a nitride film, and furthermore, the material to be etched is not limited to the conductor directly above the gate insulating film, but also when the material to be etched is not limited to the conductor directly above the gate insulating film. Even if the conductor is an intermediate layer and is deposited thereon, it is effective in the same way as the above embodiment if it includes a capacitor structure sandwiching an insulating film.
上述したように、本発明の反応性イオンエツチ
ング装置の制御方法によれば、被エツチング材中
に含まれる薄い絶縁膜を破壊しないで被エツチン
グ材の異方性エツチングを行なうことができる。
As described above, according to the method of controlling a reactive ion etching apparatus of the present invention, the material to be etched can be anisotropically etched without destroying the thin insulating film contained in the material to be etched.
第１図は反応性イオンエツチング方法の基本的
原理を説明するために示す図、第２図は第１図の
被エツチング材における異方性エツチングの状態
を示す断面図、第３図は第１図の下部電極付近に
発生する陰極降下電圧と高周波電力との関係を示
す特性図、第４図ａおよび第４図ｂはそれぞれ対
応して反応性イオンエツチング方法およびケミカ
ルドライエツチング方法における被エツチング材
中の絶縁膜の絶縁破壊頻度の実測データを示すグ
ラフ、第５図は本発明に係る制御方法が適用され
る反応性イオンエツチング装置の一例を示す構成
説明図、第６図は本発明方法における被エツチン
グ材中の絶縁膜の絶縁破壊頻度の実測データを示
すグラフである。
５０……真空容器、５１……ガス導入孔、５２
……排気孔、５３……上部電極、５４……下部電
極、５５……高周波電源、５８……被エツチング
材。
FIG. 1 is a diagram shown to explain the basic principle of the reactive ion etching method, FIG. 2 is a cross-sectional view showing the state of anisotropic etching on the material to be etched in FIG. 1, and FIG. Figure 4a and Figure 4b are characteristic diagrams showing the relationship between the cathode drop voltage generated near the lower electrode and the high frequency power, respectively, and the materials to be etched in the reactive ion etching method and the chemical dry etching method, respectively. 5 is a diagram illustrating the configuration of an example of a reactive ion etching apparatus to which the control method according to the present invention is applied. FIG. 3 is a graph showing actually measured data of dielectric breakdown frequency of an insulating film in a material to be etched. 50... Vacuum container, 51... Gas introduction hole, 52
... Exhaust hole, 53 ... Upper electrode, 54 ... Lower electrode, 55 ... High frequency power supply, 58 ... Material to be etched.
Claims (1)
ち、高周波電力印加側の電極上に、コンデサ構造
を含む被エツチング材を載置し、反応性ガス雰囲
気中で前記相対向する電極間に高周波電圧を印加
して前記被エツチング材をエツチングする反応性
イオンエツチング装置の制御方法において、 エツチング終了後で前記高周波電力の印加を停
止する直前に、前記高周波電力印加側の電極の近
傍に発生する陰極降下電圧が前記コンデンサ構造
の耐圧以下となるまで高周波電力を徐々に低減
し、こののち前記高周波電力の印加を停止させ、
この高周波電力の印加停止時に、前記高周波電力
印加側の電極に蓄積された電荷が逆流することに
よつて前記コンデンサ構造に加わる電圧が、前記
コンデンサ構造の耐圧以下となるように構成され
たことを特徴とする反応性イオンエツチング装置
の制御方法。[Scope of Claims] 1. A material to be etched including a capacitor structure is placed on the electrode on the high-frequency power application side among opposing electrodes provided in a vacuum container, and the material to be etched is placed on the electrode on the high-frequency power application side, and In a method of controlling a reactive ion etching apparatus, in which the material to be etched is etched by applying a high frequency voltage between electrodes facing each other, the electrode on the high frequency power application side is gradually reducing the high frequency power until the cathode drop voltage generated near the capacitor structure becomes equal to or lower than the withstand voltage of the capacitor structure, and then stopping the application of the high frequency power,
The configuration is such that when the application of high frequency power is stopped, the voltage applied to the capacitor structure becomes equal to or lower than the withstand voltage of the capacitor structure due to the reverse flow of the charge accumulated in the electrode on the high frequency power application side. Features: Control method for reactive ion etching equipment.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16988983A JPS6062124A (en) | 1983-09-14 | 1983-09-14 | Reactive-ion etching method |
| US06/608,449 US4566941A (en) | 1983-05-10 | 1984-05-09 | Reactive ion etching method |
| DE8484105249T DE3483800D1 (en) | 1983-05-10 | 1984-05-09 | REACTIVE ION NETWORK METHOD. |
| EP84105249A EP0133452B1 (en) | 1983-05-10 | 1984-05-09 | Reactive ion etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16988983A JPS6062124A (en) | 1983-09-14 | 1983-09-14 | Reactive-ion etching method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6062124A JPS6062124A (en) | 1985-04-10 |
| JPH0465526B2 true JPH0465526B2 (en) | 1992-10-20 |
Family
ID=15894833
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16988983A Granted JPS6062124A (en) | 1983-05-10 | 1983-09-14 | Reactive-ion etching method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6062124A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55111134A (en) * | 1979-02-19 | 1980-08-27 | Mitsubishi Electric Corp | Method of gas plasma etching |
| JPS573214A (en) * | 1980-06-04 | 1982-01-08 | Sanyo Electric Co Ltd | Manufacture of nagnetic head |
| JPS58140125A (en) * | 1982-02-16 | 1983-08-19 | Matsushita Electric Ind Co Ltd | Dry etching method |
-
1983
- 1983-09-14 JP JP16988983A patent/JPS6062124A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55111134A (en) * | 1979-02-19 | 1980-08-27 | Mitsubishi Electric Corp | Method of gas plasma etching |
| JPS573214A (en) * | 1980-06-04 | 1982-01-08 | Sanyo Electric Co Ltd | Manufacture of nagnetic head |
| JPS58140125A (en) * | 1982-02-16 | 1983-08-19 | Matsushita Electric Ind Co Ltd | Dry etching method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6062124A (en) | 1985-04-10 |
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