JPS61156816A - Plasma etching apparatus - Google Patents

Abstract

PURPOSE:To control an ion acceleration voltage freely by impressing a high-frequency power and a DC bias voltage on the same electrode. CONSTITUTION:A DC bias power source 22 is connected to an upper electrode 13, which is a cathode, through the intermediary of a choke circuit 21 for checking a high-frequency power. If a DC bias voltage is not impressed, an ion acceleration voltage on the anode side is so small as about several tens volts. When a positive-direction bias is impressed on the cathode side, a plasma voltage is also increased, while the ion acceleration voltage is increased on the anode side. When a negative-direction bias is impressed on the cathode side, the value of the ion acceleration voltage does not become small so much, since the plasma voltage is always found further in the positive direction than all the sides being in contact with plasma. According to this construction, it turns possible to vary the ion acceleration voltage in a large degree independently from other factors by the adjustment of the DC bias power source 22, in comparison with an apparatus of an anode couple system wherein the ion acceleration voltage is low.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a plasma etching apparatus, and is particularly used in an etching process during the manufacturing process of semiconductor devices.

[Technical background of the invention and its problems] Dry etching technology using plasma is becoming common in the manufacturing process of semiconductor devices, especially high-density semiconductor integrated circuit devices. The biggest reason why this technology is especially essential in the manufacturing process of high-density semiconductor integrated circuit bags M1 (LSI) is that it is possible to form a pattern of a predetermined material faithfully to the pattern of a resist, etc., which is a mask. It has good processability (anisotropic etching). Other requirements for etching technology include selective etching properties between materials, high-speed etching properties with excellent mass production, and low irradiation damage properties to prevent damage to LSIs. However, each of the above-mentioned requirements contradicts each other in some respects, and it can be said that there is no etching apparatus that fully satisfies all of the requirements. The main reason for this is that the plasma etching apparatus uses non-equilibrium plasma, which is a difficult-to-control system in which many parameters are intricately intertwined.

Below, the characteristics and drawbacks of two typical conventional dry etching apparatuses using plasma will be described.

First, the RIE method (reactive ion etching method) of the cathode couple will be described. 1st
FIG. 3 is a schematic diagram of the configuration of this type of device. A flat plate lower electrode 12 insulated from the vessel 11 is provided at the bottom of the vacuum vessel 11, and a flat plate upper electrode 13 facing the flat plate lower electrode 12 is further provided at the upper part. A member to be etched 14 made of a semiconductor substrate or the like is placed on the lower electrode 12 , and a high frequency power source 11 is connected to the lower electrode 12 via a blocking capacitor 15 and a matching network 16 . Further, the upper electrode 13 and the container 11 are grounded. The reactive gas is introduced into the vacuum vessel 11 through the gas introduction hole 18 and exhausted through the exhaust hole 19, and the gas pressure within the vacuum vessel 11 is maintained at a predetermined pressure.

In such a device, by applying high frequency power to the lower electrode 12 from the high frequency power supply 17, the lower electrode 1
A discharge is excited between the upper electrode 2 and the upper electrode 13. At this time, a part of the reaction gas inside the container 11 is brought into a plasma state. The active species created in the plasma react with the member 14 to be etched, and the volatile products are removed by exhaust gas.

Here, in a non-equilibrium plasma state where the frequency of the high frequency power source 17 is 13.56 MHI, heavy ions hardly move in the electric field, whereas light electrons have high mobility.
It collides with the electrode and is mainly accumulated in the lower electrode 12 and blocking capacitor 15. Therefore, the lower electrode 1
2 is negatively charged, and since plasma has many positive ions, it is positively charged. At this time, the average potential distribution inside the vacuum vessel 11 is as shown in FIG. 14, with the upper electrode 13 (anode) at the ground potential of 0, the plasma at the positive plasma potential Vp, and the lower electrode 12 (cathode) at the ground potential of 0. Negative potential VC
each. Therefore, a large potential difference Vdc (VdC-Vp-Vc) is generated in the space directly above the lower electrode 12. This potential difference, ie, the value of the ion acceleration voltage, reaches several hundreds of volts in normal RIE. When the potential difference Vdc is large, the etching characteristics are greatly affected as follows.

(a) Excellent anisotropy is achieved because ions with high energy are incident perpendicularly to the member to be etched. Also,
Primarily due to the effect of ions, the etching rate is relatively high for the material being etched.

(b) The effect of ions is large, the reaction approaches that of a sputtering method, and the selectivity of the amount of material is poor.

(C) Ions with high energy are incident on the member to be etched, causing great damage.

In order to eliminate disadvantages (1) and (C) of the above effects, it is sufficient to reduce the potential difference VdC, but in the conventional RIE method, VdC cannot be controlled independently, and other Vdc is controlled by changing parameters such as high frequency power and gas pressure. Therefore, a decrease in the potential difference Vdc causes deterioration of the etching characteristics, and it is practically difficult to change the potential difference VdC in the RIE method.

The second type of conventional dry etching equipment that uses plasma is an anode couple plasma etching system. FIG. 15 is a schematic diagram of a device of this type. In this type of apparatus, unlike the RIE type described above, the member to be etched 14 is placed on the grounded lower electrode 12, and a blocking capacitor 15 and a matching network are placed on the upper electrode 13 facing the lower electrode 12. A high frequency power source 17 is connected via 16.

In this apparatus, as can be easily inferred from the potential distribution diagram of FIG. 14, the energy of the ions incident on the member to be etched 14 is only Vp, which is as small as several tens of volts at most.

Therefore, the characteristics of this method are as follows, contrary to the RIE method.

(a) For materials that have insufficient anisotropy and are etched mainly by ions, the etching rate is low.

(b) Selectivity is relatively large.

(C) Less damage to the member to be etched.

As mentioned above, all items such as excellent anisotropy, high selectivity, and low damage are required for application to LSI. For some of these items, it is better for the potential difference Vdc to be higher, and for other items, it is more advantageous for it to be lower. For this purpose, it is essential to control the potential difference VdC. However, in conventional devices such as RIE, as described above, in order to control this potential difference vdC, only indirect means such as adjusting high frequency power or adjusting gas pressure can be taken.
This results in deterioration of optical characteristics, such as a decrease in etching speed. Furthermore, in the plasma etching method, it is virtually impossible to increase the potential difference Vdc. For this reason, there has been a strong desire for a technique that can independently control the potential difference Vdc.

[Object of the Invention] The present invention has been made in consideration of the above-mentioned circumstances and circumstances, and its object is to provide a plasma etching apparatus in which the ion acceleration voltage can be freely controlled.

[Summary of the Invention] In order to achieve the above object, the plasma etching apparatus of the present invention originally uses a low ion acceleration voltage in order to make the ion acceleration voltage freely controllable while taking advantage of the advantages of the conventional apparatus. Based on the anode couple method, high-frequency power and DC bias voltage are applied to the same electrode.

[Embodiment of the Invention] Hereinafter, an embodiment of a plasma etching apparatus according to the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram showing an outline of the device.
The same reference numerals are given to the parts corresponding to those of the conventional apparatus shown in FIG. 3 and FIG. 15 for explanation.

This device is basically the same as the plasma etching method shown in FIG. 15, but in addition, a direct current bias %I source 22 is applied to the upper electrode 13, which is the cathode, through a choke circuit 21 for blocking high frequency power. is connected. The output voltage of this DC bias power supply 22 can be freely adjusted.

In this example device, potential distribution states in the vacuum vessel 11 when various DC bias voltages are applied to the upper electrode 13 are shown in potential distribution diagrams in FIGS. 2 to 4.

The one in FIG. 2 is when the DC bias voltage is O, that is, when no DC bias voltage is applied. The ion accelerating voltage (2) on the side of the member to be etched (anode side) is Vp-Va, which is as small as several tens of volts at most.

The one in FIG. 3 is when a positive direction bias vb is applied to the cathode side as a DC bias voltage. Vc increases by the DC bias voltage vb, and the plasma voltage Vp also increases accordingly. Therefore, the ion acceleration voltage V=Vp - Va increases on the anode side.

In contrast to the case shown in FIG. 3, the case shown in FIG. 4 is obtained when a negative bias is applied to the cathode side as a DC bias voltage vb. Although Vc drops by the DC bias voltage vb, since the plasma voltage Vp is always in a more positive direction than all the surfaces in contact with plus÷, the value of Vp - va does not become very small.

According to this type of device, the DC bias power supply 22 is
By adjusting the ion acceleration voltage, it is now possible to greatly change the ion acceleration voltage independently of other factors. Originally, this ion accelerating voltage is as low as several tens of volts, so according to this embodiment, this accelerating voltage can be changed from several tens of volts to a DC bias voltage of +11 volts.
It can be freely controlled within a wide range up to a maximum value of 22.

By freely changing the ion acceleration voltage in this way, the degree of freedom of the culm during etching is greatly increased.

Next, some of the effects are shown below. First, the case of etching gate polycrystalline silicon having an MO8 structure will be described. FIG. 5 is a cross-sectional view schematically showing the MO8 structure. Dry etching technology is used for selective etching of the polycrystalline silicon W431, but at this time it is important to precisely control the width of the polycrystalline silicon layer 31 and to avoid damaging the underlying gate oxide film 32 and silicon diffusion layer 33. It is. When this polycrystalline silicon layer 31 is etched using the normal RIE method, it has excellent anisotropy and can be processed with high precision, resulting in a sharp shape as shown in the cross-sectional view of FIG. In addition, in FIG. 6, 34 is a resist mask. However, the selection ratio with the base gate oxide film 32 is insufficient, and the base gate oxide 1I32 of the portion other than the patterned polycrystalline silicon 1pi31 is insufficient.
decreases considerably during overetching. Then, impurity atoms pass through this thinned gate oxide film 32 and are implanted into the silicon diffusion W433 below (this tendency is large in the RIE method because the ion energy is large).
Defects in the MO8 structure are likely to occur. As a more serious damage, the RIE method induces dielectric breakdown in the gate oxide film 32. That is, in the RIE method, the member to be etched, in this case an MO8 type semiconductor device having an MO3 structure, is placed on the electrode on the side to which high-frequency power is applied, so that excess charge stored in the electrode is absorbed by the high-frequency power source. When the MO8 type semiconductor device is off, a high voltage is applied to the gate thereof, and as a result, dielectric breakdown is induced. An example of this is shown in FIG. In other words, Figure 8 shows the results of examining the breakdown voltage of the gate when a polycrystalline silicon layer was deposited on a gate oxide film with a thickness of 200 mm and this polycrystalline silicon layer was selectively etched using the RIE method.・Ru. As can be seen from FIG. 8, leakage occurred in most of the gates when a small applied voltage (2 MV/Cm or less) was applied, and this was because dielectric breakdown had already occurred during etching.

On the other hand, when the polycrystalline silicon layer 31 is etched using an anode couple method, the problems of selectivity and damage to the underlying film are resolved as expected, but the anisotropy is poor and the cross-sectional view shown in FIG. The machined shape will be as shown. Furthermore, the effect of ions is small and the etching rate is insufficient.

However, if the apparatus according to the above embodiment is used, it is possible to perform etching that takes advantage of the advantages of both of the above methods. That is, in the configuration shown in FIG. 1, a positive DC bias voltage is applied to the upper electrode 13 at the beginning of the etching process to boost the ion accelerating voltage on the anode side to about several hundred volts, thereby increasing the anisotropy. Etching is performed under conditions of high etching speed, and during the latter stages of etching progress and over-etching, the DC bias voltage is reduced to perform etching under conditions of high selectivity and low damage. Such an etching sequence is shown in FIG. The solid line in the figure shows the ion accelerating voltage, the dashed line shows the etching rate of the polycrystalline silicon layer, and the broken line shows the etching rate of the gate oxide film. As a result of adopting this method, it has become possible to perform etching with less loss of the underlying insulating film while maintaining anisotropy. Furthermore, regarding the dielectric breakdown of the gate oxide film, a sufficient gate breakdown voltage was obtained as shown in FIG.

Next, a case will be described in which the apparatus of this embodiment is used to etch a film having a step structure.

As the density of LSI increases, it is often necessary to etch a film having a multilayer structure. An example of this is etching a film 42 deposited on a base film 41 that has been selectively patterned in advance in the cross-sectional view of FIG. At this time, the base I! 141 has a constriction at the lower part where it contacts the substrate 43, and llI42 often bites into this constriction. In this case, when anisotropic etching is performed, a phenomenon occurs in which the film 42 partially remains at the dug-in portion, as shown in the cross-sectional view of FIG. Such remaining leads to a short circuit phenomenon between wiring lines. However, by using the apparatus of the embodiment described above, first performing anisotropic etching with a DC bias voltage applied, and then performing highly anisotropic etching without applying a DC bias voltage after completing this etching, the above-mentioned method could be achieved. Etching at the biting part! 1942 can be prevented from remaining partially.

As described above, in the actual etching process, the process margin is often expanded by controlling the ion acceleration voltage, and it can be said that the present invention apparatus can provide a very effective means in such cases.

[Effects of the Invention] As explained above, according to the present invention, it is possible to provide a plasma etching apparatus in which the ion acceleration voltage can be freely controlled.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an outline of a device according to an embodiment of the present invention, FIGS. 2 to 4 are potential distribution state diagrams for explaining the device of the above embodiment, respectively, and FIGS. 5 to 7 8 is a cross-sectional view for explaining the above embodiment device, respectively.
9 and 9 are characteristic diagrams for comparing the above embodiment device and the conventional device, respectively, FIG. 10 is a sequence diagram showing an example of the method of applying DC upper pressure in the above embodiment device, and FIGS. Fig. 12 is a sectional view 1 for explaining the device of the above embodiment, Fig. 13 is a configuration diagram showing an outline of a conventional device, Fig. 14 is a potential distribution diagram in the device of Fig. 13, and Fig. 15 is a diagram of other devices. 1 is a configuration diagram showing an outline of a conventional device. 11... Vacuum container, 12... Flat plate lower electrode, 13.
... flat plate upper electrode, 14 ... member to be etched, 15
...Blocking capacitor, 16...Matching network, 17...High frequency power supply, 18...Introduction hole, 19...Exhaust hole, 21...Choke circuit, 22
...DC bias power supply. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 4!13 Figure 4 Figure 5 Figure 6 Figure 8 Figure 9 Figure 1 Repulsion (MV/Cm). Figure 11 Figure 13 VaC-

Claims (5)

[Claims] (1) First and second flat plate electrodes installed opposite to each other in a vacuum container, means for applying a reference potential to the first flat plate electrode, and a high frequency signal and a direct current to the second flat plate electrode. 1. A plasma etching apparatus comprising: means for applying a signal. (2) The plasma etching apparatus according to claim 1, wherein the frequency of the high frequency signal is set to 13.56 MHz. (3) The plasma etching apparatus according to claim 1, wherein a plurality of types of reactive gases are supplied into the vacuum container at predetermined flow rates and predetermined pressures. (4) The plasma etching apparatus according to claim 1, wherein a member to be etched is placed on the first flat electrode. (5) The voltage value of the DC signal applied to the second flat plate electrode is controlled so as to be increased at the beginning of the progress of etching the member to be etched and decreased at the later stage. The plasma etching apparatus described in .