JPH0642467B2 - Plasma etching method - Google Patents

Plasma etching method

Info

Publication number
JPH0642467B2
JPH0642467B2 JP57191910A JP19191082A JPH0642467B2 JP H0642467 B2 JPH0642467 B2 JP H0642467B2 JP 57191910 A JP57191910 A JP 57191910A JP 19191082 A JP19191082 A JP 19191082A JP H0642467 B2 JPH0642467 B2 JP H0642467B2
Authority
JP
Japan
Prior art keywords
electrode
etched
etching method
material layer
plasma etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57191910A
Other languages
Japanese (ja)
Other versions
JPS5982729A (en
Inventor
正弘 柴垣
徹 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP57191910A priority Critical patent/JPH0642467B2/en
Publication of JPS5982729A publication Critical patent/JPS5982729A/en
Publication of JPH0642467B2 publication Critical patent/JPH0642467B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は平行平板型電極を有するプラズマエツチング装
置を用い、シリコン酸化膜あるいは窒化膜上に堆積され
た被エツチング材料をエツチングするにおいて、被エツ
チング材料配置側電極と、被エツチング材料を構成して
いる半導体基板の間に絶縁物を置くことにより、電荷蓄
積によるシリコン酸化膜あるいは窒化膜の耐圧劣化を抑
制する信頼性の高いプラズマエツチング方法に関する。
Description: TECHNICAL FIELD OF THE INVENTION The present invention uses a plasma etching apparatus having parallel plate electrodes to etch an etching target material deposited on a silicon oxide film or a nitride film. The present invention relates to a highly reliable plasma etching method that suppresses the breakdown voltage deterioration of a silicon oxide film or a nitride film due to charge accumulation by placing an insulator between a material placement side electrode and a semiconductor substrate that constitutes a material to be etched.

〔従来技術とその問題点〕[Prior art and its problems]

近年、集積回路(IC)製造プロセスでは、ICの高集積
度化,高速度化に伴い素子の微細加工が強く要求されて
いる。このため、アンダーカツトの無い垂直なエツチン
グ形状が達成できる反応性イオンエツチング(Reactive
Ion Etching:RIE)方法が注目を浴びている。例えば
パターンを形成すべき材料が置かれた電極に高周波電力
を印加することにより、チャンバー内に導入した減圧状
態の反応性ガスをグロー放電させる。この時この高周波
電極には電子とイオンの易動度の差及び高周波電極と対
向電極(この場合接地電位のチヤンバー内壁も含む)の
面積比の違いにより負の自己バイアスが生じる。この負
の自己バイアスは陰極降下電圧と呼ばれ、接地電位から
計つてVdcで示される。エツチング種が吸着した被エツ
チング材料表面にVdcにより加速されたプラズマ中の正
イオンが垂直に衝突して、エツチング種と被エツチング
材料間の反応を促進させて、被エツチング材料をガス化
することでエツチングを進行する。
2. Description of the Related Art In recent years, in integrated circuit (IC) manufacturing processes, there is a strong demand for fine processing of devices as the integration density and speed of ICs increase. Therefore, reactive ion etching (Reactive Ion Etching) that can achieve vertical etching shape without undercut
Ion Etching: RIE) method is in the spotlight. For example, by applying high-frequency power to the electrode on which the material to form the pattern is placed, the reactive gas in the reduced pressure state introduced into the chamber is glow-discharged. At this time, a negative self-bias is generated in the high frequency electrode due to the difference in mobility of electrons and ions and the difference in the area ratio between the high frequency electrode and the counter electrode (including the inner wall of the chamber at the ground potential in this case). This negative self-bias is called the cathode drop voltage, and is shown as Vdc, measured from ground potential. The positive ions in the plasma accelerated by Vdc vertically collide with the surface of the material to be etched adsorbing the etching species to accelerate the reaction between the etching species and the material to be etched, thereby gasifying the material to be etched. Proceed with etching.

例えば、酸化シリコンにコンタクト孔を関ける場合には
CF4+H2やCHF3を用いると良く、又シリコンウエーハ或い
は電極配線材料として、多用されている多結晶シリコン
及びアルミニウム(Al)をエツチングする場合は、Cl4
やCl2等の塩素系ガスが用いられる。
For example, when making contact holes in silicon oxide,
CF 4 + H 2 or CHF 3 may be used. Also, when etching polycrystalline silicon and aluminum (Al) which are widely used as silicon wafers or electrode wiring materials, Cl 4 is used.
A chlorine-based gas such as Cl 2 or Cl 2 is used.

電極材料に真空容器を構成しているステンレスを用いる
と、エツチング中、鉄(Fe)やNi(ニツケル)が放出さ
れ、そのことにより、素子が重金属汚染して、著しく劣
化する。そのため、石英(SiO2)やアルミナ(Al2O3
で電極を、被覆すると重金属汚染は阻止可能となるが、
SiO2やAl2O3から、酸素が放出される。その微量の酸素
が系内に混入すると、塩素ラジカルが多量に発生し、多
結晶シリコンやアルミニウム、特にリン(P)やヒ素(A
s)を含んだ多結晶シリコンはアンダーカツトが著しく
生じやすくなる。一方、ポリエステル等の高分子薄膜は
上記した欠点を除去できるものであるが、エツチング
中、高分子薄膜からの重合物が被エツチング材料表面上
に再付着し、その結果エツチング後、材料表面上に残渣
が生じやすくなると同時に、高分子薄膜もエツチングさ
れることから量産装置では定期的に高分子薄膜を貼りか
える必要があるため、生産性が低下し、好ましくない。
When stainless steel forming a vacuum container is used as the electrode material, iron (Fe) and Ni (nickel) are released during etching, which causes heavy metal contamination of the element and significantly deteriorates it. Therefore, quartz (SiO 2 ) and alumina (Al 2 O 3 )
By covering the electrode with, it is possible to prevent heavy metal contamination,
Oxygen is released from SiO 2 and Al 2 O 3 . When the trace amount of oxygen is mixed in the system, a large amount of chlorine radicals are generated, and polycrystalline silicon and aluminum, especially phosphorus (P) and arsenic (A
Undercutting is likely to occur remarkably in polycrystalline silicon containing s). On the other hand, a polymer thin film such as polyester can remove the above-mentioned drawbacks, but during etching, the polymer from the polymer thin film redeposits on the material surface to be etched, and as a result, after etching, on the material surface. Since the polymer thin film is also etched at the same time as the residue is likely to be produced, it is necessary to periodically replace the polymer thin film in the mass production apparatus, which is not preferable because the productivity is lowered.

このため、重金属汚染が無い電極材料として、スパツタ
されにくい導伝性のカーボン(炭素:C)板が最適な材
料といえる。
Therefore, it can be said that a conductive carbon (carbon: C) plate that is not easily sputtered is the most suitable material as an electrode material that does not cause heavy metal contamination.

反応性イオンエツチング方法により被エツチング材料を
エツチングする場合、前述した様にアンダーカツトの
無い異方性エツチングを達成する。他の材料、例えば
レジストや多結晶シリコンでは下地材料である、SiO2
エツチング速度より高速度のエツチング、いわゆる選択
エツチングが要求され且つ、素子の汚染が無いことが
必要とされる。最近メモリー素子(例えば、ダイナミツ
クランダムアクセスメモリー(DRAM)が高集積度化し、
現在では256KDRAMから1MビツトDRAMが研究開発されつ
つあるが、このような素子では、最小寸法幅が2μm以
下となると同時に、ゲート酸化膜やメモリー部の酸化膜
厚は200Å以下となり、極めて薄くなる。この様な構造
の多結晶シリコンや高融点金属及びこのシリサイド化合
物を、反応性イオンエツチング方法によりエツチングす
ると、下地酸化膜の耐圧が著しく劣化し、絶縁膜として
機能しなくなる場合があるという大きな問題が新たに生
じてきた。
When the material to be etched is etched by the reactive ion etching method, anisotropic etching without undercutting is achieved as described above. Etching at a higher speed than that of SiO 2 which is a base material for other materials such as resist and polycrystalline silicon, that is, so-called selective etching, is required, and it is necessary that the element is not contaminated. Recently, memory devices (eg, dynamic random access memory (DRAM) have been highly integrated,
Currently, 1M bit DRAM is being researched and developed from 256K DRAM, but in such an element, the minimum dimension width becomes 2 μm or less, and at the same time, the oxide film thickness of the gate oxide film and the memory part becomes 200 Å or less, which is extremely thin. When the polycrystalline silicon or refractory metal having such a structure and the silicide compound are etched by the reactive ion etching method, the withstand voltage of the underlying oxide film is significantly deteriorated, which may cause a large problem that the insulating film may not function as an insulating film. It has newly occurred.

〔発明の目的〕[Object of the Invention]

本発明は上記事情に鑑みて為されたもので、電荷蓄積に
よる半導体基板上のシリコン酸化膜等の絶縁膜の絶縁破
壊を阻止する反応性イオンエツチング方法を提供するも
のである。
The present invention has been made in view of the above circumstances, and provides a reactive ion etching method for preventing dielectric breakdown of an insulating film such as a silicon oxide film on a semiconductor substrate due to charge accumulation.

〔発明の概要〕[Outline of Invention]

本発明によれば、材料配置側電極と被エツチング材料を
構成している半導体基板の間に絶縁物を置くことにより
上記目的を達成している。
According to the present invention, the above object is achieved by placing an insulator between the electrode on the material arrangement side and the semiconductor substrate constituting the material to be etched.

〔発明の実施例〕Example of Invention

以下本発明の実施例を図面を参照して詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図は使用したエツチング装置の概略構成を示してい
る。1はステンレス製の真空容器本体であつて、この容
器の一部をなすように平行平板電極を構成する上部電極
2と下部電極3が対向配置されている。これら電極2,
3はそれぞれテフロン・リング4,5により真空容器本
体1とは電気的に絶縁されている。試料6は下部電極3
の上に配置される。7,8はそれぞれ電極2,3を冷却
するための水冷管である。排気管9,10は例えば油拡散
ポンプとロータリポンプを有する排気系(図示せず)に
連結されている。11は分散管であつて、ガス導入口12か
ら導入された反応性ガスはこの分散管11より容器内に均
一性よく供給されるようになつている。13はRF電源で
あり、その出力は同軸スイツチ14により切換えられ、同
軸ケーブル15、整合器16を介して上記電極2に、または
同軸ケーブル17、整合器18を介して下部電極19に、選択
的に印加されるようになつている。また各電極2,3は
それぞれスイツチ19,20により、一方にRF電力が印加
されるとき他方が接地される。真空容器本体1は常に接
地されている。真空容器本体1の側部には石英製の監視
窓21が設けられ、その外側にガスプラズマの分光を行い
エツチングの進行状況を監視するための分光器,光電
管,記録計等を含むエツチング・モニタ22が設けられて
いる。23は圧力計である。
FIG. 1 shows a schematic structure of the etching device used. Reference numeral 1 denotes a stainless steel vacuum container body, in which an upper electrode 2 and a lower electrode 3 forming a parallel plate electrode are arranged so as to face each other so as to form a part of the container. These electrodes 2,
Reference numeral 3 is electrically insulated from the vacuum container body 1 by Teflon rings 4 and 5, respectively. Sample 6 is lower electrode 3
Placed on top of. Reference numerals 7 and 8 are water cooling tubes for cooling the electrodes 2 and 3, respectively. The exhaust pipes 9 and 10 are connected to an exhaust system (not shown) having, for example, an oil diffusion pump and a rotary pump. Reference numeral 11 denotes a dispersion pipe, and the reactive gas introduced from the gas introduction port 12 is supplied from the dispersion pipe 11 into the container with good uniformity. Reference numeral 13 is an RF power source, the output of which is switched by a coaxial switch 14 and selectively to the electrode 2 via the coaxial cable 15 and the matching device 16 or to the lower electrode 19 via the coaxial cable 17 and the matching device 18. Is being applied to. Further, the electrodes 2 and 3 are respectively connected by switches 19 and 20 so that when RF power is applied to one of them, the other is grounded. The vacuum container body 1 is always grounded. A quartz monitoring window 21 is provided on the side of the vacuum container main body 1, and an etching monitor including a spectroscope, a photoelectric tube, a recorder, etc. for monitoring the progress of etching by spectrally analyzing the gas plasma outside the quartz monitoring window 21. 22 are provided. 23 is a pressure gauge.

このような装置において、上部電極2、下部電極3にカ
ーボン板を用い、第2図に示すように試料6として半導
体基板である4インチ単結晶シリコンウエハ30を熱酸化
法により膜厚400Åの酸化膜を形成し、更にシラン(SiH
4)の熱分解(750℃)を用いる減圧気相成長法(LPCV
D)により多結晶シリコン(4000Å)32を堆積した後、1
000℃のリン(P)拡散したものを、ポジ型レジスト33
(OFPR−800:東京応化製)でマスク形成したものを用
いて、実験を行つた。エツチング条件は、反応性ガスと
して、Cl2を20cc/mimH2を6cc/mimの混合ガスを0.07T
owの圧力となるように導入し、印加するRF電力を13.5
6MHz、0.25w/cm2とした。又RF電力は下部電極3に印
加するようにした。
In such an apparatus, a carbon plate is used for the upper electrode 2 and the lower electrode 3, and as shown in FIG. 2, a 4-inch single crystal silicon wafer 30 which is a semiconductor substrate is oxidized as a sample 6 to a thickness of 400 Å by a thermal oxidation method. A film is formed, and silane (SiH
4 ) Low pressure vapor phase epitaxy (LPCV) using thermal decomposition (750 ℃)
1) after depositing polycrystalline silicon (4000Å) 32 by D)
Positive type resist 33 after phosphorus (P) diffusion at 000 ℃
An experiment was conducted using a mask formed of (OFPR-800: manufactured by Tokyo Ohka). The etching conditions are as follows: Cl 2 is 20cc / mim H 2 is 6cc / mim mixed gas 0.07T
RF power to be applied is set to 13.5
The frequency was 6 MHz and 0.25 w / cm 2 . RF power was applied to the lower electrode 3.

第3図は、前記多結晶シリコン32をフツ硝酸系の溶液に
よりエツチングした後レジスト33を同様に硫酸系の溶液
で除去した試料の熱酸化膜の耐圧を測定したものであ
る。多結晶シリコン32の電極面積は10mmで、1μAの電
流が流れた時を降伏電圧とした。第3図から明らかな様
に降伏電圧は10Mv/cmと6Mv/cmに分布している。10Mv
/cmは熱酸化膜固有の降伏電圧であり、6Mv/cmは、熱
酸化膜形成時におけるプロセス上の問題、例えばゴミ等
によるものである。
FIG. 3 shows the measured withstand voltage of the thermal oxide film of a sample obtained by etching the polycrystalline silicon 32 with a fluorine-nitric acid solution and then removing the resist 33 with a sulfuric acid solution. The electrode area of the polycrystalline silicon 32 was 10 mm, and the breakdown voltage was defined when a current of 1 μA flowed. As is clear from FIG. 3, the breakdown voltage is distributed at 10 Mv / cm and 6 Mv / cm. 10 Mv
/ Cm is a breakdown voltage peculiar to the thermal oxide film, and 6 Mv / cm is due to a process problem in forming the thermal oxide film, such as dust.

この様な耐圧分布を示す試料6を、前記エツチング条件
により反応性イオンエツチング方法で多結晶シリコン32
をエツチングしその後レジスト33を硫酸系の溶液で除去
したものの、熱酸化膜31の耐圧を測定したものが第4図
である。
The sample 6 having such a breakdown voltage distribution was formed by using the reactive ion etching method under the etching conditions described above.
FIG. 4 shows the result of measuring the withstand voltage of the thermal oxide film 31, although the etching was performed and the resist 33 was removed with a sulfuric acid-based solution.

単結晶シリコンウエーハ30上の熱酸化膜31の耐圧は著し
く劣化し、絶縁膜として機能しなくなつて健ることがわ
かる。
It can be seen that the breakdown voltage of the thermal oxide film 31 on the single crystal silicon wafer 30 is significantly deteriorated, and the thermal oxide film 31 does not function as an insulating film.

この様に従来公知のカーボン板電極3上に試料6を配置
して、エツチングすると、酸化膜31の耐圧は著しく劣化
することがわかるが、第5図に示したように試料6直下
のみにポリエステルフイルム40-2をカーボン板3上に貼
付したところ酸化膜31の耐圧特性は、第3図の溶液エッ
チングによる酸化膜の耐圧分布と全く変化のない良好な
特性が得られた。試料配置側電極がカーボン板等の導体
物質と、ポリエステルフイルム等の絶縁性物質で構成す
ると、試料の酸化膜がエツチングにより絶縁破壊されな
い理由は現在のところ明確ではないが以下の様に推論さ
れる。
As described above, when the sample 6 is arranged on the conventionally known carbon plate electrode 3 and etched, the withstand voltage of the oxide film 31 is remarkably deteriorated. However, as shown in FIG. When the film 40-2 was pasted on the carbon plate 3, the withstand voltage characteristics of the oxide film 31 showed good characteristics without any change from the withstand voltage distribution of the oxide film by the solution etching shown in FIG. It is not clear at present why the oxide film of the sample is not destroyed by etching if the sample placement side electrode is composed of a conductive material such as carbon plate and an insulating material such as polyester film, but it is inferred as follows. .

陰極降下電圧は、プラズマと試料及び電極間に形成され
るシースでほとんど発生し、酸化膜の膜厚が500Å以下
の極めて薄い時でも電極と結合しているブロッキングキ
ャパシタ等における絶縁性物質が10μm以上であれ
ば、陰極降下電圧Vdcが500Vとしても電荷蓄積による酸
化膜に印加される直流電圧は高々数Vであり、酸化膜を
絶縁破壊するまでの電圧とはならない。即ち、定常状態
における陰極降下電圧発生に伴なう電荷蓄積では、酸化
膜の耐圧は劣化せず、電極材料が導体物質のみでも良い
わけである。しかしながら導体物質の電極で試料の酸化
膜の耐圧が実際に劣化することから多結晶シリコンがエ
ツチングされた直後、定常状態に達するまでの極めて短
い時間(数mm秒以内)に導体物質に接触している半導体
基板はエツチング終了前と同電位であるが、多結晶シリ
コンの絶対値の電位が、半導体基板より低くなるため、
その電位差により酸化膜が絶縁破壊すると考えられる。
一方電極が導体物質と絶縁性物質で構成されると、半導
体基板と多結晶シリコンの各々の電位はエツチングされ
た直後でも、同程度の割合いで一定電位に達するために
絶縁破壊が起らないと考えられる。
The cathode drop voltage is mostly generated in the sheath formed between the plasma and the sample and the electrode, and even when the oxide film is extremely thin, less than 500Å, the insulating material in the blocking capacitor, etc. that is bonded to the electrode is 10 μm or more. Then, even if the cathode drop voltage Vdc is 500 V, the DC voltage applied to the oxide film due to charge accumulation is at most several V, and does not reach the voltage until dielectric breakdown of the oxide film. That is, the withstand voltage of the oxide film does not deteriorate in the charge accumulation accompanying the cathode drop voltage generation in the steady state, and the electrode material may be only the conductive material. However, since the withstand voltage of the oxide film of the sample actually deteriorates at the electrode of the conductor material, the conductor material is contacted with the conductor material within a very short time (within a few mm seconds) until the steady state is reached immediately after the etching. Although the semiconductor substrate has the same potential as before etching, the potential of the absolute value of polycrystalline silicon is lower than that of the semiconductor substrate.
It is considered that the potential difference causes dielectric breakdown of the oxide film.
On the other hand, if the electrode is composed of a conductive material and an insulating material, the electric potentials of the semiconductor substrate and the polycrystalline silicon will reach a constant electric potential at the same rate even immediately after etching, so that dielectric breakdown does not occur. Conceivable.

上記一実施例は試料6配置側電極3に高周波電力を印加
したものであるが、400KHzの低高周波電力の場合は上部
電極2に高周波電力を印加してもアンダーカツトの無い
異方性エツチングが達成できる。この場合13.56MHzの様
な高周波電力と異なり、負の自己バイアスは発生しない
が、プラズマ中の正イオンエネルギーが高くなり、接地
電位の下部電極3に試料6を配置してエツチングする
と、下部電極が導体物質であると酸化膜の絶縁破壊がお
こり、試料6配置電極3を、導体物質と絶縁物質で構成
すると、13.56MHzの様な高周波電力と同様、耐圧劣化は
全く生じなかつた。
In the above-mentioned one embodiment, high frequency power is applied to the electrode 3 on the side where the sample 6 is placed. However, in the case of low high frequency power of 400 KHz, even if high frequency power is applied to the upper electrode 2, anisotropic etching without undercutting occurs. Can be achieved. In this case, unlike high-frequency power such as 13.56 MHz, negative self-bias does not occur, but the positive ion energy in the plasma increases, and when the sample 6 is placed on the lower electrode 3 at the ground potential for etching, the lower electrode is Dielectric breakdown of the oxide film occurs when it is a conductor material, and when the sample 6 placement electrode 3 is composed of a conductor material and an insulation material, no breakdown voltage occurs at all, similar to high frequency power such as 13.56 MHz.

又試料の熱酸化膜の代りに、シリコンを直接熱窒化した
膜でも同様な結果が得られ、更には多結晶シリコンの代
りにAlやタングステン(W)、モリブデン(Mo)等の高融
点金属及びそれらのシリサイド化合物をエツチングする
場合でも効果は全く同じであつた。
Similar results were obtained with a film obtained by directly thermally nitriding silicon instead of the thermal oxide film of the sample. Furthermore, instead of polycrystalline silicon, high melting point metals such as Al, tungsten (W), molybdenum (Mo), and The effect was exactly the same when etching those silicide compounds.

〔発明の効果〕〔The invention's effect〕

以上説明したように、この発明によれば、試料を配置し
た電極が導体物質と絶縁物質で構成され、前記絶縁物質
の単位当りの容量か、試料の単結晶シリコンと導電性被
エツチング材料間の絶縁膜の容量の20倍以上であればエ
ツチングにより前記試料中の絶縁膜の絶縁破壊が発生し
ない。極めて高い信頼性のLSI製造プロセスが確立さ
れる。
As described above, according to the present invention, the electrode on which the sample is arranged is composed of the conductive material and the insulating material, and the capacitance per unit of the insulating material, or the single crystal silicon of the sample and the conductive material to be etched. If the capacity of the insulating film is 20 times or more, the dielectric breakdown of the insulating film in the sample will not occur due to etching. An extremely high reliability LSI manufacturing process is established.

【図面の簡単な説明】[Brief description of drawings]

第1図は、本発明を説明するための使用装置の概略図、
第2図は被エツチング物の構成図、第3図は被エツチン
グ物の導体層を溶液によりエツチングした時のシリコン
絶縁膜の耐圧分布図、第4図は、試料配置側の電極がカ
ーボン板等の導体物質であるときの、被エツチング物の
シリコン絶縁膜の耐圧分布図、第5図は、本発明の一実
施例を示す説明図である。 1…ステンレス製の真空容器、2…上部電極、 3…下部電極、4,5…テフロン、 6…被エツチング物、7,8…水冷パイプ、 9,10…排気管、13…高周波電源、 16,18…整合回路、 30…単結晶シリコンウエーハ、 31…シリコン絶縁膜、32…導体物質層、 33…フオトレジスト、 40-2…絶縁性高分子薄膜、 41-2…導体物質層。
FIG. 1 is a schematic view of a device used for explaining the present invention,
FIG. 2 is a configuration diagram of an object to be etched, FIG. 3 is a withstand voltage distribution diagram of a silicon insulating film when a conductor layer of the object to be etched is etched by a solution, and FIG. FIG. 5 is a diagram showing a withstand voltage distribution of the silicon insulating film of the object to be etched when the conductor material of FIG. 1 ... Stainless steel vacuum container, 2 ... Upper electrode, 3 ... Lower electrode, 4,5 ... Teflon, 6 ... Etching object, 7,8 ... Water cooling pipe, 9, 10 ... Exhaust pipe, 13 ... High frequency power supply, 16 , 18 ... Matching circuit, 30 ... Single crystal silicon wafer, 31 ... Silicon insulating film, 32 ... Conductor material layer, 33 ... Photoresist, 40-2 ... Insulating polymer thin film, 41-2 ... Conductor material layer.

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】互いに対向配置された平行平板型電極を有
するプラズマエッチング装置において、シリコン単結晶
からなる第1層とこの第1層上に形成されたシリコン絶
縁膜からなる第2層との積層物質上に形成された導電性
物質層とこの導電性物質層上にパターン形成されたエッ
チングマスクとを備えた被エッチング物を前記平行平板
型電極の一方に設置してエッチングするに際し、プラズ
マに晒される前記被エッチング物を設置する側の電極上
面において、前記被エッチング物と前記電極との間に絶
縁物質層を設け、前記被エッチング物の設置箇所周囲の
プラズマに晒される前記電極上面は電極の導電性物質で
あることを特徴とするプラズマエッチング方法。
1. A plasma etching apparatus having parallel plate electrodes arranged opposite to each other, wherein a first layer made of a silicon single crystal and a second layer made of a silicon insulating film formed on the first layer are laminated. When an object to be etched having a conductive material layer formed on a material and an etching mask patterned on the conductive material layer is placed on one of the parallel plate electrodes and etched, the material is exposed to plasma. The insulating material layer is provided between the object to be etched and the electrode on the side of the electrode on which the object to be etched is installed, and the upper surface of the electrode exposed to plasma around the installation location of the object to be etched is the electrode. A plasma etching method characterized by being a conductive substance.
【請求項2】前記電極上に導体物質層を設け、前記絶縁
物質層をこの導体物質層を介して前記電極上に構成して
なることを特徴とする特許請求の範囲第1項記載のプラ
ズマエッチング方法。
2. The plasma according to claim 1, wherein a conductive material layer is provided on the electrode, and the insulating material layer is formed on the electrode via the conductive material layer. Etching method.
【請求項3】前記導体物質層が炭素であることを特徴と
する特許請求の範囲第2項記載のプラズマエッチング方
法。
3. The plasma etching method according to claim 2, wherein the conductive material layer is carbon.
【請求項4】前記絶縁物質層が、弗素系,炭化弗素系,
塩素炭化水素系,あるいはシリコン系の絶縁性高分子で
あることを特徴とする特許請求の範囲第1項乃至第3項
記載のプラズマエッチング方法。
4. The insulating material layer is fluorine-based, fluorine carbide-based,
The plasma etching method according to any one of claims 1 to 3, wherein the plasma etching method is a chlorine hydrocarbon-based or silicon-based insulating polymer.
【請求項5】前記被エッチング物の第2層のシリコン絶
縁膜が熱酸化膜及び熱窒化膜であることを特徴とする特
許請求の範囲第1項記載のプラズマエッチング方法。
5. The plasma etching method according to claim 1, wherein the second-layer silicon insulating film of the object to be etched is a thermal oxide film or a thermal nitride film.
【請求項6】前記被エッチング物の導電性物質層が、多
結晶シリコン,非晶質シリコン,タングステン,モリブ
テン等の高融点金属,及び該高融点金属のシリサイド化
合物,更には多結晶シリコンと前記高融点金属又はこの
シリサイド化合物との積層物であることを特徴とする特
許請求の範囲第1項記載のプラズマエッチング方法。
6. A conductive material layer of the object to be etched is a refractory metal such as polycrystalline silicon, amorphous silicon, tungsten or molybdenum, a silicide compound of the refractory metal, and further polycrystalline silicon and the above. The plasma etching method according to claim 1, wherein the plasma etching method is a laminate with a refractory metal or a silicide compound thereof.
【請求項7】前記被エッチング物の第2層のシリコン絶
縁膜の単位面積キャパシタ容量が前記電極の絶縁物質層
の単位面積キャパシタ容量の20倍以上であることを特徴
とする特許請求の範囲第1項記載のプラズマエッチング
方法。
7. The unit area capacitor capacitance of the second-layer silicon insulating film of the object to be etched is 20 times or more the unit area capacitor capacitance of the insulating material layer of the electrode. The plasma etching method according to item 1.
JP57191910A 1982-11-02 1982-11-02 Plasma etching method Expired - Lifetime JPH0642467B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57191910A JPH0642467B2 (en) 1982-11-02 1982-11-02 Plasma etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57191910A JPH0642467B2 (en) 1982-11-02 1982-11-02 Plasma etching method

Publications (2)

Publication Number Publication Date
JPS5982729A JPS5982729A (en) 1984-05-12
JPH0642467B2 true JPH0642467B2 (en) 1994-06-01

Family

ID=16282477

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57191910A Expired - Lifetime JPH0642467B2 (en) 1982-11-02 1982-11-02 Plasma etching method

Country Status (1)

Country Link
JP (1) JPH0642467B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63133633A (en) * 1986-11-26 1988-06-06 Matsushita Electronics Corp Manufacture of semiconductor device
JPS63133632A (en) * 1986-11-26 1988-06-06 Matsushita Electronics Corp Dry-etching system
JPH0831442B2 (en) * 1987-03-11 1996-03-27 株式会社日立製作所 Plasma processing method and apparatus

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56134738A (en) * 1980-03-26 1981-10-21 Toshiba Corp Method of forming pattern

Also Published As

Publication number Publication date
JPS5982729A (en) 1984-05-12

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