JPH0464231A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0464231A JPH0464231A JP17901390A JP17901390A JPH0464231A JP H0464231 A JPH0464231 A JP H0464231A JP 17901390 A JP17901390 A JP 17901390A JP 17901390 A JP17901390 A JP 17901390A JP H0464231 A JPH0464231 A JP H0464231A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon substrate
- barrier layer
- insulating layer
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 47
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 42
- 239000010703 silicon Substances 0.000 claims abstract description 42
- 230000004888 barrier function Effects 0.000 claims abstract description 32
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 25
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 25
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 238000004544 sputter deposition Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 5
- 239000012808 vapor phase Substances 0.000 claims description 2
- 238000001947 vapour-phase growth Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 113
- 239000010936 titanium Substances 0.000 abstract description 27
- 239000011229 interlayer Substances 0.000 abstract description 20
- 238000009792 diffusion process Methods 0.000 abstract description 11
- 239000012535 impurity Substances 0.000 abstract description 9
- 229910052719 titanium Inorganic materials 0.000 abstract description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 6
- 239000010949 copper Substances 0.000 abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 2
- 238000005275 alloying Methods 0.000 abstract description 2
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 230000005012 migration Effects 0.000 description 3
- 238000013508 migration Methods 0.000 description 3
- 239000006104 solid solution Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910001069 Ti alloy Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 2
- 235000007575 Calluna vulgaris Nutrition 0.000 description 1
- 244000201986 Cassia tora Species 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- NCAIGTHBQTXTLR-UHFFFAOYSA-N phentermine hydrochloride Chemical compound [Cl-].CC(C)([NH3+])CC1=CC=CC=C1 NCAIGTHBQTXTLR-UHFFFAOYSA-N 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要〕
シリコン基板に接続されたアルミニウム配線を有する半
導体装置、とくに シリコン基板とアルミニウム配線と
の固溶による接触抵抗の増大や浅い拡散領域の破壊を防
止するためのバリヤ層に関し
該バリヤ層の剥離に起因する絶縁不良等の発生を防止す
ることを目的とし
シリコン基板の一表面に画定された接続領域を表出する
開口を有する絶縁層を形成し、該開口内に表出する該シ
リコン基板表面に選択的にコンタクトメタル層を成長す
る工程と、バリヤ層を構成する原子が該絶縁層表面にお
いてマイグレーション可能な温度において該基板表面全
体に該バリヤ層を気相成長させ、該バリヤ層上にアルミ
ニウムを主成分とする導電層を堆積する諸工程を含むよ
うに構成する。[Detailed Description of the Invention] [Summary] A semiconductor device having aluminum wiring connected to a silicon substrate, particularly for preventing an increase in contact resistance and destruction of a shallow diffusion region due to solid solution between the silicon substrate and the aluminum wiring. In order to prevent insulation defects caused by peeling of the barrier layer with respect to the barrier layer, an insulating layer having an opening exposing a connection area defined on one surface of the silicon substrate is formed, and the inside of the opening is a step of selectively growing a contact metal layer on the surface of the silicon substrate, which is exposed to the surface of the silicon substrate; and a step of vapor phase growth of the barrier layer over the entire surface of the substrate at a temperature that allows atoms constituting the barrier layer to migrate on the surface of the insulating layer. and depositing an aluminum-based conductive layer on the barrier layer.
本発明は、シリコン基板に接続されたアルミニウム配線
を有する半導体装置に関する。The present invention relates to a semiconductor device having aluminum wiring connected to a silicon substrate.
［従来の技術］
アルミニウムは、半導体装置における主要配線材料であ
るが、一方で、シリコンと容易に固溶するため シリコ
ン基板からアルミニウム配線層にシリコン原子が拡散し
、シリコン基板に形成されている不純物拡散領域が破壊
されたり、シリコンの固溶によってアルミニウム配線層
の抵抗が増大したりする。この問題は、半導体装置の高
速化や高集積化にともなって不純物拡散領域が浅くなり
。[Prior art] Aluminum is the main wiring material in semiconductor devices, but on the other hand, because it easily forms a solid solution with silicon, silicon atoms diffuse from the silicon substrate into the aluminum wiring layer, causing impurities formed in the silicon substrate. The diffusion region may be destroyed, or the resistance of the aluminum wiring layer may increase due to solid solution of silicon. This problem arises as impurity diffusion regions become shallower as semiconductor devices become faster and more highly integrated.
かつ アルミニウムとの接触面積が縮小されるにつれて
より顕著に現れる。したがって、シリコン基板やシリコ
ン層にアルミニウム配線を接続する場合には、一般に、
これらの接触界面に、相互拡散を阻止するためのバリヤ
層を介在させることが行われている。and becomes more pronounced as the contact area with aluminum is reduced. Therefore, when connecting aluminum wiring to a silicon substrate or silicon layer, generally
A barrier layer is interposed at these contact interfaces to prevent mutual diffusion.
（発明が解決しようとする課題］
上記バリヤ層を含め、シリコン基板とアルミニウム配線
との接触部の構造や構成材料については種々提案されて
いる。その代表的なものとしてシリコン基板表面に５例
えばタングステン（讐）から成るコンタクトメタル層を
形成し１ この上にチタン（Ｔｉ）またはチタン−タン
グステン（Ｔｉ−Ｗ）合金から成るバリヤ層を形成し、
このバリヤ層上にアルミニウム配線層を形成する三層構
造がある。(Problems to be Solved by the Invention) Various proposals have been made regarding the structure and constituent materials of the contact portion between the silicon substrate and the aluminum wiring, including the barrier layer described above.A typical example is the use of tungsten, for example, on the surface of the silicon substrate. 1 form a contact metal layer made of titanium (Ti) or a titanium-tungsten (Ti-W) alloy;
There is a three-layer structure in which an aluminum wiring layer is formed on this barrier layer.
すなわち、第３図に示すように、不純物拡散領域２が形
成されているシリコン基板１上には、不純物拡散領域２
を表出する開口を有する層間絶縁層３が形成されている
。この開口内には、シリコン基板表面とＳｉＯ□等の層
間絶縁層３表面との選択成長性を利用して、タングステ
ン（−）から成るコンタクトメタル層４が形成されてい
る。そして。That is, as shown in FIG. 3, on the silicon substrate 1 on which the impurity diffusion region 2 is formed,
An interlayer insulating layer 3 is formed having an opening exposing the . In this opening, a contact metal layer 4 made of tungsten (-) is formed by utilizing selective growth between the surface of the silicon substrate and the surface of the interlayer insulating layer 3 such as SiO□. and.
層間絶縁層３上にはＴｉ−合金から成るバリヤ層５とア
ルミニウム配線層６が形成されている。このようにして
不純物拡散領域２に接続されるアルミニウム配線層６は
５例えばアルミニウムー銅（ＡＩＣｕ）合金から成り、
バリヤ層５とともにパターンニングされている。A barrier layer 5 made of Ti-alloy and an aluminum wiring layer 6 are formed on the interlayer insulating layer 3. The aluminum wiring layer 6 connected to the impurity diffusion region 2 in this way is made of, for example, an aluminum-copper (AICu) alloy,
It is patterned together with the barrier layer 5.
ところが、 Ｔｉ−Ｗから成るバリヤ層５は、 ５ｉＯ
ｚから成る層間絶縁層３との密着力が低く、また、大き
な内部応力が発生しやすいために、成膜中に剥離しやす
い。その結果１層間絶縁層３から剥離したバリヤ層５が
汚染物質となって１種々のモードの絶縁不良を生しる原
因となる。However, the barrier layer 5 made of Ti-W is 5iO
Since the adhesion with the interlayer insulating layer 3 made of z is low and large internal stress is likely to occur, it is easy to peel off during film formation. As a result, the barrier layer 5 peeled off from the interlayer insulating layer 3 becomes a contaminant, causing various modes of insulation failure.
また、第３図に示すように、アルミニウム配線層６の上
表面には１層間絶縁層３の前記開口に対応する段差が生
じていた。これは、前記開口に層間絶縁層３の段差が存
在するだけでなく、この開口のアスペクト比（高さ７幅
比）が大きくなるにつれ、この開口内におけるバリヤ層
５やアルミニウム配線層６のカバレンジが充分でなくな
るためである。半導体装置が微細化し、かつ、多層構造
化するにつれ１表面の段差すなわち凹凸が好ましくない
影響を生しることは周知の通りである。Further, as shown in FIG. 3, a step was formed on the upper surface of the aluminum wiring layer 6, corresponding to the opening in the first interlayer insulating layer 3. This is because not only does the step of the interlayer insulating layer 3 exist in the opening, but also the coverage range of the barrier layer 5 and the aluminum wiring layer 6 within this opening increases as the aspect ratio (height to width ratio) of this opening increases. This is because the amount is not sufficient. It is well known that as semiconductor devices become smaller and have a multi-layered structure, steps or irregularities on one surface cause undesirable effects.
本発明は、上記のような剥離を生じることなく。The present invention does not cause peeling as described above.
Ｔｉ−一から成るバリヤ層を形成可能とし、同時に段差
のない平滑な上表面を有するアルミニウム配線層を形成
可能とすることを目的とする。It is an object of the present invention to make it possible to form a barrier layer made of Ti-1, and at the same time to make it possible to form an aluminum wiring layer having a smooth upper surface with no steps.
［課題を解決するための手段〕
上記目的は、シリコン基板の一表面に画定された接続領
域を表出する開口を有する絶縁層を形成する工程と、該
開口内に表出する該シリコン基板表面に選択的にコンタ
クトメタル層を成長する工程と、バリヤ層を構成する原
子が該絶縁層表面においてマイグレーション可能な温度
において該基板表面全体に該バリヤ層を気相成長させる
工程と該バリヤ層上にアルミニウムを主成分とする導電
層を堆積する工程とを含むことを特徴とする本発明に係
る半導体装置の製造方法によって達成される。[Means for Solving the Problem] The above object includes a step of forming an insulating layer having an opening exposing a connection region defined on one surface of a silicon substrate, and a step of forming an insulating layer having an opening exposing a connection region defined on one surface of a silicon substrate, selectively growing a contact metal layer on the surface of the insulating layer; growing the barrier layer in a vapor phase over the entire surface of the substrate at a temperature that allows atoms constituting the barrier layer to migrate on the surface of the insulating layer; This is achieved by the method for manufacturing a semiconductor device according to the present invention, which includes the step of depositing a conductive layer containing aluminum as a main component.
〔作 用］
コンタクトホール内に表出するシリコン基板表面に、コ
ンタクトメタル層として１例えばタングステン（−）を
選択成長させたのち、該シリコン基板を８００°Ｃ程度
に加熱した状態で、基板表面に。[Function] After selectively growing a contact metal layer, such as tungsten (-), on the surface of the silicon substrate exposed in the contact hole, the silicon substrate is heated to about 800°C, and then the silicon substrate is heated to about 800°C. .
例えばチタン（Ｔｉ）をスパッタリング法により堆積す
る。その結果９次のような利点が生じる。For example, titanium (Ti) is deposited by sputtering. As a result, the following advantages arise.
■上記のような高温では、Ｔｉ原子の活性が太き（、Ｓ
ｉＯ□から成る層間絶縁層表面に対する密着力が増大す
るため、Ｔｉ層は剥離しない。■At high temperatures such as those mentioned above, the activity of Ti atoms increases (, S
Since the adhesion to the surface of the interlayer insulating layer made of iO□ increases, the Ti layer does not peel off.
■ＳｉＯ□等の層間絶縁層３表面におけるＴｉ原子のマ
イグレーションが容易となるため、コンタクトホールは
Ｔｉ層によってほぼ埋め込まれてしまう。(2) Since migration of Ti atoms on the surface of the interlayer insulating layer 3 such as SiO□ becomes easy, the contact hole is almost filled with the Ti layer.
■上記Ｔｉ層とにコンタクトメタル層との界面には、
Ｔｉ−合金層が生成する。このＴｉ−層がバリヤ層とし
て機能する。■At the interface between the Ti layer and the contact metal layer,
A Ti-alloy layer forms. This Ti-layer functions as a barrier layer.
■上記のようにしてコンタクトホールがＴｉ層によって
埋め込まれることにより平坦化されたシリコン基板表面
に形成されるアルミニウム配線層の上表面には段差が生
じない。(2) Since the contact hole is filled with the Ti layer as described above, no step is formed on the upper surface of the aluminum wiring layer formed on the planarized silicon substrate surface.
以下本発明の実施例を図面を参照して説明する。 Embodiments of the present invention will be described below with reference to the drawings.
以下の図面において２既掲の図面におけるのと同じ部分
には同一符号を付しである。In the following drawings, the same parts as in the two previous drawings are designated by the same reference numerals.
第１図は本発明の実施例の工程説明図であって同図（ａ
）に示すように、不純物拡散領域２が形成されているシ
リコン基板１表面に１例えば５ｉＯｚから成る厚さ約１
μ翔の層間絶縁層３を堆積し５周知のリソグラフ技術を
用いて、不純物拡散領域２を表出する開口３１を層間絶
縁層３に形成する。FIG. 1 is a process explanatory diagram of an embodiment of the present invention.
), on the surface of the silicon substrate 1 where the impurity diffusion region 2 is formed, a layer of about 1 oz.
A microscopic interlayer insulating layer 3 is deposited, and an opening 31 exposing the impurity diffusion region 2 is formed in the interlayer insulating layer 3 using a well-known lithography technique.
次いで１同図（ｂ）に示すように、開口３１内に表出す
るシリコン基板１表面に、−から成る厚さ１００〜２０
０人のコンタクトメタル層４を選択的に形成する。この
形成は、 ｈｐ ｂ （６弗化タングステン）ガスを用
いる周知のＣＶＤ法により行う。−層は、シリコン基板
１表面には成長するが、ＳｉＯ□等から成る層間絶縁層
３表面には成長しない。−コンタクトメタル層４は、シ
リコン基板１と後述する配線層８との接触抵抗を下げる
ために設けられ１バリヤ層としては機能しない。Next, as shown in FIG. 1(b), the surface of the silicon substrate 1 exposed in the opening 31 is coated with a thickness of 100 to 20 mm.
0 contact metal layers 4 are selectively formed. This formation is performed by a well-known CVD method using HP b (tungsten hexafluoride) gas. - layer grows on the surface of the silicon substrate 1, but does not grow on the surface of the interlayer insulating layer 3 made of SiO□ or the like. - The contact metal layer 4 is provided to reduce the contact resistance between the silicon substrate 1 and the wiring layer 8 described later, and does not function as a barrier layer.
次いで１ シリコン基板１をスパッタリング装置内に装
着し１例えば背面から赤外線照射して８００°Ｃに加熱
する。この状態で、Ｔｉターゲットをスパッタリングし
て、同図（Ｃ）に示すように、厚さ１０００人程度Ｏ７
４層８をシリコン基板１表面に堆積する。Next, 1. The silicon substrate 1 is placed in a sputtering apparatus, and the silicon substrate 1 is heated to 800° C., for example, by irradiating it with infrared rays from the back side. In this state, a Ti target is sputtered to a thickness of about 1000 O7 as shown in the same figure (C).
Four layers 8 are deposited on the surface of the silicon substrate 1.
前記開口３１内は７４層８によってほぼ埋め込まれ。The inside of the opening 31 is almost filled with 74 layers 8.
７４層８の上表面はほぼ平坦になる。上記温度において
は、−から成るコンタクトメタル層４と７４層８との界
面において合金化反応が生し、 Ｔｉ−勤）ら成るバリ
ヤ層５が一生成する。すなわち、７４層８のみではバリ
ヤ層として機能しないので、上記反応によるＴｉ−バリ
ヤ層５が必要なのである。７４層８はＳｉＯ□から成る
層間絶縁層３に対する密着力が大きく、従来のように、
Ｔｉ−から成るバリヤ層５が層間絶縁層３に堆積され
る場合のような剥離を生じない。The upper surface of the 74 layer 8 becomes substantially flat. At the above temperature, an alloying reaction occurs at the interface between the contact metal layer 4 and the 74 layer 8, forming a barrier layer 5 made of Ti. That is, since the 74 layer 8 alone does not function as a barrier layer, the Ti-barrier layer 5 formed by the above reaction is necessary. The 74 layer 8 has a strong adhesion to the interlayer insulating layer 3 made of SiO□, and as in the conventional case,
There is no delamination as would be the case if the barrier layer 5 of Ti- was deposited on the interlayer insulating layer 3.
次いで、同図（ｄ）に示すように、シリコン基板１表面
ニ、銅（Ｃｕ）を含有するアルミニウム配線層６を堆積
する。下地のＴｉ層８表面が平坦化されているので、上
表面が平坦なアルミニウム配線層６が形成される。Next, as shown in FIG. 2D, an aluminum wiring layer 6 containing copper (Cu) is deposited on the surface of the silicon substrate 1. Since the surface of the underlying Ti layer 8 is planarized, an aluminum wiring layer 6 with a flat upper surface is formed.
上記Ｔｉ層８の形成において、第２図に示すようなバイ
アススパッタリング法が好適である。すなわち、チタン
ターゲット１１が装着される電極に。In forming the Ti layer 8, a bias sputtering method as shown in FIG. 2 is suitable. That is, on the electrode to which the titanium target 11 is attached.
約６００ｖの直流負電圧（−ＤＣ）を印加し、シリコン
基板１が載置される電極に高周波バイアス電圧（ＲＦ）
を印加してスパッタリングを行う。この高周波／’ｔイ
アス電圧により、シリコン基板１表面の弱いスパッタリ
ングとＴｉの堆積とが交互に生じるため清浄な表面にＴ
ｉが成長することになり、前記層間絶縁層３表面に対す
る７４層８の密着力が増大する。A negative direct current voltage (-DC) of about 600v is applied, and a high frequency bias voltage (RF) is applied to the electrode on which the silicon substrate 1 is placed.
is applied to perform sputtering. Due to this high frequency/'t ia voltage, weak sputtering on the surface of the silicon substrate 1 and deposition of Ti occur alternately, so that the T is deposited on the clean surface.
i will grow, and the adhesion of the 74 layer 8 to the surface of the interlayer insulating layer 3 will increase.
また、この高周波バイアス電圧の損失により、シリコン
基板１の加熱が増強され８層間絶縁層３に対するＴｉ層
の密着力の向上ならびにＴｉ原子のマイグレーションが
促進される効果がある。Moreover, this loss of high frequency bias voltage has the effect of increasing the heating of the silicon substrate 1, improving the adhesion of the Ti layer to the eight interlayer insulating layer 3, and promoting the migration of Ti atoms.
従来のＴｉ−Ｗから成るバリヤ層５の形成は、 ＤＣス
パッタリング法によって行われ１ シリコン基板１の加
熱も行っていなかった。したがって、比較的低温の状態
の基板表面にＴｉまたはＴｉ−Ｗから成るバリヤ層５が
堆積されるため１層間絶縁層３表面対するバリヤ層５の
密着力が低く、また、 Ｔｉ原子等のマイグレーション
が小さいために本発明におけるような、開口３１がバリ
ヤ層５によって埋め込まれる効果も生じなかった。The conventional barrier layer 5 made of Ti--W was formed by a DC sputtering method, and the silicon substrate 1 was not heated. Therefore, since the barrier layer 5 made of Ti or Ti-W is deposited on the surface of the substrate at a relatively low temperature, the adhesion of the barrier layer 5 to the surface of the interlayer insulating layer 3 is low, and the migration of Ti atoms etc. is low. Since the opening 31 was small, the effect of burying the opening 31 with the barrier layer 5 as in the present invention did not occur.
〔発明の効果］
本発明によれば、シリコン基板に接続されるアルミニウ
ム配線層を有する半導体装置の製造において１バリヤ層
が層間絶縁層表面から剥離するこに起因する絶縁不良を
低減し１また。コンタクトホール内を導電層により埋め
込まれるためにカバレンジ不良に起因する断線や不純物
拡散領域の破壊が回避可能となり、この種の半導体装置
の製造歩留りを向上する効果がある。さらに、上表面が
平坦なアルミニウム配線層を形成できるため、高性能・
高集積度の半導体装置に必要なパターンの微細化を容易
にする効果がある。[Effects of the Invention] According to the present invention, insulation defects caused by peeling of a barrier layer from the surface of an interlayer insulating layer can be reduced in manufacturing a semiconductor device having an aluminum wiring layer connected to a silicon substrate. Since the contact hole is filled with the conductive layer, it is possible to avoid wire breakage and destruction of the impurity diffusion region due to poor coverage, and this has the effect of improving the manufacturing yield of this type of semiconductor device. Furthermore, since it is possible to form an aluminum wiring layer with a flat top surface, high performance and
This has the effect of facilitating the miniaturization of patterns required for highly integrated semiconductor devices.
図において。In fig.
１はシリコン基板、 ２は不純物拡散領域。1 is a silicon substrate, 2 is an impurity diffusion region.
３は眉間絶縁層、 ４はコンタクトメタル層。3 is an insulating layer between the eyebrows, and 4 is a contact metal layer.
５はバリヤ層、 ６はアルミニウム配線層。5 is a barrier layer, and 6 is an aluminum wiring layer.
８はＴｉ層、１１はチタンターゲット ３１は開口 である。8 is a Ti layer, 11 is a titanium target 31 is the opening It is.
第１図は本発明の実施例の工程説明図。
第２図は本発明の実施に好適なスパッタリング方法の説
明図
第３図は従来の問題点説明図
である。
杢、今と日月の実り化１詰子逼ｔｊスパ・・７リング杉
式り説期仕口冨 ２ 濠
均ヌ９８月／′）寅胸！イク）１／）ニオＹ家チθ月し
］惰 １ 図
鴫すど゛未メフＭ片に苫１−８月月］
誦 ３ ロFIG. 1 is a process explanatory diagram of an embodiment of the present invention. FIG. 2 is an explanatory diagram of a sputtering method suitable for carrying out the present invention. FIG. 3 is an explanatory diagram of problems in the conventional method. Heather, the fruition of the sun and the moon 1 Tsumeko tj spa... 7 rings Sugishikiri theory period Shiguchi Tomi 2 Hitoshi Hori 98th/') Tora chest! Iku) 1/) Nio Y family Ji θ Month] Inasu 1 Figure Sud゛ Mefu M Piece 1-August Month] Recitation 3
Claims (2)
出する開口を有する絶縁層を形成する工程と、該開口内
に表出する該シリコン基板表面に選択的にコンタクトメ
タル層を成長する工程と、バリヤ層を構成する原子が該
絶縁層表面においてマイグレーション可能な温度におい
て該基板表面全体に該バリヤ層を気相成長させる工程と
、該バリヤ層上にアルミニウムを主成分とする導電層を
堆積する工程 とを含むことを特徴とする半導体装置の製造方法。(1) Forming an insulating layer having an opening exposing a connection region defined on one surface of a silicon substrate, and selectively growing a contact metal layer on the surface of the silicon substrate exposed within the opening. a step of growing the barrier layer in a vapor phase over the entire surface of the substrate at a temperature that allows atoms constituting the barrier layer to migrate on the surface of the insulating layer; and forming a conductive layer containing aluminum as a main component on the barrier layer. 1. A method for manufacturing a semiconductor device, comprising the step of depositing.
る直流スパッタリング法によって行うことを特徴とする
請求項１記載の半導体装置の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the vapor phase growth of the barrier layer is performed by a DC sputtering method applying a high frequency bias.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17901390A JP2969830B2 (en) | 1990-07-04 | 1990-07-04 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17901390A JP2969830B2 (en) | 1990-07-04 | 1990-07-04 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0464231A true JPH0464231A (en) | 1992-02-28 |
| JP2969830B2 JP2969830B2 (en) | 1999-11-02 |
Family
ID=16058594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17901390A Expired - Fee Related JP2969830B2 (en) | 1990-07-04 | 1990-07-04 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2969830B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100338114B1 (en) * | 1995-12-18 | 2002-11-02 | 주식회사 하이닉스반도체 | Method for forming metal film in semiconductor device |
| FR2861813A1 (en) * | 2003-11-04 | 2005-05-06 | Renault Sas | Internal combustion engine, has injector fixed to support and injecting fuel, and radial lateral pipe and radial lateral orifice introducing oil into chambers to displace injector with respect to cylinder in two opposite directions |
-
1990
- 1990-07-04 JP JP17901390A patent/JP2969830B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100338114B1 (en) * | 1995-12-18 | 2002-11-02 | 주식회사 하이닉스반도체 | Method for forming metal film in semiconductor device |
| FR2861813A1 (en) * | 2003-11-04 | 2005-05-06 | Renault Sas | Internal combustion engine, has injector fixed to support and injecting fuel, and radial lateral pipe and radial lateral orifice introducing oil into chambers to displace injector with respect to cylinder in two opposite directions |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2969830B2 (en) | 1999-11-02 |
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