JPH0462U - - Google Patents
Info
- Publication number
- JPH0462U JPH0462U JP4045190U JP4045190U JPH0462U JP H0462 U JPH0462 U JP H0462U JP 4045190 U JP4045190 U JP 4045190U JP 4045190 U JP4045190 U JP 4045190U JP H0462 U JPH0462 U JP H0462U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- output
- binary
- processing circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 7
Description
第１図は本考案の原理構成を示す図、第２図は
本考案の実施例として第１図中の逐次処理回路の
構成を示す図、第３図は第２図の動作波形図、第
４図は従来の装置の構成を示す図、第５図は第４
図の動作波形図、第６図・第７図は第４図におけ
る異なる動作を示す図である。
１……アナログ信号入力端子、６……デコーダ
回路、８−１，８−２……複数の二値化回路、９
……逐次処理回路。
FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a diagram showing the configuration of the sequential processing circuit in FIG. 1 as an embodiment of the present invention, and FIG. 3 is an operational waveform diagram of FIG. Figure 4 is a diagram showing the configuration of a conventional device, and Figure 5 is a diagram showing the configuration of a conventional device.
The operation waveform diagrams in FIG. 6 and FIG. 7 are diagrams showing different operations in FIG. 4. 1...Analog signal input terminal, 6...Decoder circuit, 8-1, 8-2...Plural binarization circuits, 9
...Sequential processing circuit.
Claims (1)
号の印加される端子と、 該印加端子に並列接続され、二値化動作特性が
互いに異なる二値化回路と、 各二値化回路の出力が印加され、それを逐次信
号に変換する逐次処理回路と、 該逐次処理回路の出力をデコードするデコーダ
回路とで構成すること を特徴とする二値化信号読取装置。[Claims for Utility Model Registration] A terminal to which an analog signal is applied by reading a signal recorded on an object; a binarization circuit connected in parallel to the application terminal and having different binarization operation characteristics; A binary signal reading device comprising: a sequential processing circuit to which the output of a binary circuit is applied and converts it into a sequential signal; and a decoder circuit that decodes the output of the sequential processing circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4045190U JPH0751635Y2 (en) | 1990-04-16 | 1990-04-16 | Binary signal reader |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4045190U JPH0751635Y2 (en) | 1990-04-16 | 1990-04-16 | Binary signal reader |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0462U true JPH0462U (en) | 1992-01-06 |
| JPH0751635Y2 JPH0751635Y2 (en) | 1995-11-22 |
Family
ID=31550255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4045190U Expired - Lifetime JPH0751635Y2 (en) | 1990-04-16 | 1990-04-16 | Binary signal reader |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0751635Y2 (en) |
-
1990
- 1990-04-16 JP JP4045190U patent/JPH0751635Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0751635Y2 (en) | 1995-11-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |