JPH0462628B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a sub-screen data transfer timing generation circuit in a two-screen television receiver.

(Prior Art) In recent years, with the digitalization of television receivers, two-screen television receivers have been implemented that simultaneously display a small monitor image (sub-screen) within a standard image (main screen). Generally, there is no synchronous relationship between the main screen video signal and the sub-screen video signal in a two-screen display system, and each video signal is independently applied to the main screen video signal processing circuit and the sub-screen video signal processing circuit. . Therefore, when displaying a sub-screen within the main screen, data sampling of the sub-screen video signal, writing of the sampled video signal data to the buffer memory, and data sampling from the buffer memory to the sub-screen are performed based on the respective horizontal and vertical synchronization signals. Data is transferred to the display memory corresponding to the display position and data is read from the display memory.

In such data processing, the video signal data for one horizontal scan of the sub-screen that has been sampled and written to the buffer memory must be transferred to the display memory before being written to the next buffer memory. At this time, if the read timing of sub-screen display data from the display memory (main screen synchronization signal standard) matches the transfer timing of video signal data from the buffer memory, the memory cannot be written and read at the same time. Therefore, errors occur in the sub-screen data. Therefore, it is necessary to prevent the timing of displaying the sub-screen within the main screen and the timing of transferring the video signal data of the sub-screen from overlapping.

A conventional example of a sub-screen data transfer timing generator for preventing such an overlap between the sub-screen display timing and the data transfer timing to the display memory is shown in FIGS. 7 and 8. Figure 7 shows a reference signal generation circuit that generates a reference signal HBL that serves as a reference for transfer timing, and Figure 8 shows the luminance signal data transfer timing, color difference signal data transfer timing, and sub-screen display based on this reference signal HBL. This is a timing pulse generation circuit that generates timing.

In the reference signal generation circuit shown in FIG.
MH indicates the main screen horizontal flyback pulse and its inverted signal. PS is a display position designation signal that specifies the sub-screen display position; PS
When PS = 1 ('H' level), the screen is displayed on the left side of the main screen, and when PS = 0 ('L' level),
displayed on the right.

First, the operation when PS=1 will be explained with reference to FIG. One-shot multivibrator M1
detects the rising edge of the main screen horizontal flyback pulse (see Figure 9a) and generates a pulse signal 1Q (see Figure 9b) whose pulse width is determined by the time constant of capacitor C1 and resistors R1 and R2. )
Output. This pulse signal 1Q is applied to an input terminal 2A of a one-shot multivibrator M2. As a result, the one-shot multivibrator M2 is triggered by the falling edge of the pulse signal 1Q, and the capacitor C2, the resistors R3, R
4 outputs a pulse signal 2Q whose pulse width is determined. The inverted output 2 of this pulse signal 2Q becomes the reference signal (see FIG. 9c).

Next, the operation when PS=0 will be explained with reference to FIG. One-shot multivibrator M
Since PS=0 is input to the input terminal 1B of No. 1, even if the main screen horizontal flyback pulse is input to the input terminal 1A, its output 1Q does not change (see FIG. 10b). On the other hand, orgate G
Main screen horizontal flyback pulse MH via 21
(see Fig. 10a) is applied to the input terminal 2B of the one-shot multivibrator M2, so when the trigger is applied at the rising edge of this pulse MH, the one-shot multivibrator M2 outputs the pulse signal 2 (see Fig. 10). (see c).

The reference signal thus obtained is applied to the timing pulse generation circuit shown in FIG. This timing pulse generation circuit will be explained below with reference to FIG.

FIG. 11a shows the reference signal given from the reference signal generation circuit shown in FIG. 7 with its time axis enlarged. Oscillator 41 shown in FIG.
oscillates when given a reference signal and outputs a clock pulse to the display counter 42. The display counter 42 outputs a dot count signal 128C every time it counts 128 clock pulses.
(see Figure 11b). Here, the reason why it is set to 128 is because the number of horizontal display dots on the sub screen is set to 128, as will be understood from the explanation later. D flip-flop FF given dot count signal 128C from display counter 42
11, its output 11Q, 11 is inverted every time the dot count signal 128C is input (first
(See Figure 1 c, d). This output 11 is used as a luminance signal data transfer timing signal, and the output 11Q is used as a color difference signal data transfer timing signal.

By applying the luminance signal data transfer timing signal to the D flip-flop FF12,
The D flip-flop FF12 is triggered by the rising edge of the signal and outputs a pulse signal 12Q (see FIG. 11e). This pulse signal 12
Q is given to AND gate G22 and added to the luminance signal data transfer timing signal. This AND output (see FIG. 11f) is used as a sub-screen display timing signal PD for reading data from the display memory.

FIG. 12 shows the relationship between the sub-screen display timing signal PD obtained in this way and the sub-screen display position. Figure a shows the main screen horizontal flyback pulse.
Shows MH. The figure b shows the reference signal when PS=1, and the figure c shows the reference signal when PS=1.
HBL, c in the figure is the sub-screen display timing signal PD when PS=1. The figure d shows the reference signal when PS=0, and the figure e shows the sub-screen display timing signal PD when PS=0. Figure f shows the display positions of the sub-screens (SP1 to SP4) corresponding to each of the sub-screen display timing signals PD within the main screen MP. In addition, VS shown in figure f is
A signal that sets the vertical position of the sub screen, VS
When VS=0, the sub-screen is displayed at the top of the main screen MP, and when VS=1, the sub-screen is displayed at the bottom of the main screen MP. However, since it is not directly related to the present invention, a description of the configuration for obtaining the signal VS will be omitted.

As mentioned above, the main screen horizontal flyback pulse
Create a reference signal from MH() and use it as a luminance signal data transfer timing signal.
By separating the YS, color difference signal data transfer timing signal and sub-screen display timing signal PD, the data transfer timing and display timing are prevented from coinciding.

However, even if the data transfer timing and display timing are set not to match, there is no synchronization relationship between the main screen video signal and the sub-screen video signal, so if these timings and the sub-screen video signal data do not match, Unable to synchronize with sampling timing. Therefore, there is a possibility that the timing of sampling the sub-screen data and the timing of transferring it to the display memory may overlap.

Therefore, as shown in FIG. 8, the D flip-flop FF13 is triggered at the rising edge of the sampling signal output every time the sub-screen is scanned three times, and the output 13Q is used to transfer the data transfer area TP. It is set. FIG. 13 shows the operating waveforms at this time. FIG. 13a shows the horizontal synchronizing signal of the sub-screen, FIG. 13b shows the sampling signal, and FIG. 13c shows the output 13Q. The output 13Q is applied to the D input terminal of the D flip-flop FF14 shown in FIG. 8, and is latched at the rising edge of the reference signal (see d in the same figure). This makes the D flip-flop
Output 14Q of FF14 becomes "H" level. Since this output 14Q is given as one input of the NAND gate G23, the NAND gate G23 becomes "L" level when the luminance signal data transfer timing signal rises.
As a result, D flip-flops FF13, FF14
is cleared and each D flip-flop FF13,
From FF14 to the TP signal shown in Figure 13c and e
LD signals are output respectively. As understood from the above explanation, the period in which the LD signal is at the "H" level is a period that includes the color difference signal data transfer period and the luminance signal data transfer period.
Therefore, while this LD signal is being output, the video signal data of the sub-screen is transferred from the buffer memory to the display memory using the luminance signal data transfer timing signal and the color difference signal data transfer timing signal. , the sampling timing of the video signal data of the sub-screen (the period during which the sampling signal is at the "L" level) and the transfer timing are made not to overlap.

However, the conventional sub-screen data transfer timing generator described above generates the data transfer timing signal LD in accordance with the rising edge of the reference signal, so the next data is generated after the sub-screen display timing signal PD is output. Until the transfer timing signal LD is output, there is a waiting time such as a period during which the reference signal is at "L level". Therefore, the conventional device has a problem in that the data transfer period is limited by the waiting time, resulting in poor data transfer efficiency.

(Object of the Invention) The present invention has been made in view of the above circumstances, and an object of the present invention is to efficiently transfer sub-screen video signal data written in a buffer memory to a display memory.

(Structure of the invention) In order to achieve such an object, the present invention has the following features:
It has the following structure.

FIG. 1 is a block diagram schematically showing the configuration of the present invention. A sub-screen data transfer timing generating device 1 in a two-screen display television receiver according to the present invention is a device that generates a timing for transferring sub-screen video signal data written in a buffer memory 2 to a display memory 3, and includes: By counting the horizontal synchronizing signal H of the sub-screen video signal, a sampling signal of the sub-screen video signal is output, and by counting the control clock pulses of the buffer memory 2, the number of horizontally displayed dots on the sub-screen is determined. a counting means 4 which outputs a dot count signal C for each number corresponding to the sub-screen display position; a sub-screen display timing signal generating means 5 which outputs a sub-screen display timing signal according to the sub-screen display position; and a sampling signal from the counting means 4. and dot count signal C from the sub-screen display timing signal generating means 5 as a sub-screen display timing signal.
and a data transfer timing signal generating means 6 respectively provided with DISP.

The data transfer timing signal generating means 6 includes:
a first flip-flop FF1 that inverts its output at the end of the sampling period of the sub-screen video signal by receiving the sampling signal from the counting means 4; and a second flip-flop FF2 that latches the output 1Q of the first flip-flop FF1 at the end of the display period.

the first and second flip-flops FF1,
FF2 is cleared based on the dot count signal.

The output 2Q of the second flip-flop FF2 is applied to the counting means 4 as a control signal for starting clock pulse counting, and is also output as a data transfer timing signal.

Next, the operation of the above-mentioned invention will be explained with reference to FIG. The operational waveform diagram shown in FIG. 2 is shown to facilitate understanding of the operation of the present invention, and the present invention is not limited to such an operational waveform diagram. Of course.

By counting the horizontal synchronizing signal H of the sub-screen video signal, a sampling signal is output from the counting means 4 (see FIG. 2a). In figure a,
The "L" level period corresponds to the sampling period. By applying this sampling signal to the data transfer timing signal generation means 6,
The output of the first flip-flop FF1 of the data transfer timing signal generating means 6 is inverted (see FIG. 2c), and its output 1Q is applied to the second flip-flop FF2.

On the other hand, a sub-screen display timing signal (FIG. 2b) is generated from the sub-screen display timing signal generating means 5.
) is applied to the second flip-flop FF2. In Figure b, the "L" level period corresponds to the sub-screen display period. The second flip-flop FF2 is triggered by the sub-screen display timing signal and latches the output 1Q. As a result, the output 2Q of flip-flop FF2 is inverted (see FIG. 2d). Simultaneously with the inversion of the output 2Q, the clock pulses are counted, and when the number of clock pulses corresponding to the number of horizontally displayed dots on the sub-screen has been counted, the dot count signal C is output from the counting means 4 (see Fig. 2e). reference).
Based on this dot count signal C, the first and second flip-flops FF1 and FF2 are cleared (see FIGS. 2c and d).

The output 2Q of this second flip-flop FF2
occurs simultaneously with the end of the sub-screen display, and its pulse width corresponds to the reading period of the sub-screen video data written in the buffer memory 2. This is because counting of clock pulses starts almost simultaneously with the end of the sub-screen display, and the dot count signal C is output by counting clock pulses corresponding to the number of horizontally displayed dots on the sub-screen. This is because the number of horizontal display dots corresponds to the number of video signal data of the sub-screen written in the buffer memory 4. Therefore, by using the output 2Q of the second flip-flop FF2 as a data transfer timing signal, the video signal data of the sub-screen written in the buffer memory 2 can be transferred to the display memory 3 at the same time as the sub-screen display ends. can.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 3 is a block diagram schematically showing a sub-screen video signal processing system of a two-screen television receiver using a sub-screen data transfer timing generator according to an embodiment of the present invention.

The sub-screen video signal is sent to the sub-screen video signal processing circuit 2.
1, and is separated into a luminance signal (-Y), color difference signals (RY), (B-Y), a vertical synchronizing signal V, and a horizontal synchronizing signal H. The luminance signal (-Y) and color difference signals (R-Y), (B-Y) are sent to the multiplexer 2.
given to 2. The time-series luminance signal and color difference signal output from the multiplexer 22 are provided to an A/D converter 23. The luminance signal data and color difference signal data obtained as digital data are written into the buffer memory 24. This buffer memory 24 is composed of a line memory having a data area at least twice the number of horizontal dots on the sub-screen. In this embodiment, the number of horizontal dots on the sub screen is 128, so the buffer memory 2
4 is used in which 256 pieces of data can be written.

The brightness signal data read from the buffer memory 24 is given to the brightness signal display memory 26 via the buffer 25. Luminance signal display memory 26
is provided with a data area capable of storing luminance signal data for one field of the sub-screen. On the other hand, the color difference signal data read from the buffer memory 24 is transferred to the color difference signal display memory 2 via the buffer 27.
given to 8. The color difference signal display memory 28 has a data area capable of storing color difference signal data for one field of the sub-screen.

On the other hand, the synchronization signals V and H separated by the sub-screen video signal processing circuit 21 are given to a counter section 29 as a counting means. The counter unit 29 includes a ternary counter (not shown) that counts the horizontal synchronization signal H;
It consists of a first address counter (not shown) that counts clock pulses for controlling the buffer memory 24, and a second address counter that counts clock pulses for display. The first and second address counters are configured to count up to twice the number of horizontal dots on the sub-screen. The oscillator 30 is a buffer memory 24
Outputs clock pulses for control. This clock pulse is applied to inverter G1 and AND gate G2.
and the counter section 29 via the OR gate G3.
is given to the first address counter of. Further, the clock pulse is divided into 1/2 by a frequency divider 31.
After being frequency-divided, the signal is applied to the first address counter via an AND gate G4 and an OR gate G3. An oscillator 32 generates a clock pulse for display, which clock pulse is applied to the second address counter.

Address buses of counter section 29 colors A ₀ to A ₁₃ are output. The other ends of A ₀ and A ₁ are connected to the control terminal of the multiplexer 22 . Further, the other ends of the address buses A ₁ to _{A 7} are connected to address terminals of the buffer memory 24 . The _A0 terminal of the counter section 29 is connected to the buffer memory 24 via an AND gate G5 and an OR gate G6.
Connected to A ₀ terminal. Also, the address bus
The other ends of A ₁ to _{A 13} are connected to display memories 26 and 28, respectively.

Furthermore, the counter section 29 includes 3
Sampling signal S based on the output of the decimal counter
and its inverted signal is output. The sampling signal S is given as a control signal to the AND gate G4, and is also sent to the oscillator 3 via the OR gate G7.
0 as a drive control signal. On the other hand, the inverted signal is generated by a data transfer timing signal generation circuit 33 as a data transfer timing signal generation means constituted by D flip-flops FF1 to FF4.
given to.

In the data transfer timing signal generation circuit 33, the D input terminal of the D flip-flop FF1,
Preset terminals (active LOW) of each D flip-flop FF1 to FF4 are connected to the power supply line Vcc. The output 1Q of the D flip-flop FF1 is given as the D input of the D flip-flop FF2. The output 2Q of the D flip-flop FF2 is provided as the D input of the D flip-flop FF3, and is also provided as a drive control signal for the oscillator 30 via an OR gate G7. Moreover, the inverted output 2 of the D flip-flop FF2 is
The signal is given to the AND gate G5 and the transfer control circuit 34 as respective control signals. The output 3Q of D flip-flop FF3 is the output of D flip-flop FF4.
It is also applied to the _A0 terminal of the buffer memory 24 via the OR gate G6, and is further applied to the transfer control circuit 34 as a control signal. The transfer control circuit 34 transfers the luminance signal data and color difference signal data read from the buffer memory 24 to predetermined display memories 26 and 27 based on the two control signals.

On the other hand, a dot count signal 128C is applied from the counter section 29 to the clock pulse input terminals CK of the D flip-flops FF3 and FF4. The dot count signal 128C is output every time the first address counter included in the counter section 29 counts 128 clock pulses. The inverted output 4 of the D flip-flop FF4 is applied to the clear terminals (active LOW) of the D flip-flops FF1 to FF3. Also, the clock pulse input terminals CK and D of the D flip-flop FF2 are
The clear terminal of flip-flop FF4 receives a sub-screen display timing signal corresponding to the sub-screen display position.
DISP is given. This sub-screen display timing signal is output as an inverted signal of the sub-screen display timing signal DISP from a sub-screen display timing generation circuit 40 as a sub-screen display timing signal generating means shown in FIG.

The sub-screen display timing signal generation circuit 40 includes a one-shot multivibrator M1 for setting the position of the sub-screen when the sub-screen is displayed on the left side of the main screen, and a one-shot multivibrator M1 for setting the position of the sub-screen when the sub-screen is displayed on the right side of the main screen. and a one-shot multivibrator M2 for setting its position. Input terminal 1 of these one-shot multivibrators M1 and M2
A, 2A shows the horizontal flyback pulse of the main screen.
An inverted signal of MH is given. The outputs of the one-shot multivibrators M1 and M2 are connected to inverters G8 and G9 and AND gates G10 and G1.
1. One of the outputs is applied to the clock pulse input terminal CK of the D flip-flop FF5 via a selection circuit 41 constituted by an OR gate G12. Further, the selection circuit 41 is controlled by a display position designation signal PS that designates a sub-screen display position. The output 5Q of the D flip-flop FF5 is applied to an oscillator 32 for generating a display clock. The display clock pulse output from the oscillator 32 is applied to a second counter 29a included in the counter section 29. Second counter 29a
not only addresses the display memories 26 and 28, but also outputs a dot count signal 128' when 128 clock pulses have been counted.
This dot count signal 128' is applied to the clear terminal CL of the D flip-flop FF5 via the inverter G13. Then, the inverted output 5 of the D flip-flop FF5 is given to the data transfer timing signal generation circuit 33 as a sub-screen display timing signal.

Next, the operation of the embodiment having the above-mentioned configuration will be explained in the fifth section.
The explanation will be based on the operation waveform diagram shown in the figure.

From the sub-screen video signal processing circuit 21 to the counter section 2
By applying the horizontal synchronizing signal H to the ternary counter 9, the counter section 29 performs sampling for extracting one horizontal scanning line from three horizontal scanning lines, as shown in FIG. 5a. signal S,
The inverted signal shown in FIG. 4B is output. The "H" level period of the sampling signal corresponds to the sampling period Ts. During this sampling period Ts, the oscillator 30 is driven, and
AND gate G4 becomes conductive. On the other hand, until the sampling period Ts ends, the AND gate G2
is in a blocked state. Therefore, during the sampling period, the clock pulse of the oscillator 30 whose frequency is divided by 1/2 is input to the counter section 29. This clock pulse is counted by the first address counter of the counter section 29. When the first address counter counts up to 256, the sampling signal S and its inverted signal are inverted.

On the other hand, during the period during which the sampling signal S is output (sampling period Ts), the output of the lower two bits of the first address counter is applied as a switching control signal to the multiplexer 22 via the address buses A ₀ and A ₁ . Multiplexer 22
Based on this switching control signal, the luminance signal (-Y) input and the color difference signal (RY), (B-Y) input are time-divided, and each of the above signals is changed from (RY) to (-
Output in the order of Y)→(B-Y)→(-Y)→... Here, the time-divided color difference signal (RY),
The number of each (B-Y) is half of the luminance signal (-Y), but since the bandwidth of the color difference signal is narrower than that of the luminance signal, the color difference signal (R-
Y) and (B-Y) are the luminance signal (-
Even if it is less than Y), the image quality of the sub-screen will not deteriorate.

The time-divisionally output luminance signal and color difference signal are converted into digital data by the A/D converter 23 in accordance with the timing of the clock pulse whose frequency is divided into 1/2 by the frequency divider 31. Therefore, in the sampling period Ts, 128 pieces of luminance signal data and color difference signal data are obtained, and these data are given to the buffer memory 24 in the order of the signal data described above via the data buses _D0 to _D5 . .

On the other hand, except during the data transfer period of the buffer memory 24 (including the sampling period),
Inverted output 2 of D flip-flop FF2 is “H”
It's getting to the level. Therefore, the AND gate G5 to which the inverted output 2Q is applied is open. As a result, the count value of the first address counter of the counter section 29 is applied to the address terminals _A0 to _A7 of the buffer memory 24 via the AND gate G5, the OR gate G6, and the address buses _A1 to _A7 .

In this way, the luminance signal data and color difference signal data are sequentially written into the data area specified by the count value of the first address counter.
Here, since the luminance signal data and color difference signal data are transmitted alternately, for example, the color difference signal data is written to even addresses of the buffer memory 24, and the luminance signal data is written to odd addresses.

Next, the operation of the sub-screen display timing signal generation circuit 40 shown in FIG. 4 will be explained with reference to FIG. 6.

Assume that the sub-screen display position designation signal PS is set to "1" in order to display the sub-screen on the left side of the main screen. Then, the selection circuit 41
The AND gate G10 has one input as “L”.
It is shut down because it reaches the level. On the other hand, AND gate G11 is open because one of its inputs is at the "H" level. In this case, when the main screen horizontal flyback pulse shown in FIG. One-shot multivibrator M with a delay based on a constant
The inverted output of 1 rises (see b in the same figure). This inverted output is applied to the D flip-flop FF5 via the selection circuit 41, so that the output 5Q (DISP) of the D flip-flop FF5 rises (see d in the figure).

Output 5Q of D flip-flop FF5 is “H”
When the level is reached, the oscillator 32 is driven and a display clock pulse is applied to the second counter 29a. When 128 clock pulses have been counted, a dot count signal 128' is output from the second counter 29a (see c in the same figure). This dot count signal 128' is applied to the inverter G.
13 to the clear terminal of the D flip-flop FF5, the output 5Q is cleared (see d in the figure). Therefore, while the output 5Q is at the "H" level, the sub-screen is displayed on the left side of the main screen (see h in the figure). In addition, in the figure h, MP indicates the main screen, SPL indicates the sub-screen displayed on the left, and SPR indicates the sub-screen displayed on the right. Then, the inverted output 5 of the D flip-flop FF5 is given to the data transfer timing signal generation circuit 33 as a sub-screen display timing signal.

On the other hand, when the sub-screen display position designation signal PS is set to "0" in order to display the sub-screen on the right side of the main screen, the inverted output of the one-shot multivibrator M2 (see e in the same figure) is transferred to the D flip-flop. Given to FF5. As a result, the output 5Q of the D flip-flop FF5 becomes "H" level, and the display clock pulses are counted in the same manner as described above, and the dot count signal 128'
is output (see f in the same figure). As a result, the sub-screen display timing signal DISP corresponding to the right display position is output from the output 5Q of the D flip-flop FF5 (see g and h in the figure).

Returning to FIG. 3, when the first address counter of the counter section 29 counts up and data writing is completed, the oscillation of the oscillator 30 stops because the sampling signal S is no longer output.
Further, as shown in FIG. 5d, when a trigger is applied at the rising edge of the inverted signal, the output 1Q of the D flip-flop FF1 becomes "H" level.
The D flip-flop FF2 to which this output 1Q is applied latches the output 1Q when triggered by the rising edge of the sub-screen display pulse shown in FIG. However, the sub-screen display timing signal shown in FIG. 5c is shown by reducing the time axis of the inverted signal of the sub-screen display timing signal DISP shown in FIG.

The output 2Q is given to the oscillator 30 as a data transfer control signal to start oscillation, and
Open AND gate G2. As a result, the clock pulse output from the oscillator 30 is applied to the counter section 29 via the inverter G1, AND gate G2, and OR gate G3 without being frequency-divided.

On the other hand, when data is transferred to the display memories 26 and 27, the inverted output 2 of the D flip-flop FF2
Since Q is at the "L" level, AND gate G5 is blocked. Furthermore, during the period from when output 2Q rises to when the first dot count signal 128C is input to D flip-flop FF3 (the first half of the data transfer period), output 3Q of D flip-flop FF3 becomes "L" level. There is. Therefore, in the first half of data transfer, the address terminal _A0 of the buffer memory 24 is fixed at "0". As a result, in the first half of the data transfer period, the data written in the even address of the buffer memory 24, ie, the color signal data, is read out and placed on the data buses _D0 to _D5 . Since the address terminal _A0 is fixed at "0", the first address counter specifies one address every two clock pulses. Therefore, in order to make the read speed similar to the write speed, clock pulses without frequency division were counted during data transfer.

The transfer control circuit 34 is a D flip-flop FF.
2 inverted output 2 and D flip-flop FF3
By receiving the output 3Q of , it is detected that the color difference signal data has been read out. As a result, the buffer memory 27 and the color difference signal display memory 2
8 and set to write state. In this way, the color difference signal data read from the buffer memory 24 is transferred to the color difference signal display memory 28 via the buffer memory 27 and written to the address specified by the second address counter of the counter section 29.

By the way, the first address counter of the counter section 29 outputs a dot count signal 128C shown in FIG. 5f every time it counts 128 clock pulses. By applying the first dot count signal to the clock pulse input terminal CK of the D flip-flop FF3, the D flip-flop FF
3 latches the output 2Q given from the D flip-flop FF2, and the output 3Q becomes the "H" level (see FIG. 5g). Then, when the subsequent dot count signal is output, the D flip-flop FF4 latches the "H" level output 3Q,
The inverted output 4 becomes "L" level. Due to the falling of inverted output 4, the D flip-flop
FF1 to FF3 are cleared and each output 1Q, 2Q,
3Q becomes the "L" level as shown in FIG. 5 d, e, and g.

That is, in the latter half of the data transfer period (from when the first dot count signal 128C is output to when the next dot count signal 128C is output), the output 3Q of the D flip-flop FF3 becomes "H" level, which causes the OR gate to It is applied to the _A0 terminal of the buffer memory 24 via G6.
Therefore, in the second half of the data transfer period, the address terminal _A0 of the buffer memory 24 is fixed to "1", so that the luminance signal data written at the parsimonious address is read out during this period.

The transfer control circuit 34 receives the inverted output 2 of the D flip-flop FF2 and the output 3Q of the D flip-flop FF3, so that
Detects that luminance signal data has been read.
As a result, the buffer 25 and the luminance signal display memory 26 are set to the write state. In this way, the brightness signal data read from the buffer memory 24 is transferred to the brightness signal display memory 26 via the buffer memory 25.

As mentioned above, data transfer is performed almost simultaneously with the rising edge of the sub-screen display pulse (the end of the sub-screen display), so that by the time the next sub-screen display starts (the falling edge of the sub-screen display pulse) , the respective data in the buffer memory 24 are transferred to a luminance signal display memory 26 and a color difference signal display memory 28.

Then, triggered by the falling edge of the sub-screen display pulse, the D flip-flop FF
4 is cleared, its inverted output 4
returns to the “H” level, and the D flip-flop
Clearing of FF1 to FF3 is canceled. After that, one scanning line is extracted from the three scanning lines in the same way,
The luminance signal and color difference signal of the sub-screen video signal are time-divisionally processed and then converted into digital data and written into the buffer memory 24. Then, almost at the same time as the sub screen display ends, the buffer memory 2
4, the video signal data of the sub-screen is transferred to each display memory 26, 28.

The luminance signal data and color difference signal data written in the display memories 26 and 28 are read out during the period when the sub-screen display timing signal DUSP is output, and are D/A converted, and then displayed on the main screen and sub-screen (not shown). switching circuit. Then, by switching this switching circuit in accordance with the sub-screen display timing, the sub-screen is displayed at a predetermined position on the main screen.

In the above embodiment, the video signal of the sub-screen is extracted every three horizontal scanning lines, and the number of horizontal display dots of the sub-screen is 128. However, the present invention Of course, this is not limited to these cases.

(Effects of the Invention) As is clear from the above description, the sub-screen data transfer timing generating device in the dual-screen display television receiver according to the present invention is based on detecting the edge of the sub-screen display timing signal.
The device is configured to start transferring the video signal data of the sub-screen from the buffer memory to the display memory almost at the same time as the display of the sub-screen ends.

Therefore, according to the present invention, since there is almost no waiting time between the end of the sub-screen display and the transfer of the next data to the display memory, the video signal data of the sub-screen can be efficiently transferred to the display memory. Can be transferred.

Incidentally, in the conventional example described above, the clock for data transfer is created by the clock for display. Therefore, in the conventional example, when the frequency of the display clock pulse is adjusted to adjust the size of the sub-screen, the frequency of the transfer clock also changes. Therefore, the conventional sub-screen data transfer timing generator has the disadvantage that it takes into account that the display clock is adjusted at high speed and requires a high-speed memory that can follow this adjustment. However, in the embodiments described in FIGS. 3 and 4, the clock pulses for data transfer and the clock pulses for display are obtained from separate oscillators. Therefore,
According to the embodiment described above, there is no need to take into account changes in the frequency of the display clock, so a unique effect is achieved in that a high-speed memory is not required.

Further, in the conventional example, as shown in FIG. 7, the left and right positions of the sub-screen are determined by a reference signal generated by the interlocking of the one-shot multivibrators M1 and M2. Therefore,
When setting the left and right positions of the sub-screen, it is first necessary to set the left side of the screen using the one-shot multivibrator M2, and then set the right side of the screen using the one-shot multivibrator M1. If you set the position on the right side of the screen and then set the position on the left side of the screen, the set position on the right side of the screen will move, which is cumbersome as you will have to repeat the adjustment of the screen position several times. As described above, the conventional device also has the problem that the left and right positions of the sub-screen cannot be adjusted independently. However, according to the above-mentioned embodiment, as shown in FIG. 4, by applying a horizontal flyback pulse to the main screen, one-shot multibubbles that operate independently are used to control the left and right sides of the sub-screen. Each location can be set independently.
Therefore, according to the embodiment, there is also the unique advantage that there is no trouble when adjusting the position of the sub-screen.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing the configuration of a sub-screen data transfer timing generation device in a two-screen television receiver according to the present invention, and FIG. 2 is an explanatory diagram of the operation of the device of the present invention shown in FIG. , FIG. 3 is a block diagram showing the outline of the configuration of an embodiment of the present invention, FIG. 4 is a circuit diagram showing the configuration of the sub-screen display timing signal generation circuit in the embodiment, and FIG. 6th explanatory diagram of the operation of the embodiment shown in the figure.
This figure is an explanatory diagram of the operation of the sub-screen display timing signal generation circuit shown in FIG. 4. 7 to 13 are explanatory diagrams of conventional examples. Figure 7 shows a circuit that generates a reference signal that serves as a reference for transfer timing, Figure 8 shows a circuit that generates a data transfer timing signal based on the reference signal, and Figures 9 and 10 are shown in Figure 7. These are diagrams illustrating the operation of the circuit, in particular, FIG. 9 shows the case where the sub-screen is displayed on the left side of the main screen, and FIG. 10 shows the case where the sub-screen is displayed on the right side of the main screen. FIG. 11 is an explanatory diagram of the operation when obtaining the transfer timing signal and the sub-screen display timing signal in the circuit of FIG. 8, and FIG. 12 is an explanatory diagram showing the relationship between the sub-screen display timing signal and the sub-screen position, etc. , FIG. 13 is an explanatory diagram showing the synchronization relationship between sampling and timing of sub-screen data and data transfer timing. 21...Subscreen video signal processing circuit, 22...Multiplexer, 23...A/D converter, 24...Buffer memory, 26...Luminance signal display memory, 28...Color difference signal display memory, 29...Counter section, 30...Buffer memory control Oscillator, 32... Oscillator for display memory control, 33... Data transfer timing signal generation circuit, 40... Sub screen display timing signal generation circuit, FF1 to FF5...D flip-flop, M
1, M2...One-shot multivibrator.

Claims (1)

[Scope of Claims] 1. A sub-screen data transfer timing generation device in a two-screen television receiver that generates a timing for transferring sub-screen video signal data written in a buffer memory to a display memory, comprising: a sub-screen image; By counting the horizontal synchronization signals of the signals, a sampling signal of the sub-screen video signal is output, and by counting the control clock pulses of the buffer memory, the sampling signal is output every number corresponding to the number of horizontal display dots on the sub-screen. counting means for outputting a dot count signal to the sub-screen display position; sub-screen display timing signal generating means for outputting a sub-screen display timing signal according to the sub-screen display position; and a data transfer timing signal generating means that receives a sub-screen display timing signal from the screen display timing signal generating means, and the data transfer timing signal generating means receives a sampling signal from the counting means to generate a sub-screen display timing signal. a first flip-flop for inverting its output at the end of a video signal sampling period; and a second flip-flop for latching the output of the first flip-flop at the end of the sub-screen display period by being provided with the sub-screen display timing signal. a flip-flop, the first and second flip-flops are cleared based on the dot count signal, and the output of the second flip-flop is applied to the counting means as a control signal for starting clock pulse counting. What is claimed is: 1. A sub-screen data transfer timing generator for a two-screen television receiver, characterized in that the sub-screen data transfer timing signal is given as a data transfer timing signal for transferring sub-screen video signal data.