JPH0462456B2 - - Google Patents

Info

Publication number
JPH0462456B2
JPH0462456B2 JP60095203A JP9520385A JPH0462456B2 JP H0462456 B2 JPH0462456 B2 JP H0462456B2 JP 60095203 A JP60095203 A JP 60095203A JP 9520385 A JP9520385 A JP 9520385A JP H0462456 B2 JPH0462456 B2 JP H0462456B2
Authority
JP
Japan
Prior art keywords
bonding
wire
bonding wire
ball
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60095203A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61253824A (ja
Inventor
Mitsuo Kobayashi
Osamu Usuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP60095203A priority Critical patent/JPS61253824A/ja
Publication of JPS61253824A publication Critical patent/JPS61253824A/ja
Publication of JPH0462456B2 publication Critical patent/JPH0462456B2/ja
Granted legal-status Critical Current

Links

Classifications

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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP60095203A 1985-05-02 1985-05-02 半導体素子の組立方法 Granted JPS61253824A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60095203A JPS61253824A (ja) 1985-05-02 1985-05-02 半導体素子の組立方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60095203A JPS61253824A (ja) 1985-05-02 1985-05-02 半導体素子の組立方法

Publications (2)

Publication Number Publication Date
JPS61253824A JPS61253824A (ja) 1986-11-11
JPH0462456B2 true JPH0462456B2 (enrdf_load_stackoverflow) 1992-10-06

Family

ID=14131190

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60095203A Granted JPS61253824A (ja) 1985-05-02 1985-05-02 半導体素子の組立方法

Country Status (1)

Country Link
JP (1) JPS61253824A (enrdf_load_stackoverflow)

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