JPH0462217B2 - - Google Patents

Info

Publication number
JPH0462217B2
JPH0462217B2 JP11986283A JP11986283A JPH0462217B2 JP H0462217 B2 JPH0462217 B2 JP H0462217B2 JP 11986283 A JP11986283 A JP 11986283A JP 11986283 A JP11986283 A JP 11986283A JP H0462217 B2 JPH0462217 B2 JP H0462217B2
Authority
JP
Japan
Prior art keywords
pulse
circuit
edge
output
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11986283A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6012839A (ja
Inventor
Akira Fujimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NYUURON KK
Original Assignee
NYUURON KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NYUURON KK filed Critical NYUURON KK
Priority to JP11986283A priority Critical patent/JPS6012839A/ja
Publication of JPS6012839A publication Critical patent/JPS6012839A/ja
Publication of JPH0462217B2 publication Critical patent/JPH0462217B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
JP11986283A 1983-07-01 1983-07-01 信号復調装置 Granted JPS6012839A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11986283A JPS6012839A (ja) 1983-07-01 1983-07-01 信号復調装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11986283A JPS6012839A (ja) 1983-07-01 1983-07-01 信号復調装置

Publications (2)

Publication Number Publication Date
JPS6012839A JPS6012839A (ja) 1985-01-23
JPH0462217B2 true JPH0462217B2 (enrdf_load_stackoverflow) 1992-10-05

Family

ID=14772105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11986283A Granted JPS6012839A (ja) 1983-07-01 1983-07-01 信号復調装置

Country Status (1)

Country Link
JP (1) JPS6012839A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0658307B2 (ja) * 1988-11-16 1994-08-03 三菱電機株式会社 プラント異常点検装置

Also Published As

Publication number Publication date
JPS6012839A (ja) 1985-01-23

Similar Documents

Publication Publication Date Title
US4371974A (en) NRZ Data phase detector
US4380815A (en) Simplified NRZ data phase detector with expanded measuring interval
JPS6238791B2 (enrdf_load_stackoverflow)
US5936430A (en) Phase detection apparatus and method
US3602828A (en) Self-clocking detection system
US4371975A (en) Sampling NRZ data phase detector
KR900001593B1 (ko) 디지탈신호 재생회로
SU1301326A3 (ru) Устройство дл информации с магнитной ленты (его варианты)
US4606053A (en) Bi-phase decoder
US5619171A (en) Phase-locked loop, phase comparator for use in the phase-locked loop, and reproducing device including the phase-locked loop
US4907092A (en) Modulating/demodulating circuit for multiplex recording/playback of data in a magnetic recording/playback system
JP2592795B2 (ja) 情報データ復調装置
US3982194A (en) Phase lock loop with delay circuits for relative digital decoding over a range of frequencies
JPH0462217B2 (enrdf_load_stackoverflow)
US4540947A (en) FM Signal demodulating apparatus
US3656149A (en) Three frequency data separator
JP3237829B2 (ja) クロック識別再生回路
JPS5895447A (ja) クロツク再生回路
US4757520A (en) FM signal demodulating apparatus
JP3371913B2 (ja) 波形歪補正装置
US4291335A (en) Vertical synchronizing signal detector
JPS646582B2 (enrdf_load_stackoverflow)
JPS613544A (ja) 同期クロツク再生装置
JPH0328862B2 (enrdf_load_stackoverflow)
CA1132668A (en) Fast synchronization circuit for phase locked looped decoder