JPH0461486A - High definition television receiver - Google Patents

Abstract

PURPOSE:To eliminate unnaturality in the movement adaptive processing with simple circuit constitution by inputting a picture component in an (m/2-1)- preceding field to a moving picture system processing circuit and applying moving vector correction to a phase of a picture in an (m/2-1)-preceding field. CONSTITUTION:The interpolation phase of an in-field interpolation circuit 13 and an inter-field interpolation filter 52 is controlled by using a subsample clock subject to one field delay through the provision of one field delay devices 47,48 and an inter-frame subsample control circuit 53. Then the moving picture system processing is implemented by using a signal in an (m/2-1)-preceding field (m is a positive integer) and when moving vector correction is applied, reverse moving vector correction is applied with respect to the moving vector correction between fields so as to make a phase of the moving picture system and the still picture system coincident with a phase of a picture in the (m/2-1)- preceding field. Thus, the unnaturality in the movement adaptive processing is solved with simple circuit constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a high-definition television receiver, and particularly to a decoding processing method for high-definition television signals.

(Prior Art) A MUSE system has been proposed that compresses the band of a high-definition television signal so that it can be transmitted by satellite broadcasting, and experimental broadcasting is being conducted.

MUSE is multiple 5ub-Nyquirt
It is an abbreviation for sampling encoding, and N
This is a method developed by HK (Japan Broadcasting Corporation).

The MUSE method is described in various documents (for example, "Nikkei Electronics J, November 2, 1987 issue, pages 189 to 21, published by Nikkei McGraw-Hill.
2 High-definition broadcasting transmission system MUS using r satellites
EJ, etc.), detailed explanation will be omitted here.

The MUSE method luminance signal (Y signal) is an original signal that is AD converted at a sampling frequency of 48.6PvHI+ on the transmitting side.

FIG. 6 is a diagram showing the frequency spectrum characteristics of the MUSE signal.

The still image part is 20 to 22M as shown in Figure 6 (A).
A high-definition television signal (luminance signal) with a band of To is
First, inter-field offset sampling is performed, and the sixth
The spectrum is shown in Figure (B).

Furthermore, the sampling frequency is 32.4MH! Figure 6 (
The spectrum is shown in C).

On the other hand, the video portion is band-limited to 16.2 MHx, then subjected to sampling frequency conversion to 32.4 MHz, and line-offset subsampling. This is the 6th
Shown in Figure (D).

In this way, the band-compressed signal is DA-converted and returned to an analog signal, which is then transmitted as a MUSE signal.

As shown in FIGS. 6(C) and (D), this MUSE signal is 8,1MH! in FIG. 6(A)! The above high frequency component is 8.1MH! The transmission baseband bandwidth is compressed to within the 3.1 MH + band by folding back within the band.

A high-definition television receiver (MUSE decoder) receives and demodulates this band-compressed MUSE signal.

FIG. 7 is a block diagram showing a conventional high-definition television receiver. It mainly shows the brightness signal processing part in a high-definition television receiver.

In FIG. 7, the MUSE signal enters input terminal 1. This input signal is supplied to the AD converter 2,
A 6.2MHx clock signal is resampled to become a digital signal.

The output signal of the AD converter 2 is supplied to a de-emphasis circuit 3.

The output signal of the de-emphasis circuit 3 is supplied to a noise reducer circuit 4 to reduce noise components.

The output signal of the noise reducer circuit 4 is supplied to an interframe interpolation circuit 5. The interframe interpolation circuit 5 further includes a changeover switch 6 and a one-frame delay device 7.

Since a signal offset between frames/lines is transmitted, the receiver (decoder) side converts the data from the sampled points (sample points) to the data at the unsampled points (interpolation points). This is the interpolation process.

The interframe interpolation process is performed at terminal 6a of changeover switch 6.
The current field signal (output signal of noise reducer circuit 4) supplied to Inter-frame sub-sample clock 51 with information (switched in pixel units at 16.2 MH),
Interpolate the signal from one frame before the current field signal,
An output signal with a data period of 32.4 MHI is obtained.

The luminance signal (Y signal) of this MUSE method is a two-frame correlation signal in which a sampling point makes one cycle between two frames. Therefore, in the noise reducer circuit 4, 1
Noise reduction is performed by correlating two frames between the two-frame previous signal that has passed through the frame delay device 7 twice and the output signal of the de-emphasis circuit 3.

Note that the one-frame delay device 7 in the interframe interpolation circuit 5 performs a motion vector correction operation, which will be described later, using the motion vector signal M1.

The output signal of the interframe interpolation circuit 5 is supplied to a still image processing circuit 8 and a moving image processing circuit 9.

The still image processing circuit 8 further includes a low pass filter 10.
Sampling frequency conversion circuit 11. It is composed of an interfield interpolation circuit 12.

The interpolated signal between frames passes through a low-pass filter 10 that passes the frequency band below 12FvHIz, and a sampling frequency conversion circuit 11 changes the sampling frequency from 32.4MHr to 24.3MHr! is converted into 4
8.6MH! Become a rate pig.

The inter-field interpolation operation will be described in detail later.

On the other hand, the moving image processing circuit 9 includes an intra-field interpolation circuit 13
．． It is composed of a sampling frequency conversion circuit 14.

The intra-field interpolation circuit 13 converts the current field signal into an inter-frame sub-sample clock S having interpolation phase information.
1 (Interpolation processing is performed by 16,2MH ri, 32
．． The rate becomes 4MH+, and the sampling frequency conversion circuit 14 makes it 32.4MH! It is converted from 48.6MHr to 48.6MHr.

The output signals of the still image processing circuit 8 and the moving image processing circuit 9 are respectively supplied to a mixer 15 and mixed with the mixing ratio controlled by the motion detection signal Md.

The output signal of the mixer 15 is supplied to the low frequency switching circuit 17, and the low frequency band of 0 to 4 MIh, which does not include the aliasing component shown in FIG. 6(C), is output from the de-emphasis circuit 3. It can be easily replaced with a traffic light.

The output signal of the low frequency switching circuit 17 is sent to an output terminal 18.
A luminance signal output is obtained.

The inter-field interpolation filter is simplified by the inter-field interpolation processing performed by the low-frequency interpolation circuit 17 by interchanging the horizontal frequency band of 0 to 4 MH+.

FIG. 8 is a diagram showing two-dimensional frequency characteristics of the interfield interpolation filter. The horizontal axis represents the horizontal frequency (MH2), and the vertical axis represents the vertical frequency (cycle/screen height).

The filter having the characteristic ■ in FIG. 8 is a simplified interfield interpolation filter, and is a one-dimensional filter with no change in the horizontal direction, and the vertical frequency is 1.
It is attenuated above 125/4 (cycle/screen height),
Vertical resolution is reduced.

In the low-frequency adjustment processing, a signal in the horizontal frequency band of 0 to 4 MHr having the characteristics of ■ in FIG. Vertical resolution can be improved.

Furthermore, even if a motion detection error, which will be described later, occurs, the changeover signal does not pass through the mixer 15, so the adverse effects are reduced to zero to
4MH! It is reduced in the switching band.

Further, in FIG. 7, the output signal of the AD converter 2 is supplied to a de-emphasis circuit 3 and also to a control signal separation circuit 19.

The control signal separation circuit 19 separates a motion vector signal M1 representing movement in the horizontal and vertical directions from the transmitted control signal and outputs it from its terminal 19a.

In addition, the interframe subsample control signal representing interframe subsample phase information is separated, and its terminal 1
It is output from 9b.

Similarly, an interfield subsample control signal representing interfield subsample phase information is separated and output from its terminal 19c.

Further, an inter-field motion vector signal M2 converted from an inter-frame motion vector signal is outputted from its terminal 19d.

The motion vector signal M1 outputted from the terminal 19a of the control signal separation circuit 19 is supplied to the one frame delayer 7 as described above, and is used for motion vector correction.

The inter-frame sub-sampled control signal output from the terminal 19b of the control signal separation circuit 19 is:
The signal is supplied to the interframe subsample control circuit 20.

The inter-frame sub-sample control circuit 2o has 16.2
The MHz clock is controlled by the interframe subsample control signal to output an interframe subsample clock S 1 (16, 2M112), which is supplied to the changeover switch 6 and the interfield interpolation circuit 13 .

Similarly, the terminal 19 of the control signal separation circuit 19
The interfield subsample control signal output from c is supplied to the interfield subsample control circuit 21.

The interfield subsample control circuit 21 includes 24.
The 3MHI clock is controlled by the interfield subsample control signal, and an interfield subsample clock S2 (24.3MH) is outputted and supplied to the interfield interpolation circuit 12.

Further, the output signal of the de-emphasis circuit 3 is supplied to the noise reducer circuit 4 and also to the motion detection circuit 22.

The motion detection circuit 22 detects, for example, the current, 1 frame previous, and 2 frames.
Detects motion (change) components from signals such as before the frame,
It is supplied to the mixer 15 as the motion detection signal Md.

Here, motion vector correction will be explained in detail.

The one-frame delay device 7 has a delay amount varied by the motion vector signal M1 supplied from the control signal separation circuit 19, and performs motion vector correction.

The MUSE method performs motion vector correction when the screen moves in parallel, such as during panning or tilting. This is 1 due to the motion vector signal (horizontal and vertical motion vector signals).
This is done by moving the position of the data before the frame in the horizontal and vertical directions.

Therefore, when the screen is moved in parallel, it can be processed as a still image even though the screen is moving, and high resolution can be obtained by interpolating between frames and fields.

FIG. 9 is a diagram showing the internal configuration of the one-frame delay device 7 in FIG. 7.

In FIG. 9, the output signal of the changeover switch 6 in FIG. 7, which is the output signal of the changeover switch 6 in FIG. Delayed by a predetermined amount of time.

The output signal of the fixed delay device 24 is supplied to a multi-stage delay device 25.

The multi-stage delay device 25 is constructed by cascading delay devices having a delay time of <IH (one horizontal period) as shown in the figure.

Each IH unit output signal of the multi-stage delay device 25 is supplied to a changeover switch 26 together with a non-delayed signal.

The changeover switch 26 performs a switching operation in response to a vertical motion vector signal supplied from an input terminal 27, and performs vertical motion vector correction by selecting a delay time.

The output signal of the changeover switch 26 is supplied to a shift register 28.

The shift register 28 has a plurality of output terminals in pixel units (32,4 MH+data rate), and output signals obtained from each output terminal are supplied to the changeover switches 29, respectively.

The changeover switch 29 performs a switching operation in response to a horizontal motion vector signal supplied from an input terminal 30, and performs horizontal motion vector correction by selecting a delay time.

As a result, the motion vector corrected signal is transmitted to the output terminal 3.
Noise reducer circuit 4 obtained from 1 and shown in FIG.
and is supplied to the input terminal 6b of the changeover switch 6.

When motion vector processing is not performed (the motion vector signal is in the 0 state), the total delay time from the input terminal 23 to the output terminal 31 in FIG. 9 is set to be exactly one frame.

Now, here, the interfield interpolation circuit 12 in FIG.
I will explain about it.

FIG. 10 is a block diagram showing the internal configuration of the interfield interpolation circuit, and FIG. 11 is a diagram for explaining interfield interpolation, which will be explained together.

In FIG. 10, the output signal of the sampling frequency conversion circuit 11 of FIG. It is also supplied to

The 1-field delay device 35 outputs 5628 (H
(horizontal period), and the output signal is supplied to an IH delay device 36 and an adder 37.

The IH delayer 36 further delays the signal delayed by 562H, which is the output signal of the 1-field delayer 35, by 562H.
A signal delayed by 63H is output.

The adder 37 adds the input signal and the output signal of the delay device 36 (1), that is, the 562H delayed signal and the 563H delayed signal, and supplies the result to the coefficient unit 38.

The coefficient multiplier 38 multiplies the input signal by 1/2 and supplies it to the inter-field motion vector correction circuit 39.

As shown in FIG. 11, scanning line A 562H before and scanning line B 563H before in field n3, one field before, are averaged and interpolated into scanning line C of current field n4. It is something that will be done.

Points A, B, and C shown in FIG. 10 correspond to the scanning line phases of A, B, and C in FIG. 11.

The inter-field motion vector correction circuit 39 includes a multi-stage variable delay line, is controlled by the inter-field motion vector signal M2 input from the control terminal 40, and performs inter-field motion vector correction.

In inter-field motion vector correction, as shown in FIG. 11, the movement of n3 images one field before is corrected to match the image phase of the current field n4.

The output signal of the inter-field motion vector correction circuit 39 is
It is supplied to the terminal 33b of the changeover switch 33.

The changeover switch 33 converts the signal from the input terminal 32 supplied to its terminal 33a and the output signal of the interfield motion vector correction circuit 39 supplied to its terminal 33b to the interfield motion vector correction circuit 39 supplied to its control terminal 41. Inter-field sub-sample clock S2 (
Switching is controlled by 24,3MH+:).

Through the above interframe and interfield motion vector processing, the image phase interpolated between four fields matches the current field signal phase, and is processed in a high band in a still area.

(Problem to be Solved by the Invention) However, in the decoding processing configuration of the conventional example, the motion detection circuit 22 makes a motion detection error (or insufficient detection) on the same screen, and If a part to be processed by the image processing system and a part to be processed by the video system when the video signal has been completely detected occur at the same time, the video signal to be processed will move in the same direction, especially if the speed of movement varies, and the video processing system will This caused a speed fluctuation phase difference.

In some cases, objects moving in the same direction may appear to flicker, as if they are moving in opposite directions, which is an unnatural phenomenon that visually appears to be inconsistent movement.

If the function of the motion detection circuit on the receiver (decoder) side is perfect, that is, if it matches the motion detection circuit on the transmitter (encoder) side, the unnatural phenomenon due to the speed fluctuation phase difference will not occur.

However, since the signals on the receiver (decoder) side are offset between frames, it is not possible to detect motion between complete frames as is done on the transmitter (encoder) side. It is extremely difficult to eliminate the adverse effects caused by phase difference.

FIG. 12 is a diagram showing the time axis phase difference between the still image system and the moving image system when a motion detection error occurs.

n1 to n4 represent field numbers, where n4 is the current field, n3 is one field before, and n2 is two fields (one frame) before.

In FIG. 12(A), as mentioned above, in the still image system, inter-frame and inter-field interpolation processing is performed over four fields (4V) from n1 to n4, and four images from n1 to n4 are superimposed. ing.

Therefore, the center phase of the still image system is determined by fields n2 and n3.
exists in the middle.

On the other hand, the intra-field interpolation phase for the moving image is in the current field n4.

Therefore, as is clear from FIG. 12(A), the phase difference between the center phase of the still image system and the phase of the moving image system is 1.5 fields (1.5V), and the maximum phase difference is 3 fields (3V).
■).

This phase difference is the cause of the speed fluctuation phase difference of the moving image signal, and is the first problem to be solved.

In order to solve this problem, it is thought that if the moving image system is delayed by one field, the speed fluctuation phase difference will be minimized to 0.5 field.

However, when the screen moves in parallel, motion vector correction is applied as described above, and as shown in FIG. Matches the image phase of the field.

Furthermore, similarly between fields, the motion vector of the image one field before is corrected to the image phase of the current field as shown by the arrow.

Therefore, the still image phase during motion vector correction is the current field n4, and if the moving image processing is delayed by one field, the time axis phase difference becomes one field, and the speed fluctuation phase difference remains.

Also, at this time, the image causes discontinuous movement, and the first
problem cannot be solved easily.

Next, in order to solve or alleviate the first problem, low-frequency adjustment processing has been performed. However, the low frequency adjustment process had the following problems.

The low frequency switching circuit 17 converts all of the low frequency band from 0 to 4 MHz to the output signal of the de-emphasis circuit 3 (
If you change the amount (100%), you can obtain the highest vertical resolution, but on the other hand, the output signal of the de-emphasis circuit 3 is a signal that has not passed through the noise reducer circuit 4, and interpolation processing between frames and fields is required. Since the signal is not subjected to any processing, a problem arises in that the S/N ratio (signal-to-noise ratio) deteriorates.

In order to improve the S/N ratio, if the amount of shift is reduced, the vertical resolution becomes insufficient, making it difficult to achieve both the S/N ratio and the vertical resolution. This is the second problem to be solved.

The present invention has been made with attention to the above points, and it performs motion vector correction so that the image phase of the current field signal matches the image phase of one field before. Processing is performed using the signal before the field, and the time axis phases of the still image system and video system are made to match, thereby minimizing the phase difference with the center phase of the time axis in the event that the video signal is incorrectly processed in the still image system. This is a configuration that eliminates low-frequency adjustment processing, which solves the unnaturalness in motion adaptive processing with a simple circuit configuration, and also allows two-way interpolation between fields without performing low-frequency adjustment processing as in the past. Since we are using a dimensional filter to improve the vertical resolution,
It is an object of the present invention to provide a high-definition television receiver that can solve the problem of deterioration of the SN ratio (signal-to-noise ratio) of an output signal.

(Means for Solving the Problems) In order to achieve the above object, a motion compensation system that performs band compression by offset sampling between fields and frames, and that is equipped with a motion vector signal for motion compensation and sample point phase information. A high-definition television receiver that receives and demodulates sub-sampled transmission signals includes a motion detection circuit that detects motion components of images, and a motion vector correction circuit that applies motion vector correction to image components that span between m (m is a positive integer) fields. A still image processing circuit that performs interpolation, a moving image processing circuit that performs intrafield interpolation processing on one field signal component, and mixing processing of the output signal of the still image processing circuit and the output signal of the moving image processing circuit. and a mixer whose mixing ratio is controlled by the output signal of the motion detection circuit,
To provide a high-definition television receiver characterized by inputting an image component of /2-1 field before to a moving image processing circuit and applying motion vector correction to the image phase of m/2-1 field before. It is something.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of a high-definition television receiver of the present invention. The same parts as in FIG. 7 are shown with the same reference numerals.

The difference from the conventional example shown in FIG. 7 is that the interframe interpolation circuit 4
3 and the internal configuration of the still image processing circuit extender 44 has been changed from the conventional example, the low frequency switching circuit 17 in the conventional example has been deleted, the 1-field delay device 47, 4.8, and the inter-frame sub-sampling control. The difference is that a circuit 53 is provided so that the interpolation phase of the intra-field interpolation circuit 13 and the inter-field interpolation filter 52 is controlled by a sub-sample clock whose phase is delayed by one field.The following are the main differences. Explain the operation.

As explained in the conventional example, in the still image processing circuit, image components spanning between m (m is a positive integer) fields are subjected to motion vector correction and interpolated.

The principle of the present invention is to perform video processing on a signal m/2-1 field before, and when the motion vector correction is applied, motion vector correction is performed in the opposite direction to the motion vector correction between fields. This is to make the phases of the moving image system and the still image system coincide with the image phase of m/2-1 fields before.

The case where m=4, that is, the case where the image phase is made to match the image phase of m/2-1=1 field before will be described below.

In the present invention, one-field delayers 45 and 5 delay the conventional one-frame delayer 7 shown in FIG. 7 by 563H.
The signal is divided into 1-field delayers 46 that delay by 62H, and motion vector correction between frames is performed by the 1-field delayers 46.

This one-field delayer 46 has the configuration of the multi-stage variable delay line shown in FIG. 9, and delays by exactly 562H when motion vector correction is not performed.

The moving image processing circuit 9 is configured to receive the output signal of the one-field delay device 45 within the field.

The interpolation phase within a field is determined by converting the interframe sub-sampled control signal output to the terminal 19b of the control signal separation circuit 19 into one field using the one-field delayer 47.
The field-delayed signal is input to the inter-frame sub-sampling control circuit 53, and controlled by the inter-field sub-sampling clock S3 obtained by controlling the 16.2 MH2 clock with this signal.

The still image processing circuit 44 also processes the current field signal interpolated between frames by the changeover switch 6, and the above-mentioned one.
The signal of one field before the output of the field delay device 45 is similarly processed by low-pass filters 10 and 49 in both systems.
Attenuate 2MHx or more, and then use the sampling frequency conversion circuits 11 and 50 to attenuate 24.3MHx! Convert to rate,
Interfield interpolation is performed by an interfield interpolation circuit 51.

Furthermore, the interfield interpolation circuit 51 includes an IH delay device 36, an adder 37, and a coefficient multiplier 38 that multiplies the output of the adder by 1/2.
, an interfield inverse vector correction circuit 42 , and an interfield interpolation filter 52 .

The still image interfield interpolation filter 52 performs interfield subsample control on a signal obtained by delaying the interfield subsample control signal outputted to the terminal 19c of the control signal separation circuit 19 by one field using the one field delayer 48. input to circuit 21, and with this signal 2
The interpolation phase is controlled by the interfield subsample clock S4 obtained by controlling the 4.3MHx clock.

That is, the interpolation phase is controlled by the interfield subsample clock S4 having a phase one field earlier.

FIG. 2 is a diagram for explaining inter-field interpolation of the present invention.

As shown in the interfield interpolation circuit 51 in FIG.
Points E and F are shown in Figure 2.

This corresponds to each scanning line phase of E and F.

Interpolation between fields of the present invention is performed by adding and averaging the current field signal and H scanning lines, applying motion compensation to the image phase of the previous field by the interfield inverse vector correction circuit 42, and filtering the interfield interpolation filter. Interpolated at 52.

In the present invention, the motion vector of the current field is corrected to match the phase of the image one field before. This is the opposite direction to the conventional motion correction between fields.
The inter-field inverse vector correction circuit 42 is configured to invert the sign of the inter-field motion vector signal to control the multi-stage variable delay line.

FIG. 3 is a diagram showing the internal configuration of the interfield inverse vector correction circuit. This operates as a multi-stage variable delay line.

In FIG. 3, from the input terminal 54, the output signal of the coefficient multiplier 38 in FIG.
A previous frame signal and a current field signal are input and supplied to a shift register 55.

The shift register 55 receives an input signal of 24.3MH! Delayed in rate units, multiple output terminals QO to Qn in pixel units
output signals are supplied to the changeover switches 56, respectively.

The changeover switch 56 performs a switching operation using a signal in which the sign of the inter-field motion vector signal supplied from the input terminal 57 is inverted by the sign inverter 58, and performs inter-field motion vector correction by selecting a delay time. ing.

The changeover switch 56 is controlled by the inter-field motion vector signal, but in the present invention, the sign is inverted by the sign inverter 3, so when the inter-field motion vector signal has the largest value, the shift with the minimum amount of delay is performed. Select register output.

As a result, the motion vector corrected signal is transmitted to the output terminal 5.
9 and is supplied to the interfield interpolation filter 52 in FIG.

FIG. 4 is a diagram showing the time axis phase during motion vector correction according to the present invention.

In the conventional motion vector correction shown in FIG. 12(B), the phase is matched to the image of the current field n4, whereas in FIG. 4, the image of the previous field n3 is used as the reference. , the image of the current field n4 is subjected to motion vector correction in the negative direction.

Therefore, the direction of motion vector correction according to the present invention is opposite to that of the conventional example.

In FIG. 4, arrows indicate the direction of motion vector correction, n1 to n4 are field numbers, and n4 is the current field.

The phase of the moving image system in which the output signal of the one-field delayer 45 is interpolated within the field is the n3 field one field before.

The phase of the still image system at the time of motion vector is determined by inter-frame interpolation from nl to n3, motion vector correction in the positive direction from n2 to n4, and then inter-frame interpolation to n4.
is inter-field interpolated into n3, so the phase matches the n3 field one field before.

Therefore, the phase difference between the phase when motion detection is insufficient and the motion signal is processed in the still image system, and the phase of the still image system at the time of moving images and motion vectors is 0°5 field difference and the minimum phase difference. become.

As explained above, the high-definition television receiver of the present invention shown in FIG. Even if video signals are mistakenly processed in the still image system, the phase difference between the still image system and the video system can be minimized.
This solves the first problem.

Figure 5 shows 2 of the interfield interpolation filter in Figure 1.
FIG. 3 is a diagram showing dimensional frequency characteristics.

The interfield interpolation filter 52 shown in FIG. 1 of the present invention is a two-dimensional interpolation filter, and has a vertical orientation.

Since it consists of three scanning lines at points E and F, it has characteristics close to the band shown in FIG.

Further, by increasing the number of vertical and horizontal taps of this interpolation filter and realizing filter characteristics as shown in FIG. 5, aliasing can be further suppressed and high-band interfield interpolation can be realized.

Therefore, by converting the interfield interpolation into a two-dimensional interpolation filter, the low frequency replacement process becomes unnecessary, and the second
problems can be solved.

Also, the above explanation is based on the case of m=4, and an example was explained in which the image phase is matched to the previous field, but for - boat fishing, it is sufficient to match the image phase to the previous m/2-1 field. Of course.

(Effects of the Invention) The high-definition television receiver of the present invention has the above-described configuration, and performs motion vector correction so that the image phase of the current field signal matches the image phase of m/2 fields before. In addition, the video signal is processed using a signal m/'2 fields earlier, and the time axis phases of the still image system and the video system are made to match, thereby preventing the video signal from being erroneously processed in the still image system. This configuration minimizes the phase difference with the center phase of the time axis when Since vertical resolution is improved by using a two-dimensional filter for interfield interpolation without performing low-frequency replacement processing, the output signal S
It has excellent practical effects such as being able to solve the problem of deterioration of the N ratio (signal-to-noise ratio).

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the high-definition television receiver of the present invention, FIG. 2 is a diagram for explaining interfield interpolation of the present invention, and FIG. 3 is a diagram of an interfield inverse vector correction circuit. FIG. 4 is a diagram showing the internal configuration, FIG. 4 is a diagram showing the time axis phase during motion vector correction of the present invention, FIG. 5 is a diagram showing the two-dimensional frequency characteristics of the interfield interpolation filter in FIG. 1, and FIG. is a diagram showing the frequency spectrum characteristics of the MUSE signal, FIG. 7 is a diagram showing a conventional high-definition television receiver, and FIG. 8 is a two-dimensional frequency characteristic of the interfield interpolation filter in FIG. 7. 9 is a block diagram showing the internal configuration of the 1-frame delay device in FIG. 7, FIG. 10 is a block diagram showing the internal configuration of the interfield interpolation circuit, and FIG. 11 explains interfield interpolation. FIG. 12 is a diagram showing the time axis phase during motion vector correction. 1.23, 27, 30.32, 54.57... Input terminal, 2... AD converter, 3... De-emphasis circuit, 4... Noise reducer circuit, 5.43... Between frames Interpolation circuit, 6.26, 29.33.56... changeover switch, 7... 1 frame delay device, 844...
-Still image processing circuit, 9...Moving picture processing circuit, 10.
49...Low pass filter, 11,14°50...
Sampling frequency conversion circuit, 1.2.51... Inter-field interpolation circuit, 13... Intra-field interpolation circuit,
15...Mixer, 17...Low frequency switching circuit, 18.
31.34.59... Output terminal, 19... Control signal separation circuit, 20.53... Inter frame sub sample control circuit, 21... Inter field sub sample control circuit, 22... Motion detection Circuit, 24...Fixed delay device, 25...Multi-stage delay device, 28.55...Shift register, 35, 45, 46, 47.48...1 field delay device, 36...IH delay 37...Adder, 38...Coefficient unit, 39...Inter-field motion vector correction circuit, 40.41...Control terminal, 42...
- Inter-field inverse vector correction circuit, 52... Inter-field interpolation filter, 58... Sign inverter, Md...
・Motion detection signal, Ml, M2...Motion vector signal,
Sl, S3... interframe subsample clock, S
2. S4...Inter-field subsample clock, n
1 to n4...Field number. e+藺Figure 2 Patent Applicant Representative of Victor Japan Co., Ltd.

Claims (1)

[Claims:] A high-definition television that receives and demodulates a motion-compensated sub-sampled transmission signal that has been band-compressed by offset sampling between fields and frames, and that includes a motion vector signal for motion compensation and sample point phase information. In the John receiver, a motion detection circuit detects a motion component of an image, a still image processing circuit performs motion vector correction and interpolates image components spanning between m (m is a positive integer) fields, and 1 field. A video processing circuit that performs intra-field interpolation processing on signal components, mixes the output signal of the still image processing circuit and the output signal of the video processing circuit, and outputs the mixing ratio of the motion detection circuit. It is configured with a mixer controlled by a signal, inputs the image component of m/2-1 field before to the moving image processing circuit, and performs motion vector correction to the image phase of m/2-1 field before. A high-definition television receiver that is characterized by the ability to