JPH0888838A - Television receiver - Google Patents

Abstract

PURPOSE: To flexibly cope with the combination of memory sharing by providing a tristate function in the respective output terminals of plural signal processing circuits and alternatively selecting signals to be inputted to a memory. CONSTITUTION: In the case of processing the television signals of a first broadcasting system, selection signals S1 added to an input terminal 4 attain a state where only the signal line of the output terminal 11 is equivalently connected to a memory block 14 by turning only the output terminal 11 to a passing state and turning the output terminal 12 and 13 to a high impedance state. The television signals of the first broadcast system added to the input terminal 1 are converted into digital signals in an A/D converter 5, the converted digital television signals are decoded in a first signal processing circuit block 8 and converted into analog signals again by a D/A converter 15 and first video signals are obtained from the output terminal 18. In this case, by switching input signals to the memory block, a picture memory can be shared.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiver capable of receiving television signals of a plurality of broadcasting systems.

[0002]

2. Description of the Related Art In recent television techniques, digital signal processing techniques such as compression / decompression of television signals using a large-capacity image memory have become common. However, television broadcasting systems vary depending on the region and frequency band, and the image memory is used differently depending on the signal processing system. Generally, a television receiver supporting a plurality of broadcasting systems must have an image memory for each signal processing circuit corresponding to each broadcasting system.
The increase in the amount of image memory has led to a significant increase in product cost. Therefore, it is considered that in a television receiver capable of receiving a plurality of broadcasting systems, an image memory is shared between signal processing circuits corresponding to the respective broadcasting systems.

A conventional television receiver is disclosed in, for example, Japanese Patent Application Laid-Open No. 62-206977.

FIG. 11 is a block diagram of this conventional television receiver. In this conventional example, the MUSE system (Ninomiya et al., "High-Definition Television Satellite 1" is a band compression system for high-definition television signals. Channel transmission system (M
Technical Report TEBS95-2
(Pp. 37-42) and an NTSC system which is a broadcasting system of the current standard television signal, a television receiver capable of receiving two types of television signals.

In FIG. 11, 101 is a baseband M.
USE signal input terminal, 102 is baseband NTS
C signal input terminal, 103 MUSE / NTSC switching selection signal M / N input terminal, 104 and 105 A / D converters for converting MUSE and NTSC signals into digital signals respectively, and 106 selection signal M Selector circuit for selectively outputting the MUSE / NTSC signal according to / N,
107 and 108 are image memories, 109 is a selector circuit that alternately outputs the input signals and the signals delayed by one frame period in the image memories 107 and 108 for each pixel, and performs inter-frame interpolation processing. Timing generation circuit for generating timing signal for MUSE, 111 is NT
A timing generation circuit for generating a timing signal for SC, and 112 for MUSE according to the selection signal M / N.
A selector circuit for selectively outputting the timing signal from the timing generation circuit for NTSC, 113 is a selector circuit 11
The image memory 10 according to the timing signal from 2
An address generator that generates an address for controlling the operations of 7 and 108, and 114 is a separation circuit that separates the current field signal multiplexed by inter-frame interpolation processing by the selector circuit 109 from the signal delayed for one frame period. circuit,
115 is a MUSE signal processing circuit for performing MUSE decoding processing, 116 is an NTSC signal processing circuit for performing NTSC decoding processing, 117 to 122 are D / A converters, 123 is a high-definition television display monitor, and 124 is a current standard. It is a display monitor for a television.

The operation of the conventional television receiver thus constructed will be described with reference to the drawings. In the figure, the MUSE signal is input to the terminal 101, and the signal converted into digital data by the A / D converter 104 is input to the selector 106. At the same time, the terminal 102
The SC signal is input, and the signal converted into digital data by the A / D converter 105 is input to the selector circuit 106. Also, the terminal 103 has a MUSE signal and NTSC
A signal M / N for switching signals is input, and the selector circuit 106 outputs the MUSE signal and the NTSC signal according to the signal M / N.
The signal is switched and output.

When the selector circuit 106 selects the MUSE signal, the selector circuit 112 selects the timing signal output from the MUSE timing generation circuit 110 according to the signal M / N. The address generation circuit 113 generates an address signal suitable for the MUSE signal according to the timing signal from the selector circuit 112, and controls the image memories 107 and 108. Therefore, the operation of the image memories 107 and 108 in this case is MUSE.
The selector circuit 109 functions as a delayer for one frame period of the signal, and the selector circuit 109 receives the input MUSE signal and one frame delay MUS.
Interframe interpolation processing is performed by switching and outputting the E signal at a rate double the sample rate. The MUSE signal processing circuit 115 performs subsequent decoding processing of the MUSE signal on the signal subjected to interframe interpolation processing, and outputs digital data of the decoded RGB video signal. Each digital data is D / A converter 1
The signals are converted into analog signals by 17, 118, and 119 and input to the monitor 123.

On the other hand, when the selector circuit 106 selects the NTSC signal, the selector 112 selects the timing signal output from the NTSC timing generation circuit 111 according to the M / N signal. The address generator 113 generates an address signal suitable for the NTSC signal according to the timing signal from the selector circuit 112, and controls the image memories 107 and 108.

Therefore, in this case, the image memory 107,
The operation of 108 operates as a delayer for one frame period of the NTSC signal, and the selector circuit 109 switches between the input NTSC signal and the one-frame delayed NTSC signal at the double rate of the sample rate and outputs the same, thereby performing interframe interpolation processing of MUSE. Similarly, the NTSC signal of the current field and the NTSC signal delayed by one frame period are multiplexed for each pixel. The separation circuit 114 separates the NTSC signal multiplexed by the selector circuit 106 into a signal delayed by one frame period from the current field. The NTSC signal processing circuit 116 uses the signal of the current field from the separation circuit 114 and the signal delayed by one frame period for the subsequent NTSC.
Each decoding process of the signal is performed, and each digital data of the RGB video signal after decoding is output. Each digital data is converted into an analog signal by the D / A converters 120, 121, 122 and input to the monitor 124.

[0010]

However, the above-mentioned configuration is for memory sharing between limited processes between the two systems, and for sharing among many signal processing circuit blocks of three or more systems, There has been a problem that a large number of multi-stage selector circuits are required in order to support memory sharing in each of the space-time processing circuit units in the signal processing circuit block.
Further, in the above-mentioned configuration, the signal processing circuit other than the selected broadcasting system does not operate normally, so that there is a problem that only the image of one of the broadcasting systems can always be enjoyed. Further, in the above-mentioned configuration, although there is only one signal processing circuit block that is effectively operating, there is a problem that power consumption of two signal processing circuit blocks is consumed.

In view of the above problems, the first invention is a television that is compatible with a plurality of broadcasting systems, and shares a part or all of the memory among the signal processing circuits corresponding to the respective broadcasting systems to reduce the cost. The purpose is to provide a John receiver.

In view of the above point, a second object of the present invention is to provide a television receiver which can simultaneously enjoy an image other than the broadcasting system in which the decoding process is performed by preferentially using the shared memory.

In view of the above point, a third aspect of the present invention has an object of providing a television receiver compatible with a plurality of systems which suppresses unnecessary power consumption.

[0014]

A first invention comprises a plurality of signal processing circuit blocks and at least one memory block, and an input terminal of the memory block has signals from the plurality of signal processing circuit blocks. The lines are commonly connected, and the plurality of signal processing circuit blocks have a tri-state function at an output terminal that supplies a signal to the memory block, and all of the signal processing circuit blocks except the output terminal selected according to the selection signal are in a high impedance state. The television receiver is characterized in that the input signal to the memory block is selectively selected by the above.

In a second aspect of the present invention, each of the plurality of signal processing circuit blocks uses a spatial signal processing circuit for performing processing using only signals in the same field of the incoming input signal and signals for a plurality of fields. And a spatiotemporal signal processing circuit for performing processing, wherein signal processing using no output from the spatiotemporal signal processing circuit when signals for a plurality of fields cannot be obtained in the spatiotemporal signal processing circuit according to the selection signal It is a television receiver characterized by having a form.

A third aspect of the invention is a television receiver characterized in that each of the plurality of signal processing circuit blocks can stop the driving clock of all or part of the blocks according to the selection signal.

[0017]

According to the first aspect of the present invention, the output terminals of the plurality of signal processing circuits commonly connected to the inputs of the memories have the tristate function according to the above-described configuration, and the elements other than those selected by the selection signal are set to the high impedance state. The signals to be input to the memory are selectively selected, and the memory can be shared by the signal processing circuits by switching the selection signals.

According to the second aspect of the invention, in addition to the operation of the first aspect of the invention, when each signal processing circuit is in a state in which the memory cannot be used according to the selection signal, the spatial processing does not require the memory. Switching to perform signal decoding processing, it is possible to simultaneously perform a plurality of video signal processing even in the memory sharing state.

According to the third aspect of the invention, in addition to the operation of the second aspect of the invention, each signal processing circuit can stop the drive clock when not selected by the selection signal to suppress unnecessary power consumption. it can.

[0020]

1 is a block diagram of a television receiver according to an embodiment of the first invention. In FIG. 1, 1 is an input terminal for inputting a television signal of the first broadcasting system, 2 is an input terminal for inputting a television signal of the second broadcasting system, and 3 is a television signal of the third broadcasting system. An input terminal for inputting, 4 is an input terminal for the selection signal S1,
5 to 7 are A / D converters, 8 is a first signal processing circuit block which performs signal processing corresponding to the first broadcasting system, and 9 is a second
Second signal processing circuit block for performing signal processing corresponding to the broadcasting system of No. 10, 10 is a third signal processing circuit block for performing signal processing corresponding to the third broadcasting system, and 14 is space-time in video signal processing. A memory block having a plurality of image memories required for processing and time axis conversion processing, and 11, 12, and 13 respectively control output of signals supplied from the first, second, and third signal processing circuit blocks to the memory block 14. Signal S
Tri-state output terminal that switches between passing and high impedance state according to 1. 15 to 17 is D
/ A converter, 18 is an output terminal for outputting a decoded signal of a television signal of the first broadcasting system, 19 is an output terminal for outputting a decoded signal of a television signal of the second broadcasting system, 2
Reference numeral 0 is an output terminal for outputting a decoded signal of a television signal of the third broadcasting system.

The operation of the television receiver of this embodiment constructed as described above will be described below. The operation will be described separately for the case where the television signal to be decoded is the first broadcasting system, the second broadcasting system, and the third broadcasting system.

First, when processing a television signal of the first broadcasting system, the selection signal S1 applied to the input terminal 4 passes only the output terminal 11, and the output terminals 12 and 13 are passed.
Is placed in a high impedance state so that only the signal line of the output terminal 11 is equivalently connected to the memory block 14. The television signal of the first broadcasting system applied to the input terminal 1 is converted into a digital signal by the A / D converter 5, and the converted digital television signal is decoded by the first signal processing circuit block 8. , D / A converter 15 converts the analog signal again to obtain a first video signal from the output terminal 18.

When processing the television signal of the second broadcasting system, the selection signal S1 applied to the input terminal 4 is passed through only the output terminal 12 and the output terminals 11 and 13 are set in the high impedance state. Equivalently, only the signal line of the output terminal 12 is connected to the memory block 14. The television signal of the second broadcasting system applied to the input terminal 2 is converted into a digital signal by the A / D converter 6, and the converted digital television signal is decoded by the second signal processing circuit block 9. , D
Is again converted into an analog signal by the / A converter 16,
The second video signal is obtained from the output terminal 19.

In the case of processing the television signal of the third broadcasting system, the selection signal S1 applied to the input terminal 4 is made to pass only the output terminal 13 and the output terminals 11 and 12 are set to the high impedance state. Equivalently, only the signal line of the output terminal 13 is connected to the memory block 14. The television signal of the third broadcasting system applied to the input terminal 3 is converted into a digital signal in the A / D converter 7, and the converted digital television signal is the signal in the third signal processing circuit block 10. It is decoded, converted again into an analog signal by the D / A converter 17, and a third video signal is obtained from the output terminal 20.

As described above, according to this embodiment, when the signal processing circuit blocks corresponding to a plurality of broadcasting systems share the image memory, the signal processing circuit blocks output signals to the memory blocks. By providing the terminal with a tri-state function and switching the input signal to the memory block by controlling the tri-state state of each output terminal, the input signal to the image memory is switched by the selection means such as the conventional selector. In comparison, the image memory can be shared by the three signal processing circuit blocks without adding a new selector.

Although the output terminal for supplying a signal to the memory block is provided with the tri-state function in this embodiment, any function may be used as long as it has a function of bringing the output terminal into a high impedance state in accordance with the control signal. Needless to say. Further, in this embodiment, an example in which the memory block is shared by the three signal processing circuit blocks to the memory block has been shown, but the number of signal processing circuit blocks may be any number of two or more. It goes without saying that the invention shown in FIG. Further, in this embodiment, the example in which each signal processing circuit block has one input / output signal to / from the memory block has been shown, but the number of input / output signals may be any number of one or more, and in this case also. It goes without saying that the invention shown in the embodiment will be more effective.

FIG. 2 is a block diagram of a television receiver according to an embodiment of the second invention. In FIG. 2, reference numeral 21 is an input terminal for the MUSE signal, and 22 is an NTSC.
Input terminal of signal, 23 is input terminal of selection signal M / N, 2
4, 25 are A / D converters, 26 are MUSE signal processing blocks for decoding MUSE signals, 27 are NTSC signal processing circuit blocks for decoding NTSC signals, 14 are memory blocks, and 29 and 30 are 16.2 MHz samples, respectively. Image memory having a capacity (about 4 Mbits) capable of storing a rate MUSE signal or an NTSC signal having a sample rate of 14.3 MHz for one frame period, and 31 and 32 each capable of storing the same signal for one field period (about 2
An image memory having M bits), 33 is a screen synthesizing circuit for synthesizing the output video signal of the MUSE signal processing block 26 and the output video signal of the NTSC signal processing block 27 into one screen, and 34 and 35 are D / A converters. , 36 are output terminals for recording the decoded signal of the MUSE signal, and 37 is a monitor.

FIG. 3 is a block diagram showing a configuration example of the MUSE signal processing block 26. In FIG. 3, 41 is a moving image processing circuit, 42 is a still image processing circuit, 43 is a motion detection circuit, 44 is a mixing circuit, 45 is a selector, and 46 is MUSE.
A signal decoding circuit, 47 a scanning line number converting circuit for converting a MUSE signal into a recording signal, 48 a spatiotemporal filter, 49
Is a selector, 50 is a decoding circuit for a recording signal converted from the MUSE signal by the scanning line number converting circuit 47, and 51 to 54 are output terminals having a tri-state function. In FIG. 3, the still image processing circuit 42, the spatiotemporal filter 48, and the like are a spatiotemporal processing circuit, and the moving image processing circuit 41 is a spatial processing circuit. Further, A to L in FIG. 3 are A to L in FIG.
It shows that it is the same point as.

FIG. 4 is a block diagram showing a configuration example of the NTSC signal processing block 27. In FIG. 4, 61 is a Y / C separation circuit for still images, 62 is a Y / C separation circuit for moving images,
63 is a motion detection circuit, 64 and 70 are mixing circuits, and 65 and 7
1 is a selector, 66 is a subtracter, 67 is a still image scanning line interpolation circuit, 68 is a moving image scanning line interpolation circuit, 69 is a color signal scanning line interpolation circuit, 72 is a progressive scanning NTSC signal decoding circuit, 73 , 74 are output terminals having a tri-state function. In FIG. 4, the still image YC separation circuit 61 and the still image scanning line interpolation circuit 67 are space-time processing circuits, and the moving image YC separation circuit 62 and the moving image scanning line interpolation circuit 68 are spatial processing circuits. Further, M to T in FIG. 4 indicate the same points as M to T in FIG.

The operation of the television receiver of this embodiment constructed as above will be described below.

The MUSE signal applied to the input terminal 21 is converted into a digital signal by the A / D converter 24 and M
It is input to the USE signal processing block 26. Input terminal 2
The NTSC signal added to 2 is converted into a digital signal in the A / D converter 25 and input to the NTSC signal processing block 27.

The following description of the operation is mainly divided into the case where the signal to be decoded is the MUSE signal and the case where the signal is the NTSC signal.

First, when mainly decoding the MUSE signal, the selection signal M / N applied to the input terminal 23 becomes a value for selecting MUSE, and the MUSE signal processing block 26 and NTS.
It is input to the C signal processing block 27. In the MUSE signal processing block 26, when the selection signal M / N selects MUSE, the output end C of the tristate output terminal 51 is an input of the image memory 29, the output end F of 52 is an input of the image memory 31, and 53 The output terminals H of the above are respectively connected to the inputs of the image memory 32. On the other hand, the tri-state output terminal 54 is in a high impedance state, and the output end I is insulated from the image memory 32. The interframe interpolating circuit 421 interpolates the input MUSE signal and the one-frame period delayed signal output from the output end C of the input signal through the image memory 29 and the input end D of the interframe interpolating circuit 421. 422.

In the inter-field interpolation circuit 422, the signal subjected to the inter-frame interpolation processing and the same signal are passed through a path of output terminal F-image memory 31-input terminal G-output terminal H-image memory 32-input terminal J. Interpolation processing is performed with the obtained 1-field period delayed signal to restore the image of the still image area of the MUSE signal. The field interpolation circuit 411 performs interpolation processing using only the current signal to restore the video of the moving image area of the MUSE signal. The motion detection circuit 43 receives the current signal, the 1-frame delay signal obtained from the input terminal D, and the 2-frame delay signal obtained from the input terminal E via the image memory 30, and based on these signals, the 1-frame delay signal and the 1-frame delay signal are input. The amount of movement between two frames is detected. The mixing circuit 44 mixes the inputs from the moving image processing circuit 41 and the still image processing circuit 42 at a ratio according to the amount of motion from the motion detection circuit 43 and outputs the mixed result.

In the selector 45, the selection signal M / N is MUS.
When E is selected, S3 which is a motion adaptive processing output is selected and output. In the decoding circuit 46, the subsequent MUS
Each decoding process of E is performed to obtain a decoded output of the MUSE signal as RGB digital data. Scanning line number conversion circuit 47
Then, in order to obtain a video signal which can be recorded in the current NTSC-VCR, the number of scanning lines of the MUSE signal is converted. When the selection signal M / N selects MUSE, the selector 49 selects S4 which is the output of the scanning line number conversion circuit 47 and outputs it. At this time, the space-time filter circuit 48
Does not affect the flow of the signal processing system. Decoding circuit 50
Then, each of the following decoding processes is performed on the output of the selector 49 to obtain an output for recording as YC digital data.

In this way, when the selection signal M / N selects MUSE, the MUSE signal processing block 26 performs the motion adaptive spatiotemporal processing which is the original MUSE signal processing and does not obtain the output for recording. On the contrary, it operates so as not to perform spatiotemporal processing.

In the NTSC signal processing block 27, when the selection signal M / N selects MUSE, the tri-state output terminals 73 and 74 are both in a high impedance state and are insulated from the image memory. The inter-line YC separation circuit 621 performs YC separation using only the current signal of the input NTSC signal. The selector 65 selects YC between lines when the selection signal M / N selects MUSE.
The output S7 of the separation circuit 621 is selected and output. At this time, the inter-frame YC separation circuit 611 and the motion detection circuit 6
3. The mixing circuit 64 does not affect the flow of the signal processing system. The color signal separated by the inter-line YC separation circuit 621 is passed through a selector 65 and a subtractor 66 and a color signal interpolation circuit 69.
Is supplied to.

The subtractor 66 subtracts the color signal from the input NTSC signal to obtain the luminance signal. The inter-line interpolation circuit 681 performs scanning line interpolation using only the current signal of the input luminance signal. The selection signal M / N of the selector 71 is MU.
When SE is selected, the output S9 of the interline interpolation circuit 681 is selected and output. At this time, the inter-frame interpolation circuit 671, the motion detection circuit 63, and the mixing circuit 70 do not affect the flow of the signal processing system. The luminance signal from the selector 71 and the color signal interpolated by the scanning line in the color signal interpolating circuit 69 are supplied to the decoding circuit 72, and the subsequent decoding processing is performed to sequentially scan NT as RGB digital data.
Obtain the decoded output of the SC signal.

In this way, when the selection signal M / N selects MUSE, the NTSC signal processing block 27 does not perform the spatiotemporal processing but operates only the spatial processing to perform all the signal processing.

Next, when mainly decoding the NTSC signal, the selection signal M / N applied to the input terminal 23 becomes a value for selecting NTSC and the MUSE signal processing block 26 and NTS.
It is input to the C signal processing block 27. In the MUSE signal processing block 26, when the selection signal M / N selects NTSC, the tri-state output terminals 51, 52, 5
All 3 are in a high impedance state and are in a state of being insulated from the image memory. On the other hand, the output terminal I of the tri-state output terminal 54 is connected to the input of the image memory 32. In the field interpolation circuit 411, the input M
An image is restored by performing an interpolation process using only the current signal of the USE signal.

In the selector 45, the selection signal M / N is NTSC.
When is selected, the output S2 of the field interpolation circuit 411 is selected and output. At this time, the inter-frame interpolation circuit 421, the inter-field interpolation circuit 422, the motion detection circuit 43, and the mixing circuit 44 do not affect the flow of the signal processing system. MUS interpolated by the field interpolation circuit
The E signal is supplied to the decoding circuit 46 via the selector 45. The decoding circuit 46 performs each subsequent MUSE decoding process to obtain a decoded output of the MUSE signal as RGB digital data. In the scanning line number conversion circuit 47, the current NTSC-
In order to obtain a video signal that can be recorded in the VCR, the number of scanning lines of the MUSE signal is converted.

Since the input signal of the scanning line number conversion circuit is a signal obtained by restoring the MUSE signal only by the moving image processing, the region where the still image processing is originally supposed to contain a noise component in the space-time direction called aliasing distortion. Space-time filter circuit 48
Then, it works to reduce the aliasing distortion remaining in the output signal of the scanning line number conversion circuit. Selector 49 selects signal M / N
When NTSC is selected, the output signal S5 of the space-time filter circuit 48 is selected and supplied to the decoding circuit 50. The decoding circuit 50 performs each of the following decoding processes and obtains an output for recording as YC digital data.

When the selection signal M / N selects NTSC as described above, the MUSE signal processing block 26 restores the MUSE signal only by the field interpolation processing which is the spatial processing and obtains the output for recording. On the contrary, MUSE
It operates to perform spatiotemporal filtering to reduce aliasing distortion that occurs in the signal.

In the NTSC signal processing block 27, when the selection signal M / N selects NTSC, the output terminal O of the tristate output terminal 73 is the input of the image memory 29, and the output terminal R of 74 is the image memory 31. Will be connected to each input. Inter-frame YC separation circuit 6
In 11, YC separation processing is performed on the input NTSC signal and the 1-frame period delay signal output from the output terminal O and output from the input terminal P via the image memory 29. The YC separation circuit 621 between lines performs YC separation processing using only the current signal.

The motion detection circuit 63 receives the current signal, a 1-frame delay signal obtained from the input terminal P, and a 2-frame delay signal obtained from the input terminal Q via the image memory 30, and based on these signals, 1 The amount of motion between frames and between two frames is detected. The mixing circuit 64 mixes the inputs from the inter-frame YC separation circuit 611 and the inter-line YC separation circuit 621 at a ratio according to the motion amount from the motion detection circuit 63 and outputs the mixed result. When the selection signal M / N selects NTSC, the selector 65 selects S6 which is a normal motion adaptive three-dimensional YC separation output of NTSC signal processing and outputs it. The color signal separated by the motion adaptive three-dimensional YC separation processing is supplied to the subtractor 66 and the color signal interpolation circuit 69 via the selector 65.

The subtractor 66 subtracts the color signal from the input NTSC signal to obtain the luminance signal. The inter-field interpolation circuit 671 performs scanning line interpolation processing on the input luminance signal and the 1-field period delay signal output from the output terminal R and output from the input terminal S via the image memory 31. The inter-line interpolation circuit 681 performs scanning line interpolation using only the current signal of the input luminance signal. In the mixing circuit 70, the inter-field interpolation circuit 671 and the inter-line interpolation circuit 68
The inputs from 1 are mixed and output at a ratio according to the amount of motion from the motion detection circuit 63. The selector 71 selects the selection signal M /
When N is NTSC, S8 which is a normal motion adaptive scanning line interpolation output of NTSC signal processing is selected,
Output this. The luminance signal from the selector 71 and the color signal interpolated by the scanning line in the color signal interpolating circuit 69 are supplied to the decoding circuit 72, and the subsequent decoding processing is performed to decode the sequentially scanned NTSC signal as RGB digital data. Get the output.

In this way, when the selection signal M / N selects NTSC, the NTSC signal processing block 27 operates so as to perform the original motion adaptive spatiotemporal signal processing.

The video signal decoded in the MUSE signal processing block 26 and the video signal decoded in the NTSC signal processing block are both input to the screen synthesizing circuit 33. In the screen synthesizing circuit 33, for example, as shown in FIGS. 5 and 6, two video signals are synthesized to obtain one video signal output. In this case, it goes without saying that it is preferable that the video signal selected by the selection signal M / N is the main screen. The output video signal of the screen synthesis circuit 33 is D / A.
It is converted into an analog video signal by the converter 35 and supplied to the monitor. On the other hand, MUSE signal processing block 26
The recording output of is converted into an analog video signal by the D / A converter 34 and is supplied to the recording output terminal 36.

As described above, according to this embodiment, when the spatiotemporal signal processing circuit restricts the use of the image memory according to the selection signal, a spatial processing circuit which does not require a memory is provided as a signal processing path. By switching the path to pass, it is possible to enjoy the images of both the signal processing circuit block that mainly uses the image memory and the signal processing circuit block where the use of the image memory is restricted.

In this embodiment, when the space-time signal processing circuit restricts the use of the image memory according to the selection signal, the selectors 45, 65 and 70 are used to force the signal processing path to perform only the space processing. However, the mixing circuits 44, 64, and 70 may be configured to forcibly set the mixing ratio of the output of the spatial signal processing and the output of the spatiotemporal signal processing to 10: 0. Needless to say. Further, in this embodiment, the inter-frame interpolation circuit 4
21 performs inter-frame interpolation processing with the current signal and the 1-frame delayed signal obtained via the image memory 29. The cyclic configuration including the selector circuit 109 and the image memories 107 and 108 in the conventional example shown in FIG. It goes without saying that the inter-frame interpolation circuit may be used.

Further, in this embodiment, an example is shown in which the memory is shared by the MUSE signal processing block and the NTSC signal processing block, but even if the memory is shared between the signal processing circuit blocks corresponding to any two or more broadcasting systems. Not to mention good things. Further, in this embodiment, the MUSE interframe interpolation circuit 421 is used as a combination of memory sharing.
And NTSC YC separation circuit 611, MUSE
Inter-field interpolation circuit 422 and space-time filter 48,
Although the memories are shared among the inter-field interpolation circuits 671 of NTSC, it goes without saying that the memory is not limited to this combination.

FIG. 7 is a block diagram of a television receiver according to the first embodiment of the third invention. 7, 1 to 20 are the same as those of the first embodiment of the invention shown in FIG. Input terminals 81, 82, and 83 input clocks for driving the signal processing circuits to the first, second, and third signal processing circuit blocks, respectively. 84, 85,
Reference numeral 86 designates whether the clock signal supplied to each of the first, second, and third signal processing circuit blocks is passed according to the selection signal S1 or fixed to the "L" level A.
It is an ND circuit.

The operation of the television receiver of this embodiment constructed as above will be described below. The operation will be described separately for the case where the television signal to be decoded is the first broadcasting system, the second broadcasting system, and the third broadcasting system.

First, when processing the television signal of the first broadcasting system, the selection signal S1 applied to the input terminal 4 passes only the output terminal 11, and the output terminals 12 and 13 are passed.
Is placed in a high impedance state so that only the signal line of the output terminal 11 is equivalently connected to the memory block 14.

Further, S1 is AND circuits 84, 85, 86.
Of the clock signals input to the input terminals 81, 82, and 83 by setting only the signal input to 84 of the signals input to the "H" level and the signals input to 85 and 86 to the "L" level. , 81 of the clock signals are supplied to the first signal processing circuit block, and the clock signals of 82 and 83 are not supplied to the second and third signal processing circuit blocks, respectively. The television signal of the first broadcasting system applied to the input terminal 1 is converted into a digital signal by the A / D converter 5, and the converted digital television signal is decoded by the first signal processing circuit block 8. , D / A converter 15 converts the analog signal again to obtain a first video signal from the output terminal 18.

When processing the television signal of the second broadcasting system, the selection signal S1 applied to the input terminal 4 is passed through only the output terminal 12 and the output terminals 11 and 13 are set in the high impedance state. Equivalently, only the signal line of the output terminal 12 is connected to the memory block 14.

Further, S1 is AND circuits 84, 85, 86.
Of the clock signals input to the input terminals 81, 82, and 83 by setting only the signal input to 85 to the “H” level and the signals input to 84 and 86 to the “L” level. , 82 clock signals are supplied to the second signal processing circuit block, and 81 and 83 clock signals are not supplied to the first and third signal processing circuit blocks, respectively. The television signal of the second broadcasting system applied to the input terminal 2 is converted into a digital signal by the A / D converter 6, and the converted digital television signal is decoded by the second signal processing circuit block 9. , D / A converter 16 converts the analog signal again to obtain a second video signal from the output terminal 19.

In the case of processing the television signal of the third broadcasting system, the selection signal S1 applied to the input terminal 4 is made to pass only the output terminal 13 and the output terminals 11 and 12 are set to the high impedance state. Equivalently, only the signal line of the output terminal 13 is connected to the memory block 14.

Further, S1 is AND circuits 84, 85, 86.
Of the clock signals input to the input terminals 81, 82, and 83 by setting only the signal input to 86 to the “H” level and the signals input to 84 and 85 to the “L” level. , 83 clock signals are supplied to the third signal processing circuit block, and 81 and 82 clock signals are not supplied to the first and second signal processing circuit blocks, respectively. The television signal of the third broadcasting system applied to the input terminal 3 is converted into a digital signal in the A / D converter 7, and the converted digital television signal is a signal in the third signal processing circuit block 10
At the output terminal 20 and a third video signal is obtained from the output terminal 20.

As described above, according to this embodiment, the output terminals for supplying signals from the respective signal processing circuit blocks corresponding to a plurality of broadcasting systems to the memory block are provided with the tristate function, and the tristate function of each output terminal is provided. By controlling the state, it becomes possible to share the image memory by switching the input signal to the memory block,
By stopping the supply of the clock signal of the signal processing circuit block which is not selected by the selection signal S1 and is separated from the memory block, the power consumption of the block where the signal processing is not performed is reduced and unnecessary power consumption is suppressed. You can

In this embodiment, an example in which three signal processing circuit blocks share a memory block has been shown, but it goes without saying that the number of signal processing circuit blocks may be any number of two or more. In this embodiment, one input / output signal to / from the memory block is shown for each signal processing circuit block, but it goes without saying that the number of input / output signals may be any number of one or more. Further, in this embodiment, the AND circuit is used to stop the supply of the clock signal to each signal processing circuit block.
Any one may be used as long as it controls the supply of the clock signal, such as an ON / OFF switch.

FIG. 8 is a block diagram of a television receiver according to the second embodiment of the third invention. In FIG. 8, reference numerals 14, 21 to 37 are the same as those of the embodiment of the second invention shown in FIG. Reference numeral 38 is an input terminal for inputting a clock signal CKM for driving the MUSE signal processing block 26, and 39 is an input terminal for inputting a clock signal CKN for driving the NTSC signal processing block 27.

FIG. 9 is a block diagram showing a configuration example of the MUSE signal processing block 26. In FIG. 9, 41 to 5
4 is the same as the embodiment of the second invention shown in FIG. 5
Reference numerals 5 and 56 are AND circuits.

FIG. 10 is a block diagram showing a configuration example of the NTSC signal processing block 27. In FIG. 10, 61
74 are the same as those of the embodiment of the second invention shown in FIG. 75 is an AND circuit.

The operation of the television receiver of this embodiment constructed as above will be described below. Since the basic operation is similar to that of the second embodiment of the invention, only the operation peculiar to this embodiment will be described here. A clock signal CKM for driving the MUSE signal processing block is input to the clock signal input terminal 38, and a clock signal CKN for driving the NTSC signal processing block is input to the clock signal input terminal 39.

The following description of the operation is mainly divided into the case where the signal to be decoded is the MUSE signal and the case where the signal is the NTSC signal.

First, when mainly decoding the MUSE signal, the selection signal M / N applied to the input terminal 23 becomes a value for selecting MUSE, and the MUSE signal processing block 26 and NTS.
It is input to the C signal processing block 27. In the MUSE signal processing block 26, when the selection signal M / N selects MUSE, the output CK1 of the AND circuit 55 becomes the same as the input clock signal CKM. On the other hand, the output CK2 of the AND circuit 56 is fixed at "L" level, and the clock signal is stopped. Interframe interpolation circuit 421, interfield interpolation circuit 422, motion detection circuit 43, mixing circuit 44
CK1 is supplied as a drive clock signal to
CK2 is supplied to the space-time filter circuit 48.
It goes without saying that the other processing circuits are supplied with appropriate clocks that are not dependent on the selection signal M / N.

Therefore, when the selection signal M / N selects MUSE, the clock is not supplied to the spatiotemporal filter circuit 48 and it does not operate. According to the second embodiment of the present invention, the selector 49 is in the state of selecting S4, so that the entire signal processing path is not affected. Therefore, in this case, the power consumed by the space-time filter circuit 48 can be reduced. In the NTSC processing block 27, when the selection signal M / N selects MUSE, the output CK of the AND circuit 75
3 is fixed to the "L" level, and the clock signal is stopped. Inter-frame YC separation circuit 611, motion detection circuit 63, mixing circuit 64, inter-field interpolation circuit 67
1, CK3 is supplied to the mixing circuit 70 as a drive clock signal.

For the other processing circuits, the selection signal M /
It goes without saying that an appropriate clock independent of N is supplied. Therefore, when the selection signal M / N selects MUSE, no clock is supplied to the inter-frame YC separation circuit 611, the motion detection circuit 63, the mixing circuit 64, the inter-field interpolation circuit 671, and the mixing circuit 70. do not do. According to the second embodiment of the present invention, the selector 65 selects S7 and the selector 71 selects S9, so that the entire signal processing path is not affected.
Therefore, in this case, the power consumed by the inter-frame YC separation circuit 611, the motion detection circuit 63, the mixing circuit 64, the inter-field interpolation circuit 671, and the mixing circuit 70 can be reduced.

Next, when mainly decoding the NTSC signal, the selection signal M / N applied to the input terminal 23 becomes a value for selecting NTSC and the MUSE signal processing block 26 and NTS.
It is input to the C signal processing block 27. In the MUSE signal processing block 26, when the selection signal M / N selects NTSC, the output CK1 of the AND circuit 55 is fixed at "L" level and the clock signal is stopped.
On the other hand, the output CK2 of the AND circuit 56 is the input clock signal C
It will be the same as KM. In this case, the inter-frame interpolation circuit 42
1, inter-field interpolation circuit 422, motion detection circuit 43,
Since the clock is not supplied to the mixing circuit 44, it does not operate.

According to the second embodiment of the present invention, the selector 45 is in the state of selecting S2, so that the entire signal processing path is not affected. Therefore, in this case, the interframe interpolation circuit 421, the interfield interpolation circuit 422, and the motion detection circuit 4
3. The power consumed by the mixing circuit 44 can be reduced. NTS
In the C processing block 27, when the selection signal M / N selects NTSC, the output CK3 of the AND circuit 75 becomes the same as the input clock signal CKN. In this case, all signal processing circuits in the NTSC signal processing block operate.

As described above, according to this embodiment, in the signal processing circuit block in which the use of the image memory is restricted according to the selection signal, the path for signal processing does not pass through the space-time processing when the memory cannot be used. By switching to, it is possible to enjoy images of both the signal processing circuit block that mainly uses the image memory and the signal processing circuit block where the use of the image memory is restricted, and the signal is changed due to the switching of the path. It is possible to suppress unnecessary power consumption by stopping the supply of the clock of the signal processing circuit that does not affect the output signal on the processing path.

In this embodiment, when the space-time signal processing circuit restricts the use of the image memory according to the selection signal, the selectors 45, 65 and 70 are used to force the signal processing path to perform only the space processing. However, the mixing circuits 44, 64, and 70 may be configured to forcibly set the mixing ratio of the output of the spatial signal processing and the output of the spatiotemporal signal processing to 10: 0. Needless to say. Further, in this embodiment, the inter-frame interpolation circuit 4
21 performs inter-frame interpolation processing with the current signal and the 1-frame delayed signal obtained via the image memory 29. The cyclic configuration including the selector circuit 109 and the image memories 107 and 108 in the conventional example shown in FIG. It goes without saying that the inter-frame interpolation circuit may be used.

Further, in this embodiment, the example in which the memory is shared by the MUSE signal processing block and the NTSC signal processing block has been shown, but even if the memory is shared between the signal processing circuit blocks corresponding to any two or more broadcasting systems. Not to mention good things. Further, in this embodiment, the MUSE interframe interpolation circuit 421 is used as a combination of memory sharing.
And NTSC YC separation circuit 611, MUSE
Inter-field interpolation circuit 422 and space-time filter 48,
Although the memories are shared among the inter-field interpolation circuits 671 of NTSC, it goes without saying that the memory is not limited to this combination. Further, in this embodiment, the AND circuit is used to stop the supply of the clock signal to each signal processing circuit block, but any device such as a normal ON / OFF switch that controls the supply of the clock signal may be used. Good.

[0075]

As described above, according to the first aspect of the invention, the signal input to the memory is provided by providing the output terminals of the plurality of signal processing circuits commonly connected to the inputs of the memory with the tristate function. By selectively selecting, it is possible to share memory from many signal processing circuit blocks without adding additional hardware such as a selector, or to use various memories for each processing in the signal processing circuit block. It can flexibly deal with shared combinations, and its practical effect is great.

According to the second aspect of the invention, in addition to the effect of the first aspect of the invention, a plurality of images can be simultaneously viewed by each signal processing circuit performing respective image signal processing even in the memory sharing state. It is possible and its practical effect is great.

According to the third invention, in addition to the effect of the second invention, unnecessary power consumption can be suppressed, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a television receiver according to an embodiment of the first invention.

FIG. 2 is a block diagram of a television receiver according to an embodiment of the second invention.

FIG. 3 is a block diagram showing a configuration example of a MUSE signal processing block of the same embodiment.

FIG. 4 is a block diagram showing a configuration example of an NTSC signal processing block of the same embodiment.

FIG. 5 is a first screen diagram for explaining the operation of the screen compositing circuit of the embodiment.

FIG. 6 is a second screen diagram for explaining the operation of the screen compositing circuit of the embodiment.

FIG. 7 is a block diagram of a television receiver according to the first embodiment of the third invention.

FIG. 8 is a block diagram of a television receiver according to a second embodiment of the third invention.

FIG. 9 is a block diagram showing a configuration example of a MUSE signal processing block of the same embodiment.

FIG. 10 is a block diagram showing a configuration example of an NTSC signal processing block of the same embodiment.

FIG. 11 is a block diagram of a conventional television receiver.

[Explanation of symbols]

1,2,3,4,21,22,23,38,39,8
1, 82, 83, 101, 102, 103 Signal input terminals 5, 6, 7, 24, 25 A / D converters 8, 9, 10 Signal processing circuit block 11, 12, 13, 51, 52, 53, 73,74 Tri-state output terminal 14 Memory block 15,16,17,34,35,117,118,11
9, 120, 121, 122 D / A converter 18, 19, 20, 36 Signal output terminal 26, 115 MUSE signal processing block 27, 116 NTSC signal processing block 29, 30, 31, 32, 107, 108 Image memory 33 screen synthesis circuit 37, 123, 124 monitor 41 video processing circuit 42 still image processing circuit 43, 63 motion detection circuit 44, 64, 70 mixing circuit 45, 49, 65, 71, 106, 109, 112 selector circuit 46, 50 , 72 Decoding circuit 47 Scanning line number conversion circuit 48 Space-time filter circuit 61 YC separation circuit for still image 62 YC separation circuit for moving image 66 Subtractor 67 Scanning line interpolation circuit for still image 68 Scanning line interpolation circuit for moving image 69 Color signal interpolation Circuit 55, 56, 75, 84, 84, 86 AND circuit 110 Timing generation for MUSE Circuit 111 NTSC timing generator circuit 113 the address generator 114 separation circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Atsushi Ishizu 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (4)

[Claims] 1. A plurality of video signal processing circuit blocks and at least one memory block, wherein signal lines from the plurality of video signal processing circuit blocks are commonly connected to an input terminal of the memory block. Of the video signal processing circuit block has a tri-state function at an output terminal for supplying a signal to the memory block, and outputs all signals to the memory block except for the output terminal selected according to the selection signal to a high impedance state. A television receiver characterized by selectively selecting an input signal. 2. The television receiver according to claim 1, wherein the plurality of video signal processing circuit blocks and the at least one memory memory block perform signal processing corresponding to a plurality of broadcasting systems. 3. The plurality of video signal processing circuit blocks,
A spatial signal processing circuit that performs processing using only signals within the same field of the incoming input signal; and a spatio-temporal signal processing circuit that performs processing using signals for a plurality of fields. The television receiver according to claim 1, wherein when the spatiotemporal signal processing circuit cannot obtain signals for a plurality of fields, a signal processing mode is used in which an output from the spatiotemporal signal processing circuit is not used. 4. The plurality of signal processing circuit blocks can stop driving clocks for all or some of the blocks according to the selection signal.
The described television receiver.