JPH0344186A - Signal converter - Google Patents

Abstract

PURPOSE:To save memory capacity by one field by providing a field memory group obtaining a signal retarding an output signal of a de-emphasis circuit by one to three-fields. CONSTITUTION:A field memory group 38 consists of cascade connection of three-field memories 28-30 and outputs a one-field delay signal m1, a two-field delay signal m2, a three-field delay signal m3, retarding an output signal m0 of a de-emphasis circuit 4 by one-field, two-field and three-field respectively. The output signal m0 and the delay signals m1-m3 of the de-emphasis circuit 4 are fed to a vertical low pass filter 32 via inter-frame interpolation circuits 8, 31 and also to a movement detection circuit 33. Thus, the vertical low pass filter 32 and the movement detection circuit 33 are operated similarly as a conventional signal converter, and the memory part consists of field memories 28-30 and the clock rate is 16.2MHz for 3 fields only. Thus, one field of memory capacity saved in comparison with four fields in the conventional circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a signal conversion device, and particularly relates to a signal conversion device that converts a MUSE signal into a No. 13 signal that can be received by current television receivers. be.

(Prior Art) The MUSE system, which compresses the bandwidth of high-definition television signals and enables transmission by satellite broadcasting, has been proposed and experimental broadcasting is being conducted.

MUSE is multiple 5ub-Nyquist
It is an abbreviation for sampling encoding, and N
This is a method developed by HK (Japan Broadcasting Corporation).

The MUSE method is described in various documents (for example, 1°N 11K Technical Research, 1988;
Volume 32, p18-p53rDevelopment of the MUsE method for the second bow, p189-p212 of Nikkei Electronics J November 2, 1987 issue 3 for Nikkei McGraw-Hill.
Transmission method for high-definition broadcasting using satellites, MUSEJ, etc.>
, a detailed explanation will be omitted here.

The brightness signal (Y signal) of the MUSE method is transmitted at O11; then, as shown in FIG.
6M)1. AD conversion is performed at a sampling frequency of 16.2 MH, and data is compressed using inter-field and inter-frame offset sampling at a sampling frequency of 16.2 MH, followed by DA conversion and transmitted back to an analog signal.

This signal is shown in FIG. 2(A) as shown in FIG. 2(B).
8 of ■～■ shown in . High frequency component above IMHz is 8.1M
Folds back into the Hz band, increasing the baseband bandwidth to 8.1M
H, pressure Ii! It is being processed.

A MUSE decoder (receiver) receives and demodulates this band-compressed MLJSE signal.

However, as is well known, the MtJSE decoder requires a very large circuit and a special cathode ray tube with an aspect ratio of 16:9, and is very K(Ii).

Therefore, a signal converter (down converter) has been proposed that converts the MUSE signal with 25 scanning lines into a signal that can be received by the current television receiver with 525 scanning lines.

FIG. 3 is a block diagram showing a conventional signal conversion device.

In FIG. 3, the MUSE signal that enters the input terminal 1 is supplied to the AD converter 3 via a low-pass filter 2 that passes frequencies of approximately 8.1 MH and below.
The clock of MH (i) is resampled and becomes a digital signal.

The output signal of the AD converter 3 is supplied to a de-emphasis circuit 4, where it is subjected to de-emphasis processing, and
The signal is supplied to the control signal separation circuit 5, and the control signal is separated.

As is well known, the control signal includes motion vector data, sub-sample phase data, and the like.

The output signal g of the de-emphasis circuit 4 is supplied to the field interpolation circuit 6, and is subjected to interpolation processing from the 1st number point within the current field regardless of whether it is a moving image or a still image.

FIG. 4 is a dimensional diagram showing the pixel arrangement.

As shown in Fig. 4, the pixels of the MUSE signal are in a state where pixel O of the current field and pixel ・ of the previous frame are offset between frames, and pixel ○ and pixel ・ of the previous field are offset every 7 rem.
are being replaced.

Therefore, the intra-field interpolation process converts the data of the non-sampled points (internal midpoints) of the pixel shown in FIG. Created and interpolated.

Note that the sample point and the interpolation point are identified here by the sub-sampled phase data in the control signal supplied from the control signal separation circuit 5.

In FIG. 3, the output signal of the de-emphasis circuit 4 is supplied to a frame memory 7.

Since the frame memory 7 operates to store only one room of the input signal No. 3, the output signal of the field memory 7 is a signal delayed by one frame from the input signal.

The output signal of the de-emphasis circuit 4 and the output signal of the frame memory 7 are respectively supplied to an interframe interpolation circuit 8.

The interframe interpolation circuit 8 interpolates the current field signal and 1
Perform inter-frame push processing between the signals before the frame,
Still image processing is performed by creating data at non-sampled points (interpolation points) from data at sample points obtained by lean-bringing one frame before, and interpolating the data.

Therefore, the deterioration in image quality caused by the coarse rimple points offset between frames 21 can be resolved by making the sample point density finer by the interpolation described above.

Then, aliasing components due to interframe offsets are removed, improving image quality.

However, as is well known, in the MUSE bow, offset sampling is performed even between fields, and aliasing components for this still remain.

This aliasing component is described in the above-mentioned document I N 11 K Technical Research, 1986, No. 32'#, No. 2 pia-p53.
Since it is described in detail in Figure 3.9 of ``Development of rMUsE method'', detailed explanation will be omitted, but 12 to 22M
The +-+z band components are folded back.

FIG. 5 is a diagram showing two-dimensional frequency characteristics after inter-frame interpolation. The horizontal axis represents horizontal frequency, and the vertical axis represents -1 vertical frequency. Vertical frequency is expressed in units of TV lines, which represent television frames without regard to interlacing.

In FIG. 5, the aliasing components between fields have a horizontal frequency of 12 to 22 MHz and a vertical frequency of 1125/21-MHz.
The signal components in the frequency band of the V-tree have a horizontal frequency of 2 to 1.
2MH1, the vertical frequency is turned back to a frequency band of 1125/2 to 1125'rV.

By the way, the bandwidth required for conversion to the NTSC system is 525 TV lines or less in vertical frequency.

This aliasing component has a vertical frequency of 1125/2
It can be removed by a vertical low-pass filter that blocks the passage of frequency bands above the TV line.

The output signal of the interframe interpolation circuit 8 is supplied to a vertical low-pass filter 9.

The vertical low-pass filter 9 removes vertical frequency components in the vicinity of 1125 TV lines and removes aliasing components due to inter-field offset.

Furthermore, in the interframe interpolation process, the current-no-yield recombination point is determined based on the 1-knob sample phase data detected by the control signal 0 separation circuit 5.

The vertical low-pass filter 9 includes a field memory 10,
It is composed of line memory 1) 11, addition D[12, 13].

The current line signal jo, which is the output signal S of the interframe interpolation circuit 8, is supplied to the field memory 10.

The field memory 10 receives the human input signal by 1゛noird (5
62 lines) and the signal 156 is delayed by 562 lines.
2 is obtained. The signal 4562 before this 562 lines is
Line memory 111\ is supplied.

The line memory 11 delays the input signal by one line to obtain a signal 1563 563 lines before io.

These signals 1562 and 1563 are each supplied to the adder 12, added together, and further halved and output.

The output (1) of this adder 12 and the signal No. of the current line are
Each is supplied to the adder 13, added, and further 1/
2 and becomes the signal l, which is output.

Therefore, this signal l is expressed by the following equation.

1=i o/2+j 5a 2/4+j 5 e 3/
4 By performing processing as in the above equation, vertical frequency components in the vicinity of 1125 TV lines are removed, and the filter operates as a vertical low-pass filter.

Next, interframe interpolation processing when a still image is translated in parallel due to panning or the like operates as follows.

That is, in this case, the images between each frame are displaced due to parallel movement, and interpolation between frames cannot be performed as is.

Therefore, in the control signal separation circuit 5, the motion vector data transmitted from the transmitting side is extracted, and the read timing of the frame memory 7 is 1IIIltiO according to the amount of motion vectors, thereby adjusting the position shift between frames. After eliminating it, interframe interpolation processing is performed.

The two signals, the output signal of the intra-field interpolation circuit 6 which has been subjected to moving image processing, and the output signal of the vertical low-pass filter 9 which has undergone still image processing, are respectively supplied to a mixing circuit 14 and mixed. being processed.

The output signal of the mixing circuit 14 is supplied to a scanning line conversion circuit 15.

Further, the output signal of the de-emphasis circuit 4 and the output signal of the frame memory 7 are respectively supplied to a subtracter 17 in the motion detection circuit 16.

The motion detection circuit 16 includes a subtracter 17. Low pass filter 1
8. Absolute value circuit 19. It is composed of an R large fi selection circuit 20, a field memory 21, and a line memory 22, and its operation will be explained below.

A subtracter 17 extracts a difference signal between frames.

This interframe difference signal is supplied to a low pass filter 18.

The low-pass filter 18 is a low-pass filter that passes frequency components of 4 MHz or lower.

That is, as is clear from FIG. 2(B), since the aliasing components are concentrated at 4 MHz or more, the low-pass filter 1 is used to prevent motion detection from malfunctioning due to the aliasing components.
8 can be prevented.

The output signal of the low-pass filter 18 is transmitted to the absolute value circuit 1.
9, the absolute value of the signal is multiplied by 1:1, and motion is detected.

Movement 1il of the current line which is the output signal of the absolute value circuit 19
n,) is up to 11! When supplied to the i selection circuit 20, J
1- is also supplied to the field device 21.

The FIELMOS 7RI 21 delays the input signal by 562 lines to obtain a motion change n562 of 562 lines earlier.

This moving pigeon n5a2 562 lines before is supplied to the line memory 22.

The line memory 22 delays the ``input'' signal by one line, and obtains 583 movement lines 563 lines earlier for ``no''.

These three movements finO, n5s2, and 0563 are each supplied to the maximum value selection circuit 20, and the last of the three movements, the mouse with the maximum movement, is selected and output to the mixing circuit 14.

Since the vertical low-pass filter 9 performs processing between fields, the motion detection circuit also performs processing between rooms. In addition to motion detection between fields, motion detection between fields is also performed.

The motion detection circuit which is the output signal S of the motion detection circuit 6 is supplied to the mixing circuit 14, and operates to control the mixing ratio of the two signals in the mixing circuit 14 according to the motion detection circuit. There is.

That is, when the start of movement is below a predetermined level, t is mixed according to the amount of movement, and when it is above a predetermined level, only the moving image processing signal is output.

The output signal 3 of the mixing circuit 14 is supplied to a scanning line conversion circuit 15.

The scanning line conversion circuit 15 converts the frame frequency (30H,) into a message, for example, while keeping the frame frequency (30H,) as it is.

By controlling readout, a signal of 1125 scanning lines per frame is converted into a signal of 525 scanning lines per frame.

Said congruent line conversion circuit 15σ) output! The signal is supplied to the 101 decoding circuit 23.

The color signal (C signal) in the MUSE signal is the luminance signal @(
TCI (Time Compressed InL), which compresses the time of Y signal to 1/4 and time-division multiplexes it.
It is transmitted in a signal format called corat+on).

The TCI decoding circuit 23 time-expands the C signal to 4 (8), further converts it into two color difference signals, and outputs them together with the Y signal.

The output signal of the TCI decode circuit 23 is supplied to a DA converter 24 and becomes an analog signal.

The output signal of the DA converter 24 is supplied to an inverse matrix circuit 26 via a low-pass filter 25.

The inverse matrix circuit 26 supplies an output signal of 525 scanning lines per frame converted into 3IfA color signals of R, G, and B to an output terminal 27.

(Problem to be Solved by the Invention) The conventional signal conversion 5A system described above uses interframe interpolation processing by an interframe interpolation circuit and removal of a frequency band around the vertical frequency of 1125 TV lines by a vertical low-pass filter. , aliasing components between fields and frames are removed.

However, for interframe interpolation processing, there is a frame memory 7 that delays the output signal of the DAYF7 cis circuit by one frame, and a field memory 10 that delays the interframe interpolated signal by one field to remove aliasing components. However, each was necessary.

Note that the output signal of the dephasis circuit has a clock rate of 16.2 MH, and the signal after interframe interpolation has a clock rate of 32.4 MH.

To delay a signal with a clock rate of 32.4 MH by one field, the same memory capacity is required as to delay a signal with a clock rate of 16.2 MH by two fields (one frame).

After all, in the conventional example, the total clock rate of the frame memory 7 and field memory 10 was 16.2 MHI, and a memory capacity for 4 fields (2 frames) was required.

Furthermore, the motion detection circuit 16 requires a separate field memory 21 that delays the motion signal by one node.

The total memory capacity of these memories is quite large, resulting in a problem that the cost burden becomes extremely large.

Since the present invention has been made with attention to the above points, the output signal of the day phasis circuit is divided into one field.

By providing a field memory group that stores signals delayed by 2 or 3 fields, these signals can be used in vertical low-pass filters and motion detection circuits, reducing noise by 1 noise compared to conventional methods. It is an object of the present invention to provide a signal conversion device which is extremely advantageous in terms of cost since the memory capacity of the device can be reduced.

<Means for solving the problem> In order to achieve the above purpose, a MUSE signal obtained by band-compressing a high-definition television signal is received.

A signal conversion device that demodulates and converts the signal into a signal that can be received by a current television receiver, comprising an AD converter that resamples the MUSE signal using a clock signal, and a de-emphasis process that de-emphasizes the output signal of the AD converter. a field memory group that outputs a 1-field delayed signal, a 2-field delayed signal, and a 3-field delayed signal g obtained by delaying the output signal of the de-emphasis circuit by 1 field, 2 fields, and 3 fields, respectively; an intra-field interpolation circuit that performs moving image processing by interpolating the output signal of the circuit within the field; and a first interpolation circuit that performs still image processing by interpolating the output signal of the de-emphasis circuit and the two-field delayed signal between frames. a second interframe interpolation circuit that performs still image processing by interpolating the 1-field delayed signal and the 3-field delayed signal between frames; A vertical low-pass filter inputs the output signal of the interframe interpolation circuit, removes vertical frequency components near 1125 TV lines, and outputs the output signal, and the output signal 9 of the intra-field interpolation circuit and the output of the vertical low-pass filter. a mixing circuit that mixes and processes two signals; a scanning line conversion circuit that converts the 1125 scanning line signals that are the output signals of the mixing circuit into scanning line signals of the current television system;
An inter-frame difference signal is obtained from the output signal of the de-emphasis circuit and the 2 noyield delay signal described above, and the first mover is detected by converting it into an absolute value through a low-pass filter, and the first mover is detected by the one-field delay signal. A second motion loss is detected by obtaining a difference signal between the signal and the 3-field delay signal and converting it into an absolute value through a low-pass filter. A third moving insect is detected with the amount of motion delayed by one line, and this first. Second. Select and output the maximum amount of movement among the third movement suspensions, and adjust the mixing ratio of the two bows in the mixing circuit accordingly.
The present invention provides a signal conversion device characterized in that it is configured to include a motion detection circuit that performs lltllll motion detection circuitry.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of a signal conversion device of the present invention. The same parts as in FIG. 3 are designated by the same reference numerals.

The main difference in configuration from FIG. 3 is that a field memory group 38 is provided to obtain signals obtained by delaying the output signal of the de-emphasis circuit 4 by 1 field, 2 fields, and 3 fields. The operation of only the parts will be explained.

In FIG. 1, the output signal mo of the de-emphasis circuit 4 is supplied to a field memory group 38.

The field memory group 38 includes three field memories 2
8, 29, and 30 are connected in cascade, and the output signal no of the de-emphasis circuit 4 is
Field, 2 fields.

1-field delayed signal m1 delayed by 3 fields
, 2-field delayed signal Qm2.3-field delayed signal m
3 is output.

Note that the three field memories 28, 29, and 30 operate at a clock rate of 16.2 MH.

The output signals m, ) of the de-emphasis circuit 4 and the 2-field delay signal m2 are respectively sent to an interframe interpolation circuit 8.
(first inter-frame interpolation circuit), performs inter-room interpolation processing between one frame (two fields), and converts the data at the unsampled point (interpolation point) to the one-frame previous interpolation circuit. It is created from data at a sample point (sample point), performs interpolation still image processing, and outputs the signal jo of the current line.

Incidentally, the inner III'I processing in the interframe interpolation circuit 8 is performed using the sub-sampled phase data detected by the control signal separation circuit 5.

Similarly, the 1-field delayed signal @m+ and the 3-field delayed signal m3 are each supplied to the interframe interpolation circuit 31 (second interframe interpolation circuit),
A still image that performs interframe interpolation processing between frames (fields), creates data at unsampled points (interpolated points) from data at sampled points one frame before (sample points), and interpolates. Processing the system.

Further, the interpolation process at J3 in the interframe interpolation circuit 31 is performed by delaying the sub-sample phase data detected by the control signal separation circuit 5 by one field by a one-field delayer 37.

However, the interframe interpolation circuit 31 inputs the input signal to the interframe interpolation circuit 8 on 562 lines (
Since the signal is delayed by 1 field), the output signal of the interframe interpolation circuit 8 (signal jNjo of the current line is
2 lines (signal 1562 before 562 lines delayed)
is outputting.

The output signals of the interframe interpolation circuits 8 and 31 are supplied to a vertical low-pass filter 32, respectively.

The vertical low-pass filter 32 is composed of a line memory 11 and tighteners 12 and 13.

The signal @l 562 from 562 lines before, which is the output signal of the interframe interpolation circuit 31, is supplied to the line input circuit 11.

The line memory 11 delays the input signal by one line to obtain a signal 1563 563 lines before jo.

These signals @l 582 and 1563 are input to the adder 12, respectively.
It is supplied to the factory, caulked, and then halved and output.

The output signal of the adder 12 and the current line signal lo, which is the output signal of the interframe Nishioki circuit 8, are each supplied to the adder 13, where they are tightened, and further halved to become the signal l, which is output. has been done.

Therefore, this vertical low 11! ! The pass noiler 32 operates in the same manner as the vertical low-pass filter 9 in the conventional example, and vertical frequency components in the vicinity of 1125 TV lines are removed.

The output signal of the noield interpolation circuit 6 which has been subjected to moving image processing and the output signal of the vertical low-pass filter 32 which has undergone still image processing are sent to a mixing circuit 14, respectively.
Supplied and mixed! 1111 has been confirmed.

The output signal of the mixing circuit 14 is supplied to a scanning line conversion circuit 15.

Further, the motion detection circuit 33 includes attenuators 17, 34° low-pass filters 18, 35. Absolute value circuit 19°36, maximum value selection circuit 20. Field memory 21 and line memory 2
2, and its operation will be explained below.

The output signal mo and the two-field delay signal m2 of the de-emphasis circuit 4 are respectively supplied to a subtracter 17 in the motion detection circuit 33, and a difference signal between frames is extracted.

This inter-frame difference signal is supplied to a low-pass nolter 18.

The low-pass filter 18 is a low-pass filter that passes frequency components of 4MH or less.

The output signal of the low-pass filter 18 is transmitted to the absolute value circuit 1.
9, the absolute value of the signal is obtained and the motion of the current line (the first motion ffi>no has been detected).

The current line movement lno which is the output signal of the absolute value circuit 19
is supplied to the maximum value selection circuit 20.

Similarly, the 1-field delayed signal m1 and the 3-field delayed signal m3 are each supplied to a sound attenuator 34 in the motion detection circuit 33, and a difference signal between frames is extracted.

This inter-frame difference signal is supplied to a low-pass filter 35.

The low-pass filter 35 is a low-pass filter that passes frequency components of 4MH or less.

The output signal of the low-pass filter 35 is supplied to an absolute (ia) circuit 36, and the absolute value of the signal is multiplied by 15I to detect motion loss.

Note that the input signals to the subtractor 34 are signals delayed by 562 lines (1 field) with respect to the input signals to the subtracter 17, so the motion mouse that is the output signal of the absolute value circuit 36 is as follows. Compared to the motion number no which is the output signal of the absolute value circuit 19, the motion of the previous 562 lines (the second motion) is n562.The motion of the mouse 562 lines before which is the output signal of the absolute value circuit 36 is is supplied to the maximum value selection circuit 20 and also to the line memory 22.

The line memory 22 delays the input signal by one line and stores the motion jet (third motion I) 563 lines before the no.
) n5a3 is obtained.

These three moving blocks no, n562 and 0563 are respectively supplied to the maximum value selection circuit 20, and the largest moving turtle among the three is selected and output to the mixing circuit 14.

The motion detection signal which is the output signal of the motion detection circuit 33 is supplied to the mixing circuit 14, and operates to control the mixing ratio of the two items in the mixing circuit 14 according to this motion detection circuit. .

Therefore, this motion detection circuit 33 operates in the same manner as the motion detection circuit 16 in the conventional example.

As explained above, it can be seen that the vertical low-pass filter 32 and motion detection circuit 33 in the signal conversion device of the present invention operate in the same manner as the conventional example shown in FIG.

Moreover, the memory capacity is 28.
29.30, clock rate 16.2MH,
Therefore, only 3 fields are needed, which is one field less than the 4 fields of the conventional example.

Furthermore, the field memory 21 in the conventional motion detection circuit can also be deleted.

(Effects of the Invention) The signal conversion v4 device of the present invention has the above-described configuration, and includes a field memory group that obtains a signal obtained by delaying the output signal of the DAF7cis circuit by 1 field, 2 fields, or 3 fields. By using these signals in the vertical low-pass filter and motion detection circuit, the memory capacity for one field can be reduced compared to the conventional method, making it very cost-effective and practical. It has an arrogant effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the signal conversion device of the present invention, FIG. 2 is a diagram showing frequency spectrum characteristics of a signal of the MIJSE transmission system, and FIG. 3 is a block diagram showing a conventional signal conversion device. FIG. 4 is a diagram showing a pixel arrangement, and FIG. 5 is a diagram showing two-dimensional frequency characteristics after interpolation between frames. DESCRIPTION OF SYMBOLS 1... Input terminal, 2, 18, 25.35... Low pass filter, 3... AD converter, 4... De-emphasis circuit, 5... Control signal separation circuit, 6...
... Inner circuit in the field, 7... Frame memory,
8゜31...Interframe interpolation processing circuit, 9,32...
・Vertical low-pass filter, 10, 21.2B, 29°3
0...Field memory, 11.22...Line memory, 12.13...Adder, 14...Mixing circuit,
15...Scanning line conversion circuit, 16. '33...Motion detection circuit, 17.34...Subtractor, 19.36...Absolute 1j1 circuit, 20...Maximum value selection circuit, 23...
TCI decoding circuit, 24...DA converter, 26...
Inverse matrix circuit, 27...output terminal, 37...
1 field delay device, 38... field memory group,
1. Ilo. j5a2. j5a: +...signal, mo...output signal of the de-emphasis circuit, ml...1 field delay signal, m2...2 field delay signal, m3...3
Field delay signal, no+1 0563...Motion suspension.

Claims (1)

[Scope of Claims] In a signal conversion device that receives and demodulates a MUSE signal obtained by band-compressing a high-definition television signal and converts it into a signal that can be received by a current television receiver, the MUSE signal is resampled using a clock signal. a de-emphasis circuit that performs de-emphasis processing on the output signal of the AD converter; and a 1-field delay for the output signal of the de-emphasis circuit by 1 field, 2 fields, and 3 fields, respectively. a field memory group that outputs a delayed signal, a 2-field delayed signal, and a 3-field delayed signal; an intra-field interpolation circuit that performs video processing by interpolating the output signal of the de-emphasis circuit within the field; and the de-emphasis circuit. a first interframe interpolation circuit that performs still image processing by interpolating the output signal of the circuit and the 2-field delayed signal between frames; a second interframe interpolation circuit that performs image processing; and a vertical low frequency component that inputs the output signals of the first and second interframe interpolation circuits, removes vertical frequency components near 1125 TV lines, and outputs the result. a pass filter; a mixing circuit that mixes and processes two signals, the output signal of the intra-field interpolation circuit and the output signal of the vertical low-pass filter; A scanning line conversion circuit converts the signal into a scanning line signal of the John system, and a difference signal between frames is obtained from the output signal of the de-emphasis circuit and the two-field delay signal, and the signal is converted to an absolute value through a low-pass filter. A first motion amount is detected by doing this, and an inter-frame difference signal is obtained from the 1-field delayed signal and the 3-field delayed signal, and the second motion amount is determined by converting it into an absolute value through a low-pass filter. Detect the amount of motion, further detect a third amount of motion that is obtained by delaying this second amount of motion by one line, and select the largest amount of motion among the first, second, and third amounts of motion. and a motion detection circuit that outputs a motion detection circuit and controls a mixing ratio of the two signals in the mixing circuit accordingly.