JPH0746547A - Muse decoder motion detection circuit - Google Patents

Abstract

PURPOSE:To reduce circuit scale and to improve the accuracy of edge detection by sharing the same function circuit of an edge detection processing part as one part of motion detection processing and an inter-field interpolation processing part as one part of the reproducing processing circuit of a video moving image signal. CONSTITUTION:Concerning the MUSE decoder motion detection circuit provided with the edge detecting means for performing motion detection processing (12) and an in-field interpolating means 13 for interpolating image data inside a field and equipped with a circuit block to form the plural pieces of the same function respectively in the edge detecting means and the in-field interpolating means 13, one or plural circuit blocks are mutually shared by the edge detecting means and the in-field interpolating means 13.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to band-compressed MUSE.
The present invention relates to a MUSE decoder that demodulates a signal into an original wideband high-definition television signal and reproduces the signal, and in particular, an MUSE decoder that shares a circuit for edge detection processing that is a part of motion detection processing and a video / video signal reproduction processing It relates to a motion detection circuit.

[0002]

2. Description of the Related Art MUSE (Muitiple Sub-Nyquist Sampling) is applied to an original high-definition television signal to perform a sub-Nyquist sample that makes a round in four fields as a method of band-compressing a wide-band high-definition television signal to a practical level for transmission.
Encoding) method.

The MUSE method is a method developed by NHK (Japan Broadcasting Corporation) and used in various documents (eg, December 1, 1990).
The detailed description is omitted because it is described in "MUSE-Hibbit Transmission System" by Yuichi Ninomiya et al.

In the MUSE system, a high-definition television signal (hereinafter referred to as "baseband signal") having a band of up to about 22 MHz for a luminance signal (hereinafter referred to as "Y signal") and about 7 MHz for a color signal (hereinafter referred to as C signal). With a bandwidth of 27 MH
Approximately 8 MHz to transmit on 1 channel of satellite broadcasting of z
Is performing band compression processing. The MUSE decoder demodulates the band-compressed signal (hereinafter referred to as "MUSE signal") into the original baseband signal.

FIG. 6 is a block diagram showing the structure of a conventional MUSE decoder.

The MUSE signal is supplied to the input terminal 1,
After the band is limited by the LPF 2 having the cutoff frequency of 8.1 MHz, the digital signal is sampled by the A / D converter 3 with the clock signal of 16.2 MHz. The output signal of the A / D converter 3 is input to the audio decoding unit 4, the synchronization processing unit 5, and the de-emphasis processing unit 6.

The audio decoding unit 4 separates and decodes the audio signal from the input signal, and outputs an audio 4 channel / independent data signal 7.

In the synchronization processing unit 5, the synchronization signal 8 and the control signal 9 are separated from the input signal and supplied to each signal processing unit.

The de-emphasis processing unit 6 performs a process opposite to the emphasis in the MUSE encoder (transmission side process). The signal subjected to the de-emphasis process is subjected to the inverse process of the transmission gamma on the encoder side in the inverse gamma correction processing unit 10 to become the linear signal 11.

The signal 11 after the inverse gamma correction processing is input to the motion detection processing unit 12, the field interpolation processing unit 13, and the interframe interpolation processing unit 14.

The motion detection processing section 12 detects a moving image area using the signal of the frame difference, and the MIX processing section 18 generates a motion signal 15 which is the basis of the mixture ratio of the still image area and the moving image area. The detailed operation of the motion detection process will be described later.

The field interpolation unit 13 interpolates the moving image area in each field and demodulates the 16 MHz data into the 32 MHz data. The field interpolation processing of the moving image area will also be described later. The signal interpolated in the field is 32
The MHz rate is converted into a sampling signal of 48 MHz rate, and is input to the MIX processing unit 18.

The inter-frame interpolation processing unit 14 performs interpolation by interpolating the missing sample with the sample of the previous frame in the still image area. 16M by inter-frame interpolation processing
The data of the Hz rate becomes the data of the 32 MHz rate. The Y signal after the inter-frame interpolation processing is passed through the LPF 19 having a cut-off frequency of 12 MHz in order to prevent aliasing that occurs when the sampling frequency is converted in the next processing.

After passing through the LPF, interpolating between fields is performed, so that the sampling frequency is converted from the 32 MHz rate to the 24 MHz rate. 24 MH in sampling frequency converter 20
Data converted to z-rate is inter-field interpolation processing unit 2
In 1, the missing sample is interpolated with the sample of the previous field to become a sampling signal of 48 MHz rate and MIX
It is input to the processing unit 18.

In the MIX processing section 18, the motion picture signal from the sampling frequency conversion section 17 and the still picture signal from the inter-field interpolation processing section 21 are combined with the motion signal 15 from the motion detection processing section 12.
Mix accordingly.

The output signal of the MIX processing section 18 is separated into a line-sequential scanning color signal into an RY signal 23 and a BY signal 24 in a TCI decoding section 22, and an inverse matrix section 26 calculates a Y signal 25. It is converted into three signals of R signal, G signal, and B signal. These three signals are converted into analog signals by the D / A converter 27, and output as high-definition signals of R signal 29, G signal 30, and B signal 31 through the LPF 28 having a cutoff frequency of about 21 MHz.

Next, the motion detection processing and the field interpolation processing will be described. For the conventional MUSE-based motion detection and field interpolation methods, refer to various documents (for example, Electronics Life 19 published by the Japan Broadcasting Corporation).
January 1990 issue, p38-48 "Mechanism of HDTV receiver")
Have been introduced in.

FIG. 7 is a block diagram showing the structure of a conventional motion detection process. The signal 11 subjected to the inverse gamma correction processing is input to three blocks of the edge detection processing unit 37, the two-frame difference detection processing unit 32, and the one-frame difference detection processing unit 33 in the motion detection processing unit 12.

The edge detection processing unit 37 detects the signal of the edge portion corresponding to the contour portion of the object. A schematic diagram of edge detection is shown in FIG. Since the input signal has a 16 MHz rate, there are points with data (hereinafter referred to as "sample points") and points without data (hereinafter referred to as "non-sample points") on the same line every 32 MHz, and edge detection is performed. Is done in two different ways.

FIG. 8 shows the detection at the sample point and the non-sample point of the horizontal edge detection in (A) and (B), respectively, and FIG. 9 shows the detection at the sample point and the non-sample point of the vertical edge detection, respectively. Shown in (A) and (B). Since the four methods are similar, the description will be made on behalf of the horizontal edge detection at the sample points shown in FIG. The six image data shown in FIG.
If A6, then | A1-A2 |, | A3-A4 |, | A5
-A6 | is found and the maximum value of the three values is taken as the value of the lateral edge of A4.

That is, the lateral edge value of A ₄ = MAX {| A1-A2 |, | A3-
A4 |, | A5-A6 |}.

Similarly in FIGS. 8B and 9A and 9B, the values of the vertical edge and the horizontal edge of each pixel are obtained.

Horizontal edge value of B7 = MAX {| B1-B2 |, | B3-B4
||| B5-B6 |} Vertical edge value of C4 = MAX {| C1-C2 |, | C3-C4
||| C4-C5 |} Vertical edge value of D6 = MAX {| D1-D2 |, | D2-D3
|, | D4-D5 |}

The two-frame difference detection processing unit 32 obtains a difference signal between the two frames and detects a motion corresponding to a slow motion (2 frames = 1/15 seconds).

The 1-frame difference detection processing unit 33 obtains a difference signal between 1-frames, and a motion (1
Motion detection corresponding to frame = 1/30 seconds) is performed.

The detected three types of signals, the edge signal 16, the two-frame detection signal 34 and the one-frame detection signal 35, are input to the moving image area detection processing section 36. The moving image area detection processing unit 36 adjusts the sensitivities of the 1-frame difference detection signal 35 and the 2-frame difference detection signal based on the edge signal 16, takes the maximum value of each of the two signals for each pixel, and outputs it as the motion signal 15. To do.

FIGS. 10A and 10B are schematic views showing an example of conventional field interpolation processing. FIG. 10 (A) is a diagram showing a process of interpolating a sample point (interpolating point E7) and FIG. 10 (B) from a non-sample point (interpolating point F7) from peripheral sample points. Since both methods are similar, FIG.
The field interpolation processing at the sample points shown in FIG. The 13 image data shown in FIG.
When E13 is set, the processing of function f1 is performed on all the data to generate E7 data, and the sampling points are interpolated. Similarly for FIG. 10B, interpolation of non-sample points is performed.

As described above, the motion detection processing unit 12 and the edge detection processing unit 37 and the field interpolation unit 13 perform processing using the same data. Comparing the image data of FIG. 8 (A) and FIG. 10 (A), A1 and E4, A2 and E9, A3 and E
2, A4 and E7, A5 and E5, A6 and E10 are the same data. 8 (B) and FIG. 10 (B), FIG. 9 (A) and FIG. 10 (A), FIG.
The same applies to (B) and FIG. 10 (B).

[0028]

As described above, the conventional MU
The SE decoder has an independent processing system although the motion detection processing unit and the field interpolation processing unit perform similar processing. Therefore, the circuit scale becomes large and it is difficult to reduce the circuit scale.

Therefore, according to the present invention, the edge detection processing section which is a part of the motion detection processing and the field interpolation processing section which is a part of the reproduction processing circuit of the video and moving image signal share the same functional circuit. The purpose is to reduce the circuit scale and improve the accuracy of edge detection.

[0030]

To achieve the above object, the present invention demodulates a MUSE signal band-compressed by sub-samples that make a cycle of four fields into an original broadband high-definition television signal and reproduces it. A MUSU decoder for performing motion detection, an edge detecting means for obtaining an edge signal from a difference value of image data in a predetermined range in a field, and an in-field for interpolating image data in the field. One or a plurality of the circuit blocks in the MUSE decoder motion detection circuit, each of which includes one or a plurality of circuit blocks having the same function in each of the edge detection means and the field interpolation means. Is characterized in that the edge detection means and the field interpolation means share each other. Providing MUSE decoder motion detection circuit according to.

The present invention also provides a MUSE decoder motion detection circuit, wherein the one or more circuit blocks are at least a line memory for image data.

[0032]

In the MUSE decoder motion detecting circuit of the present invention, the same function part as the edge detecting means included in the motion detecting processing means and the field interpolating means for performing the field interpolation for reproducing the moving picture signal. , The circuit scale can be reduced.

Further, the edge signal can be obtained from the image data in a wide range within the field and the image data at a uniform distance around the field without increasing the circuit scale.
This makes it possible to improve the detection accuracy of the edge signal required for each pixel.

Furthermore, by using the shared portion as a line memory for image data, the circuit required for edge detection can be reduced to about 30%.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, first and second embodiments of the present invention will be sequentially described with reference to the drawings.

First, the first embodiment will be described with reference to FIGS. 1, 2 and 3.

FIG. 1 is a block diagram of a MUSE decoder of the present invention, and FIG. 2 is a block diagram of a motion detection processing section of the MUSE decoder of the present invention. Both block diagrams are the same as the block diagrams shown in the conventional examples of FIGS. 6 and 7, except that the edge signal 16 from the field interpolation unit 13 is input to the motion detection processing unit 12. Therefore, description of the same parts as the conventional one will be omitted, and different parts will be mainly described.

As described in the conventional example, the motion detection processing section
The edge detection processing unit 37 and the field interpolation unit 13 in 12 perform processing using the same data. Therefore, in the present invention, as shown in FIG. 2, the edge detection processing unit 37 shown in FIG. 7 of the conventional example is deleted, and the edge signal 16 is generated by using the image data used in the processing by the field interpolation unit 13. The calculation process for obtaining is performed.

FIG. 3 is a schematic diagram showing edge detection in the field interpolating unit 13 according to the first embodiment of the present invention. FIG. 3A shows sample points and FIG. 3B shows non-sample points. )
Shown in. Since the two methods are similar, the edge detection processing at the sample points shown in FIG. When the 13 pieces of image data in FIG. 3 (A) are designated as E1 to E13, | E4-E9 |, | E2-E7 |, | E5-E10 | are obtained, and the maximum value of the three values is set to E7. Horizontal edge value, | E4−
E5 |, | E6-E7 |, | E7-E8 | are obtained, and the maximum value of the three values is taken as the value of the vertical edge of E7.

That is, the lateral edge value of E7 = MAX {| E4-E9 |, | E2-E7
||| E5-E10 |} Vertical edge value of E7 = MAX {| E4-E5 |, | E6-E7
|, | E7-E8 |}.

Similarly in FIG. 3B, the values of the horizontal edge and the vertical edge of each pixel are obtained.

Horizontal edge value of F7 = MAX {| F1-F6 |, | F4-F10
||| F2-F8 |} Vertical edge value of F7 = MAX {| F3-F4 |, | F4-F5
|, | F6-F8 |}

In this way, the edge signal 16 detected using the image data of the field interpolation unit 13 is used as the motion detection processing unit.
The signal 34 from the 2-frame difference detection processing unit 32 and the 1-frame difference detection processing unit are input to the moving image area detection processing unit 36 in the 12
It is configured to generate the motion signal 15 in combination with the signal 35 from 33.

Therefore, according to the first embodiment described above, the circuit of the edge detection processing unit 37 can be shared with the field interpolation unit 13, so that the circuit scale can be reduced. The shared portion in the embodiment corresponds to, for example, a line memory for image data.

Next, a second embodiment will be described with reference to FIGS.

As can be seen from the schematic diagrams showing an example of the field interpolation (FIG. 10) and the edge detection processing (FIGS. 8 and 9) of the conventional example, the field interpolation has more than the edge detection processing. Using the data of. By sharing the circuit of the edge detection processing section with the field interpolation section, the conventional edge detection processing is performed using the data of the field interpolation section 13 in the first embodiment (FIG. 3). In the second embodiment, the edge detection processing is performed using more data than in the conventional case.

FIGS. 4 and 5 are schematic diagrams showing the edge detection processing of the second embodiment, and the detection of the lateral edge is shown in FIGS. 4 (A) and 4 (B).
The vertical edge detection is shown in FIGS. 5 (A) and 5 (B). Since the four methods are similar, the horizontal edge detection at the sample points shown in FIG. 4A will be representatively described. Assuming that the seven image data in FIG. 4 (A) are A1 to A7, | A1-A2 |, | A
3-A4 |, | A5-A6 |, | A4-A7 |

That is, the lateral edge value of A4 = MAX {| A1-A2 |, | A3-A4
|, | A5-A6 |, | A4-A7 |}.

The values of the horizontal edge and the vertical edge of each pixel are similarly obtained in FIGS. 4B, 5A, and 5B.

Horizontal edge value of B7 = MAX {| B1-B2 |, | B3-B4
|, | B5-B6 |, | B2-B8 |, | B6-B9 |} Vertical edge value of C4 = MAX {| C1-C2 |, | C3-C4
||| C4-C5 |, | C6-C7 |} Vertical edge value of D6 = MAX {| D1-D2 |, | D2-D3
|, | D4-D5 |, | D7-D8 |, | D8-D9 |}

According to the present invention, when such edge detection processing is performed, the edge detection processing (see FIGS. 8 and 9), which is deviated from the data of the previous line in the conventional example, is reduced to a uniform distance in the periphery. It can be detected using some data.
Therefore, the accuracy of the edge signal for each pixel can be improved.

Therefore, according to the second embodiment described above, the circuit of the edge detection processing unit 37 is shared with the field interpolation unit 13, and the edge detection processing using more data than before is performed. The accuracy of the edge signal can be improved. The shared part in the embodiments is, for example, a line memory for image data.

The present invention can be applied not only to the MUSE decoder, but also to other image processing devices as long as it is a system of performing the data interpolation in the field and the edge detection by using the data in the same field. .

[0054]

As described above, according to the present invention, the circuit for the edge detection processing section, which is a part of the motion detection processing, and the circuit for the field interpolation processing section are shared. The circuit scale can be reduced, and the circuit required for edge detection processing can be reduced to about 30%.

Further, when the edge detection processing is performed, the number of data in the vertical line direction can be increased, so that the detection can be performed using the data at the equal distances around, and the detection of the edge signal for each pixel can be performed. The accuracy can be improved. As a result, the accuracy of the motion signal output from the motion detection processing unit is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

3A and 3B are schematic diagrams showing edge detection using field interpolation at sampled points and non-sampled points in the present invention, respectively.

4A and 4B are schematic diagrams showing lateral edge detection at a sampling point and a non-sampling point in the present invention, respectively.

5A and 5B are schematic diagrams showing vertical edge detection at a sampling point and a non-sampling point in the present invention, respectively.

FIG. 6 is a block diagram showing a configuration of a conventional MUSE decoder.

FIG. 7 is a block diagram showing a motion detection processing unit in a conventional MUSE decoder.

8A and 8B are schematic diagrams showing horizontal edge detection at sample points and non-sample points in a conventional MUSE decoder, respectively.

9A and 9B are schematic diagrams showing vertical edge detection at sample points and non-sample points in a conventional MUSE decoder, respectively.

10A and 10B are schematic diagrams showing field interpolation processing at sample points and non-sample points in a conventional MUSE decoder, respectively.

[Explanation of symbols]

 1 MUSE signal input terminal 3 A / D converter 6 De-emphasis processing unit 12 Motion detection processing unit 13 Field interpolation unit 15 Motion signal 16 Edge signal 17 Sampling frequency conversion unit 18 MIX processing unit 27 D / A converter 32 2 Frame difference detection processing unit 33 1 Frame difference detection processing unit 36 Video region detection processing unit 37 Edge detection processing unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H04N 11/08 11/24 7337-5C H04N 11/08

Claims (2)

[Claims] 1. A MUSU decoder for demodulating and reproducing an original wideband high-definition television signal from a MUSE signal band-compressed by sub-samples that make a cycle of four field cycles, and a field for performing motion detection processing. An edge detection means for obtaining an edge signal from a difference value of image data in a predetermined range within the field, and a field interpolation means for interpolating the image data within the field. In a MUSE decoder motion detection circuit having one or a plurality of circuit blocks performing the same function in each of the insertion means, one or a plurality of the circuit blocks are connected to each other by the edge detection means and the field interpolation means. A MUSE decoder motion detection circuit having a shared configuration. 2. The MUSE decoder motion detection circuit according to claim 1, wherein the one or more circuit blocks are at least a line memory for image data.