FI92128B - Method for the realization of the signal processing branches in an HD-MAC decoder and a circuit solution according to the method - Google Patents

Description

92128

Method for implementing the signal processing branches of an HD-MAC decoder and a circuit solution according to the method - For the purpose of determining the signal processing branches of an HD-MAC decoder and the definition of the signaling branches of the HD-5 randet

The present invention relates to a method for implementing signal processing branches from a subsampling pattern of an HD-MAC receiver-decoder to a high-definition television image, in which a video signal is input to memories, samples stored in memories are read and processed three signal processing branches, of which the first branch (80 ms branch) processes samples of image areas that are substantially stationary within the image, and the second branch (40 ms branch) processes samples of image areas with slow motion within the field, and the third branch (20 ms branch) processes 20 samples within the field of the picture areas in which the motion is fast and in which the switch controlled by the motion information switches the high-definition television picture formed by one signal processing branch at a time decode rin departure. The invention further relates to a circuit solution according to the method.

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European High Definition Television HDTV (High Definition Television) has been developed as part of the European EUREKA project. The system specifications include a proposal for an HDTV production standard that defines the presentation format of 30 programs in a studio environment, as well as a proposal for a broadcast standard. Transmission is via satellite or cable using a MAC system that is not compatible with any traditional TV system. For this reason, current receivers need a special decoder to receive the MAC-35 transmission. The HDTV studio standard has an aspect ratio of 16: 9 and comprises 1250 lines displayed at an interleaving ratio of 2: 1 (or later 1: 1) and a field frequency of 50 Hz. However, this HDTV picture must be compressed for transmission to be compatible with current receivers with a MAC decoder. The image is encoded when transmitted into a MAC-compatible HD-MAC signal by compressing the signal to a fourth part in a band-5 decompression encoder so that the original image can be restored at the receiver. The line number of the transmission signal is thus half of the original, i.e. 625 lines, and the interleaving ratio is 2: 1. For the bandwidth lowering encoder, the input signal format is currently agreed to be 1250/2: 1/50 10 Hz, but later the interleaving ratio is likely to change to 1: 1, in which case the compression must be further increased. In view of the receiver, the so-called A DATV signal that transmits information about the motion content of an image. Compression is based on controlled subsampling, which is controlled by motion information. This means that the less motion there is in the image, the higher the spatial resolution is used, and when the motion content of the image is large, the temporal resolution is increased at the expense of the spatial.

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In the above-mentioned bandwidth reduction encoder BRE (Bandwidth Reduction Encoder), the image to be transmitted is divided into blocks of 16 * 16 pixels, which are derived from one of the three image processing branches based on their motion content. Each signal introduced into the hook has its own sampling pattern. If there is no movement, the signal is controlled. 80 ms to the branch, where a subsampling pattern (decimation) is taken from each image field so that half of the pixels of the final image are transmitted. Samples are taken from each line and the decimated image 30 forms a quincunx sampling pattern. In this way, half of the compression is obtained and the other half is obtained by increasing the transmission time of one image from 40 ms to 80 ms. The name of the branch comes from this. If there are slow-moving objects in the sub-area of the image, the video signal to be compressed is directed to the 40 ms 35 branch, where the field transmission time is increased from 20 ms to 40 ms and only every other quincunx subsampled field is transmitted, i.e. every second sample is taken from every other field. . If there are fast-moving parts in the image, the 92128 3 compressible video signal is routed to a 20 ms branch, where the bandwidth is reduced by a quarter so that every fourth sample of each original image field is transmitted, i.e. there are samples from each line of the original image. Each branch of the 5 BREs has its own low-pass filter and a so-called "line shuffling" function, in which the format of the 1250-line image (line duration 32 με) is made compatible with the MAC system 625 lines (line duration 64 με) as the format. In the 40 ms branch, this function is included in the 10 subsamples themselves. According to the information provided by the motion detector, a switch is controlled which connects only one branch at a time to the output of the BRE. This information, in which branch the output signal is generated, is encoded in a DATV signal, according to which at the receiving end the encoder directs the signal to the correct 15 branches.

In the HD-MAC decoder of the receiver, the compressed picture 625/2: 1/50 Hz must be restored to the original HDTV format, ie 1250/2: 1/50 Hz. The decoder can be called a Bandwidth Restoration Decoder (BRD) and is analogous to the BRE described above.

The BRD processes video signals and DATV data. Decisions on video signal processing in the branch, the so-called branch decisions, and the motion vectors are transmitted in the DATV signal during the vertical-25 shutdown period. In addition, information about the mode of operation (television or film mode) is transmitted. The DATV decoder separates the block decisions and motion vectors from the encoded DATV signal and transfers them to the video signal processing blocks. The BRD decoder will now be described in more detail with reference to Fig. 1, in which the luminance-LUM and chrominance processing branches CHROM of the BRD are shown, and the following description relates to the luminance signal. The received sample frequency is 13.5 MHz and the output frequency of the BRD is 54 MHz. The encoder comprises a "line deshuffler" block L1, 3-6 field memories L2 connected to e.g. kas-35 cadmium, a subsampling pattern converter L3 and three interpolator branches L4, L5 and L6. Each interpolator branch produces a complete HDTV field and the output of the selected branch is switched by switch L7 to the BRD output signal. The 4 positions of switch 92128 are controlled by the motion information contained in the received DATV signal. Since the line frequency in the transmission has been reduced to 15.625 kHz, the line samples of the 20 ms, 40 ms, and 80 ms branches must be shifted to obtain the original line frequency of 31.25 kHz line-5. This operation is performed in block L1 so that 2 lines are always generated from one incoming line, so that each new line consists of every other sample of the incoming line. After the deshuffling operation, the luminans inner signal is delayed in the field memories L2. The field signal-10 lit is then processed in a sub-sample pattern converter L3 SSPC (Sub-Sample Pattern Converter), which reconstructs the original subsampling patterns using line memories. From the converter L3, the subsampling patterns are passed to branches L4, L5, and L6, where 15 original HDTV fields are formed by interpolation. In the 40 ms branch L6, the interpolation is motion compensated and utilizes the motion vectors indicated in the DATV signal. Controlled by the DATV information, the switch L7 connects one of the branches at a time to the output of the BRD, thus obtaining the original HDTV picture in the format 20 1250/2: 1/50 Hz.

In the 40 ms branch, odd fields are transmitted during two field cycles. Even fields must be interpolated from tempo-reconstructed odd fields. As a result, the SSPC L3 outputs two signals to the 40 ms branch L6 when processing even HD-MAC fields. One of the signals comprises the previous and the other the next subsampled odd field. The signals are processed in two sub-branches comprising two-dimensional spatial interpolators (series-connected quincunx and vertical interpolators) and motion compensation blocks. When odd HD-MAC fields are processed, samples of the current field enter the second sub-branch of the 40 ms branch and only this second sub-branch is used. Missing pixels in the subsampled HD-MAC field are recovered spatially by quincunx interpolators. Because odd fields contain only odd lines in the HD-MAC field, the missing even fields must be interpolated. When the vertical component of the motion vector is even, the output from these interpolated lines is selected. After Quincunx and vertical interpolation, motion compensation is performed with line and pixel delays controlled by motion vectors. Finally, the outputs from the motion compensation blocks are averaged over a 40 ms interpolation branch in television mode, while in film mode, even fields are formed from the previous odd field, generating two fields from a single image. The output of the 40 ms interpolation branch yields interpolated even and odd-10 mat fields, which are combined to produce an HDTV image.

The 20 ms branch normally comprises two cascaded interpolation filters; quincunx and horizontal interpolator. The Quincunx interpolator produces an orthogonal-15 image comprising a line of 720 active samples, the number of which is doubled by the horizontal interpolator. The 80 ms branch comprises a quincunx interpolator that produces either even or odd fields from the subsampled fields.

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The chrominance signal is encoded in essentially the same way as the luminance signal, although chrominance processing is slightly simpler than luminance processing. However, motion compensation is not used in the 40 ms branch and the DATV signal generated in the luminance 25 processing is also used in the Kro-minance coding. Since the processing of the chrominance signal is essentially similar to the processing of the luminance signal, the chrominance signal processing branch CHROM will be described very briefly below with reference to Fig. 1.

The received sample frequency of the chrominance signal is 6.75 MHz comprising both chrominance components U, V and the output frequency of BRD for each chrominance component U, V is 27 MHz, in which case they are transmitted separately in alternating lines. The encoder comprises a "line deshuffler" block C1, 3-4 field memories-35 and C2 connected e.g. to a cascade, a subsampling pattern converter C3 (SSPC) and three interpolator branches C4, C5 and C6, to which the subsampling pattern converter C3 each produces one signal. Each interpolator branch produces a complete HDTV field and the output of the selected branch is switched by switch C7 to the BRD output signal. The position of the switch is controlled by the motion information contained in the received DATV signal.

5 The signal from the BRD can be further processed to increase its display frequency, as the low field frequency causes harmful white field flicker and 2: 1 interleaving line flicker, which are overcome by increasing the display frequency. There are two basic ways to increase the display frequency. The field frequency can be increased to, for example, 100 Hz, in which case the format is 2: 1/100 Hz, or the interleaving can be removed, i.e. the image is made progressive, for example, to 1: 1/50 Hz. Methods can be divided into methods that do not use motion information, motion adaptive methods, and motion compensated methods.

Thus, for the transmission of an HDTV image, the pixels to be transmitted are arranged so as to provide a signal corresponding to a normal MAC-tele-20 vision image. The arrangement of the pixels causes some visible errors when viewing an HD-MAC signal on a standard MAC receiver. To eliminate these errors, a temporal compatibility enhancement circuit, 25 TCI (Temporal Compatibility Improvement) module, has been added to the bandwidth recovery decoder BRD, which is denoted TCI in Figure 1. In addition, a Motion Compensated Compatibility Improvement (MCCI) circuit has been added to the BRD, which is denoted MCCI in Fig. 1, respectively. The TCI and MCCI loh-30 homes in the HD-MAC encoder BRE improve the quality of the compatible standard definition image. In the BRD, the TCI and the MCCI perform an inverse conversion to the corresponding functions performed in the encoder BRE. After TCI and MCCI, the video signals are processed in the same way as in the normal MAC system 35 (BRD). The MAC encoder BRE thus converts the video information, i.e. the digitally encoded DATV signal and audio, into an analog signal which can be transmitted via satellites or cable channel and on the receiver side. The MAC encoder BRD converts the analog signal received via the satellite back into a digital video signal. This signal can be displayed by MAC receivers with normal color accuracy without any additional equipment. In addition, the decoder 5 separates the DATV signal and the audio from the video signals. In the HD-MAC receiver, TCI'1 and the BRD transmission decoder return the high definition picture to the original. The missing pixels are formed on the basis of the transmitted pixels and the correct interpolation method (20, 40 or 80 ms branch) is selected on the basis of the motion information transmitted by the 10 DATV signals.

When the HD-MAC signal is viewed on a standard MAC receiver, interfering flicker at 12.5 Hz occurs in still parts of the image. To reduce this flicker, a temporal compatibility enhancing circuit TCI has been added to the transmission chain, the filtering method of which is performed only for the luminance signal and only for the signals processed in the 80 ms branch, and is the same for both even and odd fields.

At the transmitting end, temporal attenuation is performed between two fields 40 ms apart, for which two field memories L8 are required (Fig. 1), which can be used as known to be the field memories L2 of the SSPC L3, thus saving memory circuits. Because high frequency components cannot be displayed on the MAC receiver, attenuation is not performed for high horizontal frequencies. Therefore, the difference signal between the fields is filtered by a low-pass filter. In order not to affect the high-definition picture quality of the TCI, the temporally attenuated signal is amplified in the 30 HDTV receivers (TCI ^ decoding). This is an inverse operation for filtering at the transmission end. TCI'1 decoding is a recursive operation, i.e. the amplified signal is fed back to the filter.

The Inter Field Shuffling used in the 40 ms coding branch, called the Synthetic Interlace Technique, transmits 35 8? 2 ί l 8 two consecutive lines of the same odd HD-MAC field in two consecutive transmission fields. This technique causes artefacts, which are characterized by a kind of film effect, the so-called judder effect. The 25 Hz temporal -5 of its subsampling is characterized by said film effect. For the 40 ms compensated branch, a significant method has been implemented to achieve a good motion description of the picture to be transmitted to the HD-MAC decoder without losing the original information. This method, called motion-com pensed compatibility enhancement, MCCI, allows the judder effect to be rounded with temporal attenuation in the motion direction after bandwidth reduction (BRE), and its filtering method is applied only to the luminance signal and only to 40 ms branch-processed signals. Prior to bandwidth recovery-decoding (BRD), temporal sharpening in the motion direction must be performed in the decoder. The principle of this attenuation involves mixing the transmitted and compensated point in the direction of motion. The odd fields are transmitted 20 as they are processed in the bandwidth decoding encoder BRE. Even fields are obtained by emphasizing the field to be transmitted and the projection of the previous field in the direction of motion. The information of the previous field is obtained from the field memory L9 connected to the MCCI, in which one of the field memories L2 of the SSPC L3 can be used.

The HD-MAC decoder originally implemented in the EUREKA project requires complex blocks with a large number of interconnections and is therefore not suitable for implementation as an integrated circuit. Due to the complex implementation of the EUREKA HD-MAC decoder, a newer decoder was developed with the aim of using as few different blocks as possible, with limited complexity and more practical interfaces. This newer decoder is disclosed in International Patent Application PCT / NL91 / 00021. The decoder shown therein has reduced the number of field and line memories compared to the EUREKA decoder. It has been possible to reduce the field memory by switching the decoding branch of the 40 ms mode and the 80 ms decoding branch in succession, so that the outputs of the 40 ms interpolator are utilized in the interpolation of the 80 ms branch. In order to decode the 80 ms mode field, samples of four successively received 5 ms mode fields are in principle required. If, in temporal mode changes where the sequence of 80 ms mode fields is followed or preceded by non-80 ms mode fields, the missing samples required by the 80 ms mode interpolator are taken from the 40 ms interpolator output, the HD-MAC television decoder 10 can only cope with three field memories, such as is disclosed in said patent application PCT / NL91 / 00021, the contents of which are hereby incorporated by reference.

The implementation of the HD-MAC decoder BRD as integrated circuits has required 19 Application Specific Integrated Circuits (ASICs) even in 15 newer decoders. In particular, the motion-compensated interpolator (40 ms in the branch) is a high-surface-area circuit manufactured with current IC technology. In the decoder disclosed in said patent application-20, the central circuit is a multifunctional integrated circuit designated, according to its internal structure, as a two-dimensional filter structure TDFS (Two Dimensional Filter Structure), which in practice is a programmable signal processor. The TDFS circuit comprises four cascade line delays connected to the cascade, interpolation circuits, multiplexers connecting the line delays to form selected delays, controllable selector blocks for connecting the selected delays to the interpolation circuits, a paging control section, a control delay block parallel to the interpolation circuits, which provides control signals to the selector blocks, and an output block having a multiplier block containing the coefficients to be controlled by the control block 11a, and a summing and scaling block. The TDFS circuit is thus a general purpose circuit 35, and the decoder disclosed in said patent application was sought to be implemented while minimizing the number of different types of circuits. Thus, the central circuit in the implementation is said TDFS-ft circuit, of which there are 11 in the decoder, of which 8 are used for interpolation of the luminance processing branch and 3 for the interpolation of the Kro-miniance processing branch. In the luminance processing branch, as many as 4 TDFS circuits were needed to implement the motion compensated interpolator of the 40 ms branch. Li-5 Saxony, because the circuit is made flexible in operation, it has also been possible to use it in other interpolation and (compensation) delay functions required in the other interpolation part of the decoder. Other integrated circuits of the decoder include subsampling pattern recovery circuits SSPCs, line memory 10s, DATV circuits, and MCCI. This patent application discloses a decoder in which the number of different types of circuits is small. However, the disadvantage of this solution is that the decoder comprises a large number of circuits (there are several circuits of the same type) and is still space-consuming in its implementation. One reason for the large number of circuits and the space-consuming solution is that the implementation of the decoder is largely based on the TDFS of the multifunction integrated circuit, whereby in certain functions a large part of its blocks remain unused and consume unnecessary space.

It is an object of the present invention to provide a method for implementing the signal processing branches of an HD-MAC decoder and a circuit solution according to the method. According to the invention, an integrated circuit is implemented in an HD-MAC receiver, which • can be operated in two different configurations so that the interpolation of the luminance branch of the BRD of the HD-MAC decoder can be implemented with only two similar integrated circuits. By using the two integrated circuits according to the invention to implement the signal processing branches of the HD-MAC decoder, a large area saving is achieved compared to the implementation of the eight TDFS circuits of the decoder according to said patent application, and the number of different types of circuits has not increased. It is also an object of the invention to provide a bandwidth recovery decoder BRD of an HD-MAC receiver comprising an integrated silicon according to the invention. and comprising only five application-specific integrated circuits.

92128 11

The invention is characterized in that at least two identical circuits are connected to each other, each comprising an interpolator of the first and third signal processing branches and an interpolator of one sub-branch 5 of the second signal processing branch.

The application-specific integrated circuit according to the invention can be implemented using fixed solutions, whereby the circuit is not a general-purpose multifunction controllable signal processor that can be implemented by control. The circuit comprises compensation delays of one sub-branch of the 40 ms motion compensated interpolator, 20/80 ms of the interpolator, and selector and summing blocks to implement two different configurations. Thus, the circuit is controllable so that in a second configuration it comprises a 40 ms second sub-branch interpolator and an 80/20 ms interpolator, and in a second configuration it comprises a 40 ms interpolator second sub-branch and the compensation delays required when using 20 80 ms as described in said patent application. in branch interpolation, 40 ms interpolator outputs, where when interpolations are performed at different times, delays are needed to compensate for the time taken for the second interpolation so that the interpolated fields are output to the decoder simultaneously.

• The invention will now be described in detail with reference to the accompanying drawings, in which Figure 1 shows an HDD-MAC receiver bandwidth Palau-30 decoder BRD already described, Figure 2 shows an implementation of an HD-MAC receiver bandwidth Poder-decoder BRD according to the invention as application-specific integrated circuits, Fig. 3 shows an integrated circuit according to the invention, Fig. 4 shows a block diagram comprising the main functions of an HD-MAC decoder, Fig. 921 28 12 Fig. 5 shows a block diagram of a circuit solution according to the invention, in which BRD signal processing branches are implemented with two integrated circuits according to Fig. 3, Fig. 6a shows a more detailed implementation of each of the 5 blocks of the circuit solution shown in Fig. 5, Fig. 6b shows a second embodiment according to the invention, Fig. 6c shows a third embodiment according to the invention, Fig. 6d shows a fourth embodiment according to the invention, Fig. Fig. 7 shows an alternative power consumption optimized embodiment of the circuit solution according to the invention, Figs. 8a and 8b show in more detail the switching of the switching circuits of the circuit according to Fig. 7, and Fig. 9 shows another embodiment of the integrated circuit according to the invention for use according to Figs. .

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Figure 2 shows an implementation of the HDD MAC receiver bandwidth recovery decoder BRD according to the invention as application-specific integrated circuits. Chrominance and DATV processing are each performed by a separate circuit CHROM and 25 DATVs, and the chrominance processing circuit CHROM further uses external field memories C2, whereby the incoming signal 1 is initially routed (according to reference 2) to the field memories C2 and , 4, 30 5. The processed U and V components 6, 7 are obtained as the output of chrominance processing. The DATV circuit performs DATV decoding as well as the control functions of the other circuits of the BRD. These control functions include, for example, timing of other circuits, control of motion vector and branch decision information to the circuits, and control of additional functions such as still image or noise reduction. The luminance iproses the initial part of the tone, i.e. the TCI, MCCI, line. the "deshuffler" LI and SSPC L3 are connected to one circuit LUMI. The remainder of the luminance processing, i.e. the 92128 13 interpolators of 80, 40 and 20 ms, are implemented with two identical circuits LUM2.

For the LUMI circuit, 3-6 field devices L2 are used, which are implemented on a separate circuit LUMI. These memories can be used in a separate implementation to replace the two field memories L8f required by the TCI and the one field memory L9 required by the MCCI and the 3-6 field memories L2 required by the SSPC L3. In this case, the outputs of the field memories L2 connected to the input L3 of the SSPC are recursively connected to the second inputs of the TCI and the MCCI.

Using the four field memories, noise and drop-outs can also be removed recursively, as disclosed in patent application FI-922295. In order to achieve better noise reduction, the circuit can implement noise amount and type detection in the SSPC. When selecting subsampling patterns, not all of the required points are at the inputs of the circuit, but a portion must be interpolated. Interpolation achieves good results with a simple implementation solution using four-point median interpolators. In the median interpolation of a four-to-20 point, two of the four chapters are searched for, and the result of the interpolation is the average of these. In the LUM1 circuit, a still image can be implemented simply by using existing field memories, as disclosed in patent application FI-923769. 25 It is also possible to divide a LUMI circuit into two circuits si

that the SSPC L3 is disconnected from other functions. In this case, four common field memories can still be used. For luminance processing, a 13.5 MHz signal is input to the LUM1 circuit (Ref. 8), as described in connection with Figure 1. From the "deshuffler" block of the line LI

transmitting the signal 9 to the cascaded field memories L2, from which the information of the fields required for the SSPC block L3 is obtained, and from the SSPC block L3, the subsampled figures 14-17 are obtained to the interpolation branches L4-L6, and a 54 MHz signal is obtained as an output, which can also be given as two 27 MHz signals 20, 21.

92128 14

The interpolations are implemented using the integrated circuit LUM2 according to the invention with two different configurations LUM2a and LUM2b. The circuit LOM2 is shown in Figure 3. The circuit LUM2 has three data inputs a, b and c and two data outputs n and o, each of which is 8 bits wide at a frequency of 27 MHz, which is also the internal clock frequency of the LUM2 circuit. There are one or more control inputs / outputs, as shown in Figure 3. The 20 ms L4 and 80 ms L5 interpolators are implemented in the same block. The 40 ms interpolator L6 is connected in series before the 10 20/80 ms interpolator block, whereby the outputs of the 40 ms block can be used for 20/80 ms interpolation, as shown in Figure 4. In this way, the 20 / The result of 80 ms of interpolation in the edge areas of the image blocks containing different motion decisions, while saving the number of memories, as disclosed in patent application PCT / NL91 / 00021. The 40 ms interpolator L6 is known to comprise two identical motion-compensated sub-branches L6 ', of which only one is used in the non-motion-compensated state when interpolating odd fields. In the interpolation of even Kent-20 paths, the second sub-branch L6 'calculates the counterpoint from the previous and the second L6' from the next field, and the averaging of these counterparts is then performed to produce an interpolated sample. Since the implementation of the sub-branch L6 'of the motion-compensated interpolator L6 requires a large surface area with 25 integrated circuits, it is preferable to divide the motion-compensated sub-branches L6' into two different circuits. Since the sub-branches L6 'are identical in structure, they can be implemented with two identical circuits LUM2. Since the 20/80 ms interpolation L4, L5 is performed after the 40 ms interpolation 30 L6, compensation delays corresponding to the delay of 40 ms in the block L6 are needed to compensate the outputs of the 20/80 ms branch of the COMP SSPC L3 so that the signals 14 -17 is obtained simultaneously for 80/20 ms interpolator L4, L5. The area of the circuit can also be reduced by using line reference structures (not shown) in the 20/80 ms interpolator L4, L5 to provide 35 compensation delays in addition to the separate convergence delays COMP. The interpolators disclosed in patent applications FI-904 716 and FI-904 717 can be used for interpolation from the quincunx sampling pattern in all motion steps. As disclosed in patent application FI-914 782, the outputs of the circuits in the form of a quincunx sampling pattern can be arranged in the interpolators by changing the values of the control signals corresponding to the motion vectors in a 40 ms branch according to the quincunx sampling pattern either one pixel up or down. In the 20 ms branch, the output signal comprising the quincunx sampling pattern can be provided by controlling the inputs and outputs of the line memory path 10, and in the 80 ms branch, the output of the SSPC is obtained directly in the form of a quincunx sampling pattern.

At the input a 15 of the integrated circuit LUM2 according to the invention, the subsampling pattern of the second sub-branch L6 'of the 40 ms interpolator L6 of the SSPC L3 and the subsampling pattern of the second sub-branch L6' are directed to the input a (even fields) of the second LUM2 circuit, respectively. Inputs b and c are supplied with the 20 subsampled patterns required for 80/20 ms interpolation L4, L5. The 40 ms interpolation branch L6 performs 40 ms mode interpolation as well as motion compensation during even field processing. The 20/80 ms block L4, L5 processes either 20 or 80 ms interpolation depending on the branch decision of the luminance processing.

The 80/20 ms block L4, L5 also includes a delayed and non-delayed switching capability for some of the operating modes of the circuit LUM2. Direct bypass is used when you do not want to use the line memories of the block to compensate for delays. A delay size corresponding to 80/20 ms processing is used in 30 pass-throughs when the outputs of the block are connected directly to the outputs of the BRD and the processing mode is in the branch for 40 ms. The compensation delay block COMP contains a delay corresponding to a processing delay of 40 ms for two 8-bit data lines. If the circuit implements the most optimal solution in terms of area 35 (connection according to Figure 3), the line structures contained in the 80/20 ms block can be used as part of the compensation water in some operating modes of the circuit, whereby the 80/20 ms block delay structures can be utilized at maximum size and 921 28 16 the size of the compensation delay block COMP can be reduced accordingly by the size of said delays.

Figure 5 shows the circuit solution according to the invention roughly in two blocks: an assembly formed by two integrated circuits LUM2 operating in substantially two different configurations LUM2a, LUM2b according to the invention. As described in connection with Figure 3, the LUM2 circuit has three inputs a, b, c and two outputs n, o and one or more inputs for the control signal. The interpolation part of the BRD can be implemented with two LUM2 circuits. They can be connected to each other in several different ways, but in terms of area, the most optimal structure of the circuit is shown in Figure 3, whereby the circuits can be connected to each other according to Figure 5 to implement interpolation with a minimum number of inputs and outputs. The control block CTRL shown in Fig. 3 controls the interpolator blocks L4, L5, L6 'and the selector members V1-V3 to implement two different configurations LUM2a and LUM2b. With the correct control, both configurations are implemented, whereby the input 14 of the subsampling pattern from the converter SSPC L3 to the second sub-branch L6 'of the interpolator L6, hereinafter referred to as sub-branch "a", is introduced into the circuit of the second configuration LUM2a. input 18, 19 is obtained as outputs 18, 19 of the circuit LUM2b implementing the second configuration 25 of the LUM2 circuit and outputs of the BRO, i.e. a 54 MHz video signal corresponding to an HDTV image as two 27 MHz signals 20, 21 are obtained as outputs of the LUM2a configuration. 54 MHz signal. Input 15 of the subsampling-30 converter SSPC L3 of the circuit of the second configuration LUM2b is supplied to another sub-branch L6 'of the 40 ms interpolator L6, hereinafter referred to as sub-branch "c", preferably inputs of the next field, and 20 ms and 80 For the ms branches, the subsampled patterns and outputs 18, 19 are applied to the inputs of the circuit according to the configuration LUM2a of the other configuration. The circuit according to the configuration LUM2a performs the interpolation of the second sub-branch L6 '(previous field) of the 40 ms interpolator L6 and the interpolations of the 80/20 ms branches. Configuration 92128 17 LUM2a does not use the compensation delay block COMP. The circuit of the second configuration LUM2b performs interpolation of the second sub-branch L6 '(next field) of the 40 ms interpolator L6 and 5 delays of 40 ms processing time on the delay block COMP, possibly utilizing 80/20 ms internal interpolator line line structures (not shown). The 80/20 ms interpolator block L4, L5 is not used for interpolation in the LUM2b configuration, but has feedthroughs where it can be bypassed by control, or its 10 line delay structures can be used for delay compensation, as already mentioned.

Figures 6a-6d show a roughly more detailed block diagram of the circuit LUM2 in different configurations LUM2a and LUM2b.

In connection with the descriptions of the functions roughly shown in Figures 6a-6d, reference is made mainly to Figure 3 to illustrate the signal transitions in the circuit LUM2 and the interpolation operations, since Figures 6a-6d mainly show the blocks used in the various functions of the circuit LUM2 according to the invention.

Figure 6a shows a more detailed block diagram of the implementation of the interpolation part (consisting of circuits LUM2a and LUM2b) shown in Figure 5 according to the invention with different configurations of circuit LUM2 LUM2a and LUM2b. In the configuration LUM2a, a 40 ms interpolation block L6 'and an 80/20 ms interpolation block L4, L5 are used. In addition, a selection and summing member VI, an attenuation member V2, a selection member V3 (shown in Fig. 3) and a control block 30 CTRL, which controls the integrated circuit LUM2 according to the invention to said configuration LUM2a, are desirably used to transmit the signal. In the configuration LUM2b, the 40 ms interpolation block L6 'and the compensation delay block COMP are mainly used. In addition, selector elements VI-V3 are used for transmitting signals, as well as a control block CTRL 35 for controlling the integrated circuit LUM2 according to the invention to said configuration LUM2b. At the same time, Fig. 6a shows the operation of the interpolation section LUM2a, LUM2b during the processing of the even fields of the 40 ms branch when the film mode is not

_ - I

> 21 28 18 used, as well as 80/20 ms during branch processing. The circuit LUM2b then calculates the next field "c" of the 40 ms interpolation and executes the compensation delay COMP. The selection element V2 directs the signals f and g directly to the outputs j and k 5 (Fig. 3). The implementation can be area optimized, whereby part of the compensation delay is formed by the line delays of the block L4, L5 of 20/80 ms. On the basis of the branch decision information, the selection element V3 selects the signals d and e at the outputs n and o 40 ms in the case of a branch decision, otherwise delayed signals f and g 10 or in the compensation delay block COMP and 80/20 ms interpolation mode blocks L4, L5 delayed signals 1 and m. ms interpolation previous field "a" and 20/80 ms interpolation. In the selection / summing block VI, the inputs b and c and the signals d 15 and e are averaged if the branch decision is 40 ms and the even fields are processed and the film mode is not used. With a branch decision of 20/80 ms, signals b and c are routed directly via selection elements VI and V2 to the 80/20 ms interpolator L4, L5. The inputs h and i or f and g of the selection element V2 are fed directly to j and 20 k and in the selection element V3 1 and m to the outputs n and o. If the image block to be processed is in the 40 ms mode, only the compensation delay is performed in the 20/80 ms interpolation processing block L4, L5.

Figure 6b shows the main features of the operation of the LUM2 circuit during the processing of the odd fields of the 40 ms branch, using only the second sub-branch L6 'of the 40 ms interpolator, and during the film mode, when 80/20 ms interpolation can also be performed. The circuit LUM2b then performs only 30 a compensation delay COMP, which can be formed in part by line delays in the interpolation block L4, L5 for 20/80 ms. The selection element V2 directs f and g to j and k and the selection element V3 to the outputs n and o of l and m (Fig. 3). When processing odd fields, only the samples of the current field "b" are used, in which case a second sub-branch L6 'of the interpolator L6 of 40 ms is sufficient for interpolation, and then the circuit LUM2a performs an interpolation of 40 ms without motion compensation, and not the 40 ms interpolation block L122 of the circuit LUM2b. 'not used at all. The selection element VI selects inputs b and c at its outputs h and i in the case of a branch decision of 80/20 ms and signals d and e in the case of 40 ms (Figure 3). The selection element V2 directs h and i to j and k and the selection element V3 to the outputs n and o of 5 l and m. If the image block to be processed is in the 40 ms mode, only the compensation delay is performed in the 20/80 ms interpolation processing block L4, L5.

Figure 6c shows an alternative embodiment of the operation of 40 ms branch odd field processing, during film mode and 80/20 ms during interpolation. The LUM2b circuit operates as in the case of Figure 6a, except that no motion compensation is performed in the 40 ms branch L6 '(because it involves processing odd fields). The LUM2a circuit performs only 80/20 ms interpolation L4, L5, whereby the selection element VI controls b and c to h and i and the selection element V2 to control h and i to j and k. The selection element V3 directs l and m to the outputs n and o (Fig. 3). If the image block to be processed is in the 40 ms mode, only the compensation delay is performed in the 20/80 ms interpolation processing block L4, L5.

Figure 6d shows another alternative embodiment 25 in operation of 40 ms branch odd field processing during film mode and 80/20 ms during interpolation. The LUM2b circuit performs all interpolations L4, L5, L6 'and the compensation delay COMP. For 40 ms interpolation, L6 'does not use motion compensation. In the configuration, LUM2b then selects the selection element VI as d and e for lux and i (Figure 3).

Depending on the branch decision of the image block at its outputs j and k, the selection element V2 selects the signals h and i in the case of 40 ms and the signals b and c in the case of 20/80 ms (i.e. the signals f and g). The selection element V3 directs l and m to the outputs n and o. If the image block to be processed is in the 40 ms mode, only the compensation delay is performed in the 20/80 ms interpolation processing block L4, L5. In the circuit LUM2a, the inputs b, c are directed directly to the outputs n, o, whereby the selection element V2> 2128 20 selects the signals b and c as j and k and the selection element V3 directs l and m to the outputs n and o.

The alternative embodiments shown in Figures 6c and 6d are necessary if it is desired to optimize power consumption, in which case only the active blocks are running and the others are switched off. These various embodiments are achieved by controlling the LUM2 circuit to implement those different LUM2a and LUM2b configurations as described above. By using the embodiments shown in Figs. 6b-10d by alternating them in a suitable order, the power consumption of the circuits LUM2a and LUM2b can be equalized with each other. In the embodiments shown in Figures 6c and 6d, the SSPC L3 exchanges the values of its 40 ms branch outputs with each other because only the 40 ms interpolator second sub-branch L6 'is used to process the odd fields and usually the SSPC L3 outputs to the upper sub-branch L6', i.e. the embodiments shown here. for circuit LUM2a, while in Figures 6c and 6d, 40 ms interpolation is performed in the lower circuit LUM2b. Alternatively, as described above, the functions of the upper and lower LUM2 circuits may be interchanged, so that in the case of Figures 6c and 6d, 40 ms interpolation would be performed in the upper LOM2 circuit, and the SSPC L3 does not need to exchange its output values with each other.

25

The embodiments shown in Figures 3-6 are optimized in terms of surface area and number of input and output terminals, although Figures 6a-6d showed alternative embodiments to optimize power consumption. Alternative embodiments of the circuit solution according to the invention for optimizing power consumption are presented below with reference to Figures 7-9. In these embodiments, however, the number of input and output terminals and the area of the integrated circuit LUM2 according to the invention increase.

Fig. 7 shows the connections between the LUM2 circuits in the power consumption optimizing embodiment, when the internal modes of operation of the LOM2a and LUM2b circuits correspond to the functions shown in Figs. 6a-6d. The operation and implementation of the LUM2 circuit 92128 21 thus remains substantially similar to the implementation according to Figure 3. Only one selector member has been added, as shown in Figure 9.

5 The idea in the alternative shown in Figure 7 is to equalize the power consumption of two identical circuits LUM2 by reversing the processing order of the circuits every two (or possibly 4, 8 ...) processed fields so that one LUM2 circuit is not substantially loaded more than the other. That is, if the upper LUM2 circuit shown in Fig. 7 first performs e.g. the functions of the LUM2a circuits shown in Figs. 6a-6d and the lower LUM2 circuit performs the functions according to the LUM2b circuits of the respective figures (Fig. 8a), said upper and lower circuits are switched. LUM2 circuit functions to each other such that after two (or 4 or 8 ...) processed fields, the upper LUM2 circuit performs functions according to the LUM2b configuration and the lower LUM2 circuit performs functions according to the LUM2a configuration ( Figure 8b). During the odd fields, only one 40 ms interpolation 20 line L6 'is processed, whereby the second branch L6' can be turned off completely to reduce power consumption, as shown in Figure 6d. The functions can be switched because the LUM2a and LUM2b configurations are implemented with two identical LUM2 circuits. In addition, the power consumption can be reduced by always turning off the passive 20/80 ms interpolation block of the second LUM2 circuit (which is not used for interpolation).

In Figure 7, the lines 18, 19 between the LUM2a and LUM2b circuits are bidirectional. The outputs 20, 21 of both circuits are connected to the same output lines. When one circuit produces output data, the outputs of the other are set to the high impedance state. The number of input and output terminals thus increases as power consumption is optimized.

Figure 9 shows an implementation of the integrated circuit LUM2 according to the invention in the circuit according to Figure 7 in order to optimize power consumption. The implementation is very similar to Figure 3; only an additional optional member V4 and two additional inputs have been added to the input. Two outputs have been added to the selector V3. In addition, the circuit has an input / output buffer (not numbered) into which two bidirectional lines 18, 19 enter, i.e. through which two input signals 18, 19 can be received or two output signals 18, 19 can be given. Thus, two bidirectional lines have had to be added to the LUM2 circuit. The circuit of Figure 9 operates as the circuit of Figure 3 in the embodiments of Figures 6a (even fields) and 6b (odd fields, or 6c or 6d). The main difference 10 is that the LUM2 circuits switch operating modes with each other every 2 (or 4, 8 ...) fields. The change of mode is performed by selector elements VI and V4, which are controlled by the control block CTRL. If the circuit LUM2 is in the state LUM2a, the selection element VI selects the inputs 18 and 19 and 15 for the signals b and c as the outputs 20 and 21 as the active outputs of the selection element V4.

If the circuit is in state LUM2b, the selection element V1 selects inputs 16 and 17 for signals b and c and the selection element V4 selects outputs 18 and 19 as active outputs. Each circuit sets the passive outputs to the high impedance state. When switching operating modes, the SSPC exchanges the values of its 40 ms branch outputs with each other.

Another alternative to reduce circuit-specific power consumption is to perform interpolations using three interconnected integrated circuits according to the invention, wherein one LUM2 circuit uses either a 40 ms interpolator L6 'or an 80/20 ms interpolator L4, L5 or neither, but not both. That is, one circuit performs 40 ms interpolation of the second sub-branch L6 '30, another circuit performs 40 ms interpolation of the second sub-branch L6', and the third circuit performs 80/20 ms interpolation L4, L5, and if any of these circuits are not used or part of the circuit is not used, the circuit in question or that part of circuit 35 is turned off. Similar to the implementation of the two LUM2 circuits, the implementation of the three LUM2 circuits equalizes the power consumption of the LUM2 circuits with which the interpolation of the second sub-branch L6 'of the 40 ms interpolation is performed. Especially then.

23 921 28 when processing odd fields, in which case only the second sub-branch L6 'is used in the 40 ms processing, the power consumption of the circuits is equalized by alternating the use of the circuits appropriately.

5

The circuit solution according to the invention, in which the interpolations of the HD-MAC decoder are performed by two integrated circuits LUM2 according to the invention with about 350,000 transistors, achieves considerable space savings compared to the use of eight TDFS circuits disclosed in PCT / NL91 / 00021. there are about 240,000 transistors in the circuit.

The HD-MAC decoder is now implemented with five integrated circuits (four different types of circuits), while as many as 19 integrated circuits (six different types of circuits) have been used in the solution of said patent application. Thus, the solution according to the invention brings considerable cost and space savings in the implementation of an HD-MAC decoder.

Claims (20)

A method of realizing the signal processing branches (L4, L5, L6) that process a sub-sample pattern of an HD-MAC decoder into a high-resolution image, in which HD-MAC decoder - a video signal is fed to memories (L2), - samples stored in memories (L2) are read and processed so that the original transmitted sub-sample pattern is formed, - the formed sub-sample pattern is led into three signal processing branches (L4, L5, L6), of which the first branch (L5) processes internally in the image. samples of image areas which are substantially stationary, and the second branch (L6) processes internally in the field samples of image areas in which movement is slow, and the third branch (L4) processes internally in the field samples of image areas, in which the motion is rapid, and - the high resolution image formed by a signal processing branch (L4, L5 or L6) is coupled at the thread to the output of the decoder with a switch (L7) controlled by the motion information (L7), characterized in that - At least two circuits (LUM2) coupled Tili each other, each of which comprises an interpolator (L4, L5) of the first and third signal processing branch and an interpolator (L6 ') of the second signal processing branch (L6) one under-crotch. 25 Method according to claim 1, characterized in that the circuits (LUM2) are identical. Method according to claim 1, characterized in that the circuits are connected to each other such that - the sub-sample pattern (16, 17) of the first and the third signal processing branch (L4f L5) and the sub-sample pattern (15) is retrieved by the one sub-branch (L6 ') of the second signal processing branch (L6), and 35. to the second circuit (LUM2a), the sub-sample pattern (14) is retrieved by the second sub-branch (L6') of the second signal processing branch (L6 ') and the first circuit (LUM2b) outputs ( 18, 19), and 92128 31 - the high resolution image is obtained from the outputs of the second circuit (LUM2a) (20, 21). Method according to claim 3, characterized in that, in processing the even field of the second signal processing branch (L6) and the sub-sample pattern of the first and third signal processing branch (L4, L5), - processing of the sub-sample pattern is carried out in the first circuit (LUM2b). one sub-branch of the second branch (L6), and - in the second circuit (LUM2a) processing the sub-sample pattern of the second branch (L6) second sub-branch (L61) and processing of the first and third signal processing branch (L4, L5) sub-sample patterns. 15 Method according to claim 3, characterized in that in processing the odd field of the second signal processing branch (L6) and the sub-sample pattern 20. of the first and third signal processing branch (L4, L5), processing of the sub-sample pattern by the second circuit (LUM2a) is performed. second branch (L6) one sub-branch (L6 ') and processing of the first and third signal processing branch (L4, L5) sub-sample patterns. Method according to claim 3, characterized in that, in processing the odd field of the second signal processing branch (L6) and the sub-sample pattern of the first and third signal processing branch (L4, L5) - processing of the sub-sample pattern in the first circuit (LUM2b) one sub-branch (L6 ') of the second branch (L6) and processing of the sub-sample pattern of the first and third signal processing branches (L4, L5). Method according to claim 3, characterized in that in processing the odd 3 fields of the second signal processing branch (L6) and the sub-sample pattern of the first and third signal processing branches 412 (L4, L5) 92128 32 - it is carried out in the first circuit. Processing (LUM2b) processing of the sub-sample pattern of one sub-branch (L6) one sub-branch, and - in the second circuit (LUM2a) processing of the sub-sample pattern 5 of the first and third signal processing branches (L4, L5). Method according to Claim 3, characterized in that the delay compensation element (COMP) contained in the circuit (LUM2) is performed delay compensation. Method according to Claim 8, characterized in that the delay compensation is carried out in part with the line delay element of the first and third signal processing branches (L4, L5). Method according to any of claims 3-7, characterized in that the sub-sample pattern (16, 17) of the first and third signal processing branches (L4, L5) and the first circuit (LUM2b) are also retrieved (LUM2b). ), the outputs (18, 19) of the second circuit (LUM2a) are also retrieved. Method according to claim 10, characterized in that the high-resolution image fds is output from the outputs (20, 21) of the second circuit (LUM2a) and outputs (20, 21) of the first circuit (20, 21) in a high impedance state. Method according to claim 10, characterized in that the function of the first (LUM2b) and the second (LUM2a) circuit changes; It is contemplated that the first circuit (LUM2b) performs the functions of the second circuit (LUM2a) mentioned in any of claims 4-7 and the second circuit (LUM2a) performs the functions of the first circuit (LUM2b) mentioned in any of claims 4-7, Wherein the high-resolution image is affixed from the outputs (20, 21) of the first circuit (LUM2b) and outputs (20, 21) of the second circuit (LUM2a) in a high impedance state. 921 28 33 Method according to claim 1, characterized in that three circuits (LUM2) are connected to each other such that - to the first circuit (LIJM2), the sub-sample pattern of the second signal processing branch (L6) is one sub-branch 5 (L6 '), - to the other circuit (LUM2), the sub-sample pattern is retrieved by the second sub-branch (L6 ') of the second signal processing branch (L6), and - to the third circuit (LUM2), the sub-sample pattern of the first and third signal processing branch (L4f L5) and the first and second circuits (L6) are retrieved. LUM2) outputs, and - the high resolution image is captured from the outputs of the third circuit (LUM2). A circuitry for the signal processing branches (L4, L5, L6) processing a sub-sample pattern of an HD-MAC decoder into a high-resolution image, which comprises HD-MAC decoder - memories (L2), in which a desired number of received samples can be stored, a sub-sample pattern reset circuit (L3) that reads the samples stored in memories (L2) and forms the original transmitted sub-sample patterns under the control of a motion information connected to the received signal (DATV (L4, L5, L6), of which the first branch (L5) processes internally in the image samples of image areas which are substantially stationary, and the second branch (L6) processes internally in the field samples of image areas, in which the movement is slow , and the third branch (L4): internally processes in the field samples of image areas in which motion is rapid, and to which signal processing g cleans the formed sub-sample pattern is controlled at the base of the motion information (DATVj, and 35. a switch (L7) controlled by the motion information (DATV), which switches a signal formed by a signal processing branch (L4, L5 or L6)) into the thread to the decoder output. , characterized in that it comprises 34 921 28 - at least two interconnected circuits (LUM2), each of which comprises an interpolator (L4, L5) of the first and third signal processing branches and an interpolator (L6 ') of the second one branch of the signal processing branch (L6). Circuit device according to claim 13, characterized in that the circuits (LUM2) are identical. Circuit device according to claim 14, characterized in that it comprises two circuits (LUM2) connected to each other such that - the first circuit (LUM2b) is connected to the outputs (16, 17) of the first and third signal processing branch (L4) of the sub-sample pattern reset circuit (L4), L5) and to the output 15 (15) of one sub-branch (L6 *) of the second sample processing circuit (L3) of the sub-sample pattern reset circuit (L6), and - the other circuit (LUM2a) has been coupled to the output (15) of the other sub-branch (L6) ') of the second sample processing circuit (L3) second sample processing branch (L6) to the first circuit (LUM2b) outputs (18, 19), and - as the output of the circuit device is the second circuit (LUM2a) outputs (20, 21). Circuit device according to claim 14, characterized in that it comprises three circuits (LUM2) connected to each other such that - the first circuit (LUM2) has been connected from its inputs to the output (15) of one sub-branch (L6 ') of sub-sample the second signal processing branch (L6) of the pattern reset circuit (L3), 30. the second circuit (LUM2) has been connected from its inputs: to the output (15) of the second sub-branch (L6 ') of the second sample processing circuit (L3) sub-signal processing branch (L6) - the from its inputs, the third circuit (LUM2) has been connected to the outputs of the first and third signal processing branch (L4, L5) of the sub-sample pattern reset circuit (L4, L5) and to the outputs of the first and second circuit (LUM2), and $ έ ί ά 8 35 - as the circuit device. output is the output of the third circuit (LUM2). Circuit device according to claim 14, characterized in that in the circuit (LUM2) there are selector means (VI, V2) coupled between the interpolators (L4, L5, L61), and a control unit (CTRL) which controls the selector means (VI, V2) and the interpolators (L4, L5, L6 '). Circuit device according to claim 14, characterized in that in the circuit (LUM2) there is a compensation delay element (COMP) coupled parallel to the interpolator (L6 ') by a sub-branch of the second signal processing branch (L6) and in series with the interpolator (L4, L5) of the first and third signal processing branches. Circuit device according to claim 14, characterized in that the interpolator (L61) of a sub-branch of the second signal processing branch (L6) and the interpolator (L4, L5) of the first and third signal processing branches contain the delay elements which require constant signal processing. 21. A circuit device according to claim 14, characterized in that the circuit (LUM2) is an integrated circuit. 25