JPH0461422A - Phase synchronizing signal generator - Google Patents

Abstract

PURPOSE:To eliminate the need for an oscillator oscillating a higher frequency than a desired basic clock frequency by binarizing a triangle wave signal whose frequency is the same as that of a synchronizing clock signal at plural levels and selecting the synchronizing clock signal based on a trigger signal from a signal group of plural phases obtained as a result. CONSTITUTION:The generator consists of a frequency variable triangle wave generator 1, a phase comparator 2, a crystal oscillator 3 whose oscillating frequency is f0, level comparators 5A-5D, a square wave generator 6, an output switch 7, an output switch control section 8, an output gate 12 and a comparison voltage generating section 13. Then a triangle wave signal whose frequency is the same as that of a synchronizing clock signal is outputted, the triangle wave signal is binarized at plural levels and outputted and the synchronizing clock signal is selected based on a trigger signal from a signal group with plural phases outputted. Thus, the synchronizing clock signal with small phase jitter is obtained without using a signal whose frequency is higher than a reference frequency f0.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase synchronization signal generator that generates a synchronization clock signal synchronized with a trigger signal.

[Prior Art] Conventionally, in laser beam printers (hereinafter referred to as LBPs), the deflection position and modulation timing of the beam have been very important factors, and have a great influence on the quality of the finished recorded image. For this reason, the detection signal of the beam position detection device that detects the beam deflection position and the clock input to the laser beam modulator must always be in the same phase, and in order to generate the clock, synchronization with less jitter is required. An oscillator is required.

Conventionally, in order to obtain a phase synchronized oscillation signal with little jitter, the basic tarok frequency (fo) is required as shown in Fig. 12.
Generate a clock that is N times larger than
It is configured to be N.

In FIG. 12, 21 is a beam position detection device that outputs a detection signal for the beam indicating the beam deflection position, and 22
23 is a clock oscillator that generates a clock with a frequency (Nf, ) that is N times the basic clock frequency f0, and 23 is a l/
A D-type flip-flop (D-FF) 24 generates a reset pulse that resets the N counter and the l/n counter in synchronization with the detection signal and the clock f times N times with a time error less than or equal to the detection signal. A 1/n counter that determines the period for generating a pulse indicating that a synchronized basic clock has been detected and outputting a synchronized basic clock from beam detection, and 25 is a synchronization pulse that is the pressure of the D-FF 23. The clock that is reset and N times the output of the clock oscillator 22 is set to 1.
This is an l/N counter that divides the frequency by /N.

FIG. 13 shows a timing chart showing the operation of the conventional example.

In FIG. 13, when the synchronizing pulse b indicating the beam deflection position rises between t1 and t2, the 1/N counter 25 is first reset, the oscillation of the basic clock f is stopped, and the 1/n counter 24 is reset. starts counting. The l/n counter 24 counts the desired time from the input of the synchronization pulse until the synchronized basic clock is generated, generates a reset pulse e at timing t, and generates a reset pulse e at timing t.
3. Reset D-FF. Since the output of D-FF23 is inverted by the reset pulse of e, 17n from t4
The counter 24 stops counting, and the 1/N counter 25
starts counting and f. Outputs the clock. The maximum jitter between the basic clock f and the detection signal after t4 is (tx
-t+), so it can be suppressed to less than l/N of the period of the basic clock.

[Problem to be solved by the invention] In the above conventional example, in order to obtain the necessary basic clock f0, N
Double the clock is required. As far as the inventor knows, for example, a resolution of 240 DPI (dot perin
ch), the basic clock is approximately 1.55MHz
However, in a 600DPI device, the basic clock depends on the resolution in order to balance the vertical and horizontal directions. Also, jitter is allowed up to 178 of the basic clock period, so the original oscillation frequency is 12.4 for a 240DPI machine.
MHz, but a 600DPI machine requires 77.5MHz.

However, when attempting to use such a high frequency oscillation signal, the following problems arise.

(1) In the original oscillator, it is extremely difficult to realize a crystal oscillator that oscillates at 77.5 MHz as a fundamental wave.

(2) A crystal oscillator using an overtone mode such as 3x requires a tuning circuit such as a coil and a capacitor, which increases costs due to adjustment and additional circuits.

(3) Because the oscillation frequency is very high, this 77.5MH
The z signal becomes an unnecessary radiation component to other peripheral circuits and peripheral devices, and has an adverse effect.

(4) Since the operating frequency of gate arrays and the like is high, reliable operation is extremely difficult.

An object of the present invention is to provide a phase synchronized signal oscillator that solves the above-mentioned problems.

[Means for Solving the Problems J To achieve the above object, the present invention provides triangular wave output means for outputting a triangular wave signal having the same frequency as a synchronized clock signal;
The triangular wave signal from the triangular wave output means is outputted at two or more levels.
The apparatus includes a plurality of level comparison means for converting and outputting values, and means for selecting a synchronized clock signal based on a trigger signal from a group of signals of a plurality of phases output from the plurality of level comparison means.

[Function] According to the present invention, a triangular wave signal having the same frequency as a synchronous clock signal is binarized at a plurality of levels, and a synchronous clock signal is selected based on a trigger signal from a group of signals of a plurality of phases obtained as a result. By doing so, it is possible to obtain a synchronized clock signal with accurate frequency and less phase jitter than the conventional one (without using an oscillator or the like with a higher frequency than the desired basic clock).

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a system using an eight-phase clock signal group among the embodiments of the present invention. FIG. 2 shows the relationship between each signal group in this embodiment.

In FIG. 1, a voltage-controlled frequency variable triangular wave oscillator (VCO) I is the frequency f. The VCOL is controlled in a so-called phase-locked loop (PLL) by a crystal oscillator 3 and a phase comparator 2, which serve as a reference, and the frequency of the VCOL is the same as that of the crystal oscillator 3, and the phase is 190 degrees with respect to the crystal oscillator 3.
The relationship is maintained as follows. The triangular wave output 4 of the VCOL is compared at four levels of ■A* to V11N from the comparison voltage generator 13 as shown in FIG. 2 by four level comparators 5A to 5D, and four types of signal groups p, -p.

is formed. From this signal group, the square wave generator 6 generates an eight-phase clock signal group CLKI to CLKI8 with a duty of 50% and a phase shift of 1/8 period.

Trigger signal T input asynchronously to CLKI~8
When 1 is input from external input terminal 9, CLK whose rising part comes first after the rise of CLKI to 8 is selected from CLKI to 8.
is taken out via the output switch 7 under the control of the output switch control section 8. At this time, so that the phase change can be recognized on the side receiving the synchronization signal output, the output switch controller 8 controls the gate 12 to fix the output to Low for the first period after the change (so-called muting operation). 12.

Next, the basic configuration of the triangular wave oscillator 1 in this embodiment is shown in FIG. 5(a), and the details are shown in FIG. 5(b).

As shown in FIG. 5(a), the triangular wave oscillator includes a charge/discharge limiter 16 and a charge/discharge switch (Sco, 5oc) 1?
, a capacitor CIJ, and an output buffer 18, and as shown in FIG. 17
are resistors R4 to R13 and transistors 06 to Q14
The output buffer 18 includes resistors R1 to R3, transistors 01 to Q5, and two constant current sources.

The triangular wave is formed by charging and discharging the capacitor C1 with a constant current Ic by the charge/discharge limiter 16 controlling the charge/discharge switch]7. Switching between charging and discharging is performed by comparing the voltage vc of the capacitor CI with the comparison voltage VHL. Here, the upper limit voltage 8 and lower limit voltage 8 of VHL are V
If CC is the power supply voltage, ■@=Vcc Vst
o+1 (Pace emitter pressure of Q17) VIIEQ
I. (Base-emitter mold pressure of 018) Va=Vec
(R14+R15)XI+Vmto+t
Veto's is represented by the amplitude ΔVc'' VN-
VL= (R14+ R15) X I+ roar. Therefore, the oscillation period T and frequency f of the triangular wave are expressed as follows, where f is variable by changing Ic1-. In this embodiment, the comparison voltage VNL changes in a square waveform as shown in FIG. 5(C), and operates as a hysteresis comparator. Therefore, a differential signal obtained by dividing this amplitude with resistance is outputted from the triangular wave oscillator 1 to the above-mentioned phase comparator 2, and input from the in-phase comparator 2 to the control input terminal 17A of the charge/discharge switch 17 of the triangular wave oscillator 1. PLL operation is performed by changing the constant current Ie in the charge/discharge switch 17 according to the control signal.

The triangular wave signal used in this embodiment has no discontinuous points at all points, and the absolute values of the uphill slope and the downside slope are equal. By using such a triangular wave signal, detection measures near the discontinuity points that are required when using a signal with discontinuous points, such as a sawtooth wave, are not required, and furthermore, it is possible to eliminate the need for detection measures near the discontinuous points, such as a sawtooth wave. This has the advantage that even if the comparison levels are the same, it is possible to easily form a clock signal group with a uniform duty of 50%.

Next, the configuration of the phase comparator 2 is shown in FIG.

As shown in FIG. 6, the phase comparator 2 includes a phase detection section 61
The 0 phase detection section 61 includes a current-voltage conversion section 62, a reference comparison section 63, a current output section 64, and a reference current generation section 65, and includes resistors R46 to R49 and transistors 043 to Q.
50 and a constant current source 1, and a current-voltage converter 62
are resistors R41-R45 and transistors 039-Q
42 beats, the reference comparison section 63 has resistors R36 to R40.
, transistors 035 to 038, a constant current source 1, a capacitor C2, and a reference voltage source VjEF, and the current output section 64 includes resistors R31 to R35 and a transistor 0
Consists of 31 to Q34.

In the phase detection section 61, the differential signal pair S1/NSI from the triangular wave oscillator 1 and the differential signal pair S from the crystal oscillator 3 are detected.
2・NS2 is compared in phase, and the phase difference between the two is 190°.
Then, the voltage v0 of the capacitor C2 becomes the reference voltage V. -2, there is a constant potential difference, the error current 1A from the current output section 64 has a constant value, and the phase is stabilized. On the other hand, when the phase difference deviates from 190°, the error current Ill changes, and the value of the constant current IcT is changed by the control signal input to the triangular wave oscillator 1, and the frequency of the triangular wave oscillator l is changed to reach the above point. The phase difference is controlled to -90°.

The configuration of the level comparators 5A to 5D is shown in FIG. Each of the level comparators 58 to 5D has the same configuration, and has a reference voltage (2) for comparison. + (2)B*+vCR+VD* is the only difference, and as shown in the figure, it consists of resistors R51 to R54, transistors Q51-058.4 constant current sources 11, and bias power supply VIIAff. By establishing the relationship between v□ and vO* with respect to the amplitude of the triangular wave VTR as shown in Fig. 2, the output of each level comparator P A'' P o
The change points of each can be arranged at equal intervals, that is, at T/8. Although not shown in FIGS. 1 and 2, the level comparator also outputs an inverted output NP, (x: A-D), and the square wave generator 6 at the next stage outputs PKINPX (X: A-D).
Eight-phase signal groups CLKI to CLKI8 are generated using only the rising side of each of the eight signal groups A to D).

The output switch control section 8 whose configuration is shown in FIG. 3 latches CLKI~8 at the rising point of the trigger signal T1 as shown in FIGS. 2 and 3, and as a result L+ (s, =
1 to 8), the synchronizing signal output CLK as shown in FIG. 4 is selected by the output switch 7. Furthermore, muting is performed by the gate 12 when switching CLK.

In this embodiment, although not shown, by forming the reference current I0 of the triangular wave oscillator 1 from a bandgap voltage,
This prevents the oscillation frequency from changing due to power supply voltage fluctuations. In addition, the reference voltage VAN~V□ generated by the comparison voltage generator 13 is the output vTI of the triangular wave oscillator l.
It is formed to have a correlation with I in terms of voltage and temperature characteristics. These things make it possible to eliminate adjustments as a whole.

In the above example, the triangular waves are compared at four levels,
Although 8-phase signal groups CLKI-8 are formed, numerically when comparing N levels, a 2N-phase signal group CLKI-N can be formed. In that case, the level to be compared may be 1-+n- for the first point (3≦N), assuming that the amplitude of the triangular wave is 1. An example of N=3 is shown in 28 N FIG.

In addition, if you use the falling side of the level comparator output together with the rising side, you can generate an 8-phase signal group from only the 4 types of positive phase PA to PD without using an inverted output signal. .

Furthermore, as is clear from FIGS. 2 and 4, CL
K5 is the inversion of CLKI, similarly CIJ6
-8 are inverted versions of CLK2-4, respectively. By utilizing this fact, as shown in FIG. 9, the output switch control section 8' only needs to detect four L1 to L4.
By providing the inverting output section 71 in the output switch 7', an output equivalent to that in FIG. 2 using eight phases can be obtained with only four phases CLKI to 4.

By the way, as an example in the case of N=4, as is clear from FIG. 5, the limiter comparison voltage VHL is equal to the triangular wave signal VTI.
It has a constant phase relationship with I. Therefore, as shown in Figure 10, the level comparison is made at three points, V, , V, , V, and P,
~ Obtain the PC signal group. Then, the triangular wave oscillator 1 in FIG. 5 outputs VHL shown by the dotted line, and the level comparators 5', .about.5'. If a delay amount Δt' corresponding to the delay time (shown as Δt in Figure 1O) is given by the delay compensation circuit 15 as shown in Figure 11, the output CLKI~8 equivalent to that in Figure 2 can be obtained. can get.

In this case, when comparing levels at points near the apex of the triangular wave (V, and ve in this example), the potential difference Δ■ from the apex
,,Δve are the corresponding points in FIG. 2, Δ■o, ΔVl
Since it can be doubled compared to ll, the peak of the triangular wave becomes blunted and Δ■
, ', Δvc' can be detected, and the comparative detection operation can be performed more reliably. Furthermore, if a level comparator with the same detection capability as in Figure 2 is used, the level interval can be further narrowed as shown in vlI~■1 in Figure 1O, further reducing jitter (1716 cycles in this example). It also becomes possible.

[Effects of the Invention] As explained above, by comparing triangular wave signals synchronized with a synchronous clock signal at N levels (N = 2, 3, 4...) and using the signal group, 2N phase A signal group CLKI to 2N is obtained, and by selecting an appropriate CLK from these for the external trigger signal, a synchronized clock signal such as a frequency signal higher than the reference frequency f0 can be obtained. Since it is sufficient to use a crystal oscillator having the same frequency as the desired frequency f0, it is possible to obtain a synchronizing signal output at a lower cost even when the frequency is higher than that of the conventional method. In addition, since a frequency higher than fo is not used, there is less unnecessary radiation on the high frequency side (compared to the conventional N-divider type), and the influence on surrounding circuits can be reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a diagram showing the relationship between various signal groups in Fig. 1, Fig. 3 is a block diagram of the output switch control section, and Fig. 4 is a block diagram of the output switch control section. 5(a) is a diagram showing the basic configuration of the triangular wave oscillator, FIG. 5(b) is a diagram showing the detailed configuration of the oscillator, and FIG.
c) is a diagram showing an example of the signal waveform in the oscillator, Figure 6 is a diagram showing the configuration of the phase comparator, Figure 7 is a diagram showing the configuration of the level comparator, and Figure 8 is an example of triangular wave division. 9 is a diagram showing another example of the output switch portion, FIG. 10 is a diagram showing the relationship between various signal groups in another embodiment of the present invention, and FIG. 11 is a block diagram of the same embodiment. 12 is a block diagram of the conventional example, and FIG. 13 is a diagram showing signals of the conventional example. 8... Output switch control unit, 12... Output gate, 13, 13'... Comparison voltage generation unit, 21... Beam position detection device, 22... Crystal oscillator, 23... D type Flip-flop, 24... l/n frequency division counter, 25... l/n frequency division counter, 5', ~5'. ...Level comparator, 15...Delay compensation circuit. 1... Frequency variable triangular wave generator, 2... Phase comparator, 3... Crystal oscillator with oscillation frequency f0, 5A to 5D...
・Level comparator, 6... Square wave generator, 7... Output switch, Box Fig. 3 Fig. 4 Fig. 5 (Q) Fig. 7 1

Claims (1)

[Claims] 1) A triangular wave output means for outputting a triangular wave signal having the same frequency as a synchronized clock signal, and a triangular wave signal outputted from the triangular wave output means at two or more levels.
It is characterized by comprising a plurality of level comparison means for converting and outputting values, and a means for selecting a synchronized clock signal based on a trigger signal from a group of signals of a plurality of phases output from the plurality of level comparison means. Phase synchronized signal generator.