JPH0461352A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To form a self-alignment structure in which a short-channel effect is suppressed and a source resistance is simultaneously reduced by epitaxially growing a highly active layer on a semiconductor substrate with a temporary gate as a mask. CONSTITUTION:A resist pattern 12 is formed on a semiconductor substrate 10, an active layer 14 is formed by ion implanting, the pattern is removed, Si ions are implanted deeper than the layer 14 with a resist pattern 16 to form an active layer 18, the resist pattern is removed, a resist pattern 20 is then formed on the entire substrate, and a temporary gate 21 is formed by reactive ion etching. An insulating film 30 is formed on a region except the active layer by an ECR plasma CVD, with the gate 21 and the film 30 as masks an N<+>-type GaAs layer is selectively epitaxially grown as an active layer 22, thereby alleviating source and drain resistances. Then, the gate 21 is etched to form a space between the layer 22 and the gate 21.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a field effect transistor (hereinafter referred to as FET), and particularly to a method for manufacturing a self-lined MESFET.

[Prior Art] Schottky junction FETs, so-called MESFETs, using compound semiconductors such as GaAs have been developed. This MESFET has a simple structure and manufacturing process, making it suitable for miniaturizing the gate.The shorter the gate length, the higher the frequency of operation possible, making it ideal for integrating elements with excellent high-frequency characteristics and high-speed operation. Widely used in circuits.

However, simply shortening the gate length increases the electrical resistance of the gate, which on the contrary impedes high-speed operation and deteriorates noise characteristics. Therefore, a method has been considered to reduce the gate resistance by forming a gate with a T-shaped or mushroom-shaped cross section, with the lower part in contact with the active layer of the semiconductor being thinner and the upper part being thicker.

On the other hand, in order to increase the speed of FETs, it is important to not only miniaturize the gate but also reduce the source resistance. For this reason, a structure is generally used in which the active layer in the source/drain region is formed deeper and has a higher impurity concentration than the active layer under the gate.

Such a high concentration layer in the source/drain region is
It is desirable that it extends not only directly below the drain electrode but also to the ends of the source and drain sides of the gate.

However, in this case, misalignment between the active layer (high concentration layer) of the source/drain region and the gate becomes a problem as the gate becomes finer as described above. For this reason, self-lined MESFETs in which source/drain regions and gates are configured in a self-aligned manner are widely used.

Such self-line type ME SFET performs ion implantation of a high concentration layer using a heat-resistant gate as a mask.
There is a method of performing heat treatment to electrically activate the ion-implanted layer while leaving the heat-resistant gate as it is, or a method of forming a temporary gate and performing ion implantation of a high concentration layer using this temporary gate as a mask, and then implanting the temporary gate or the temporary gate. It is manufactured by a method in which heat treatment is performed while the inverted pattern of the gate remains on the semiconductor substrate, and a gate is formed at the position where the temporary gate existed.

In addition, a method of fabricating a self-line type FET with a gate with a T-shaped cross section by ion implantation using a simple process using a temporary gate is also used (Japanese Patent Application No.
No. 120989).

However, as the gate length is shortened in this way, phenomena called short channel effects, such as a shift of the threshold voltage to the negative side and a decrease in mutual conductance, occur.

In the case of GaAsMESFET, this is thought to be due to the current flowing through the semi-insulating GaAs under the active layer under the gate.

It is known that reducing the thickness of the highly doped layer in the source/drain region is effective in reducing this current. However, the thinning of the high concentration layer causes an increase in electrical resistance, resulting in an increase in source resistance and a decrease in mutual conductance.

Therefore, a certain distance is placed between this high concentration layer and the gate, and a layer having a thickness intermediate between the active layer under the gate and the high concentration layer in the source/drain region is placed between the gate and the high concentration layer. MESF with a so-called LDD structure with two high concentration layers
ET is used. However, there is a limit to how thin the second high concentration layer can be made for the same reason as above.

In order to create a structure that simultaneously satisfies the conflicting demands of suppressing the short channel effect and reducing source resistance by thinning the highly doped layer in the source/drain region, the highly doped layer is formed deeper than the active layer under the gate using ion implantation. Instead, a self-line type MESFET has been proposed and prototyped that is epitaxially grown on the active layer.

[Problems to be Solved by the Invention] However, the epitaxial growth described above uses selective epitaxial growth using a heat-resistant gate as a mask, and as the gate length is shortened, the gate resistance increases, which deteriorates high-frequency operation and noise characteristics. There was a problem.

The present invention has been made in view of the conventional FET manufacturing method described above, and by forming a highly doped layer using selective epitaxial growth, it is possible to simultaneously suppress the short channel effect and reduce the source resistance. By using a temporary gate instead of a heat-resistant gate as a mask for the high-frequency An object of the present invention is to provide a method for manufacturing an FET with excellent characteristics.

[Means for solving the problem] In order to achieve the above object, the FET according to claim (1)
The manufacturing method includes a first step of forming a first active layer of a predetermined conductivity type in a predetermined region of a semiconductor substrate, a second step of forming a temporary gate on this first active layer, and a second step of forming a temporary gate on the first active layer. A second layer containing high concentration impurities is placed on the semiconductor substrate as a mask.
A third step of selectively epitaxially growing the active layer of
The method is characterized by comprising a fourth step of forming a gate electrode by replacing the temporary gate with a conductive material.

In addition, in order to achieve the above object, the method for manufacturing an FET according to claim (2) includes a first step of forming a first active layer of a predetermined conductivity type in a predetermined region of a semiconductor substrate; a second step of forming a temporary gate on the active layer; and a mask for selective epitaxial growth on the semiconductor substrate in a region other than the first active layer plus the region where the source electrode and the drain electrode are to be formed. a fourth step of selectively epitaxially growing a second active layer containing a high concentration of impurities on the semiconductor substrate using this thin film and the temporary gate as a mask; and a fifth step of forming a gate electrode by replacing the .

Further, in order to achieve the above object, the method for manufacturing an FET according to claim (3) is such that in the method for manufacturing FET according to claim (1), the fourth step applies a resist covering the entire surface of the semiconductor substrate. A resist with a certain thickness remains at the bottom so that only the upper part of the temporary gate is exposed by a predetermined amount, and the cross-sectional shape is inverted tapered so that the width becomes wider from the resist surface toward the semiconductor substrate. a step of forming a groove, and a step of removing the temporary gate in this groove;
The present invention is characterized in that it includes the steps of depositing a gate material thinner than the depth of the trench on the entire surface of the semiconductor substrate processed in the step, and removing the resist.

Further, in order to achieve the above object, the method for manufacturing an FET according to claim (4) includes a method for manufacturing an FET according to claim (1), wherein the method includes a step before the first step or a step between the first step and the second step. A region deeper than the first active layer by using ion implantation into a region that includes a region where a source electrode and a drain electrode are to be formed and is a certain distance away from a region where a temporary gate is to be formed. tertiary containing high concentration of impurities
The method is characterized in that it includes a step of forming an active layer.

Furthermore, in order to achieve the above object, the method for manufacturing an FET according to claim (5) includes a first step of forming a first active layer of a predetermined conductivity type in a predetermined region of a semiconductor substrate; a second step of forming a temporary gate on the active layer; and a third step of selectively epitaxially growing a second active layer containing a high concentration of impurities on the semiconductor substrate using the temporary gate as a mask.
a fourth step of forming a gate electrode by replacing the temporary gate with a conductive material;
The method is characterized by including a step of removing or insulating the second active layer formed by selective epitaxial growth in a region other than the region to become a field effect transistor after the step or the fourth step.

[Function] As described above, the FET manufacturing method of the present invention epitaxially grows a highly active layer on a semiconductor substrate using a temporary gate as a mask, thereby realizing a self-line structure in which short channel effects are suppressed and source resistance is reduced. can.

Furthermore, after forming the high concentration layer, this temporary gate is replaced with a metal gate using a resist groove with an inversely tapered shape, so a normal low resistance metal can be used as the gate metal, and its cross-sectional shape Since it can be made into a T-shape or a mushroom shape, it is possible to reduce the resistance of the gate.

[Example] Hereinafter, a preferred example of the method for manufacturing an FET according to the present invention will be described with reference to the drawings.

Figure 1 shows the self-line type MESFE in this example.
It is a partial sectional view explaining the manufacturing method of T.

First, as shown in FIG. 1(a), semi-insulating GaA
A resist pattern 12 for forming an N layer is created on a semiconductor substrate 10 such as S, and ions such as Si are implanted to form an active layer 14. Note that in this embodiment, this active layer 14
The conductivity type is N type (hereinafter, this layer will be referred to as the N layer).

After removing the resist pattern, as shown in FIG. 1(b), a resist pattern 16 is formed on the semiconductor substrate 10, and Si ions are implanted deeper than the active layer 14 (N layer). Active layer] 8 (hereinafter referred to as N'' layer) is formed.

After that, the resist pattern 16 is removed and the
Heat treatment is performed at 0° C. to activate the ion-implanted impurities.

Furthermore, SiO2 is applied as a temporary gate film on the entire surface of the semiconductor substrate.
After forming the S I ON layer etc., a resist pattern 2 for forming a temporary gate is placed on the temporary gate film at the position where the temporary gate is to be formed.
form 0.

After the etching, as shown in FIG. 1C, using this temporary gate forming resist pattern 20 as a mask, the temporary gate rim is etched using reactive ion etching (RIE) to form a temporary gate 21.

After that, S I N % using ECR plasma CVD
An insulating film 30 such as a 5iON film is formed on the surface of the semiconductor substrate in a region other than the active layer using a lift-off method, as shown in FIG. 1(d).

Then, as shown in FIG. 1(e), an N-GaAs layer containing a high concentration of impurities is selectively epitaxially grown on the semiconductor substrate 10 using the temporary gate 21 and the insulating film 30 as masks. This N''-GaAs layer functions as the active layer 22 and has the effect of reducing source resistance and drain resistance.

Next, as shown in FIG. 1(f), the temporary gate 21 is etched by a predetermined amount by wet etching or plasma etching, etc., as shown in FIG. 1(e).
A minute space is formed between the active layer 22 (N layer) formed in the step shown in FIG. 2 and the temporary gate 21.

In this way, by going through the steps shown in FIGS. 1(a) to (f), the temporary gate and the N layer are formed on the semiconductor substrate in a self-aligned manner, and the N layer is formed on the N layer. This makes it possible to suppress the short channel effect, but in this embodiment, a gate with a T-shaped cross section is formed by going through a step of replacing the temporary gate 21 with a gate metal of low resistance. It's something you get.

That is, first, as shown in FIG. 1(g), a pair of ohmic electrodes that will become the source electrode 23 and the drain electrode 25 are formed on the active layer 22 (N layer) in the region of the active layer 18 (N layer). After that, a resist 24 covering the temporary gate 21, the source electrode 23, and the drain electrode 25 is applied to the entire surface of the substrate, and a resist of a certain thickness is applied to the bottom so that only the upper part of the temporary gate 21 is exposed by a predetermined amount. The remaining portion 26 is formed to have an inverted tapered shape whose width gradually increases from the resist surface toward the semiconductor substrate.

Hereinafter, the process of forming the reversely tapered groove 26 will be explained using image reverse photolithography as an example.

A positive photoresist as the resist 24 is spin coated onto the semiconductor substrate 10 to a predetermined thickness using a spin cord. This positive photoresist is a special resist in which a photosensitizer is added that reduces the dissolution rate in a developer under certain exposure and reverse baking conditions.

After applying this positive type resist, pre-baking is performed and initial exposure is performed through a photomask. At this time, the area where the groove 26 is to be formed is not exposed to light.

Then, reverse baking is performed under predetermined temperature conditions to stabilize the initially exposed portion of the positive photoresist.

Next, flood exposure is performed over the entire surface of the positive photoresist to increase the rate of dissolution of the unexposed portions of the resist in the alkaline developer during the above-mentioned initial exposure. As a result, the initially exposed portions become difficult to dissolve in an alkaline developer, while the positive resist in the unexposed portions during the initial exposure becomes easily soluble.

Then, only the unexposed portions at the time of initial exposure are removed by development with an alkaline developer.

Then, as mentioned above, the initially exposed portion has a lower dissolution rate in the developer than the unexposed portion, and the amount of light received by the resist at the time of initial exposure is attenuated as it gets deeper from the resist surface. As shown in Figure (g), it has a reverse tapered shape in which the width gradually increases from the resist surface toward the semiconductor substrate 10.

Further, in order to leave a resist of a certain thickness on the bottom so that only the upper part of the low gate 21 is exposed by a predetermined amount, the exposure amount in the flood exposure may be made smaller than usual.

After the inversely tapered groove 26 is formed, as shown in FIG.
A metal gate 28 is formed in the groove 26 by removing the metal using buffered hydrofluoric acid or the like, and then depositing a gate metal over the entire surface using a vacuum evaporation method or the like.

As the gate metal, for example, the well-known Ti/Pt
A low resistance metal such as /Au can be used.

Finally, by removing the resist 24 applied in FIG. 1(g), a metal gate having a T-shaped cross section is formed on the semiconductor substrate as shown in FIG. 1(j).

As described above, by using the process of this example, a low-resistance gate with a T-shaped cross section can be obtained in the container, and a self-line type MES with suppressed short channel effect can be manufactured.
However, the FET manufacturing method of the present invention is not only applicable to such a self-line type MESFET manufacturing method, but can also be used, for example, to manufacture a HEMT.

That is, in the manufacturing method of HEMT, recess etching around the gate is required when forming the gate, but the process of this example eliminates the need for recess etching, and therefore, reproducibility etc. can be improved. Become.

FIG. 2 is a partial cross-sectional view illustrating the method of manufacturing the HEMT in this example.

First, as shown in FIG. 2(a), a semi-insulating GaA
Undoped GaAs layer 12 and N-type AlG on s-substrate 11
The aAs layer 13 and the N-type GaAs layer 16 are epitaxially grown in this order. At this time, the undoped GaAs layer 12
A two-dimensional electron gas is generated on the undoped GaAs layer 12 side of the heterojunction interface formed between the N-type AlGaAs layer 13 and the undoped GaAs layer 12 .

Next, a temporary gate 21 and an insulating film 30 are formed on the N-type GaAs layer 14 in the same manner as in the MESFET example described above.

Furthermore, using the temporary gate 21 and the insulating film 30 as a mask, the N-GaAs layer containing a high concentration of impurities is formed into the N-type G.
Selective epitaxial growth is performed on the aAs layer 16.

After element isolation, ohmic electrodes and gate electrodes are formed in the same manner as in the MESFET example described above.

As described above, by using the process of this embodiment, a HEMT with reduced source resistance and drain resistance can be manufactured without using recess etching, which has many problems with reproducibility.

[Effects of the Invention] As explained above, according to the FET manufacturing method according to the present invention, a low resistance gate with a T-shaped or pine mushroom cross-sectional shape can be easily manufactured, and the short channel effect can be suppressed. This has the effect that self-line type MESFETs and the like having excellent high frequency characteristics can be easily manufactured.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the MESFET manufacturing method according to the present invention, and FIG. 2 is an explanatory diagram of an embodiment of the HEMT manufacturing method according to the invention. 10... Semiconductor substrate 11... Semi-insulating GaAs substrate 12... Undoped GaAs layer 13-N-type AlGaAs layer 14... Active layer (N layer) 26... 28... 30... Two-dimensional electron gas N-type GaAs layer active layer (N layer) Resist pattern for temporary gate formation Temporary gate active layer (N layer) N selective epitaxial growth GaAs layer trench metal gate insulator film

Claims (5)

[Claims] (1) A first step of forming a first active layer of a predetermined conductivity type in a predetermined region of a semiconductor substrate, a second step of forming a temporary gate on this first active layer, and using this temporary gate as a mask. a third step of selectively epitaxially growing a second active layer containing a high concentration of impurities on the semiconductor substrate; and a fourth step of forming a gate electrode by replacing the temporary gate with a conductive material. A method for manufacturing a featured field effect transistor. (2) a first step of forming a first active layer of a predetermined conductivity type in a predetermined region of a semiconductor substrate; a second step of forming a temporary gate on this first active layer; and a second step of forming a temporary gate on this first active layer. a third step of forming a thin film serving as a mask for selective epitaxial growth on the semiconductor substrate in a region other than the region where the source electrode and the drain electrode are to be formed; A fourth step of selectively epitaxially growing a second active layer containing a high concentration of impurities on a semiconductor substrate, and a fifth step of forming a gate electrode by replacing the temporary gate with a conductive material. A method for manufacturing a field effect transistor. (3) In the method for manufacturing a field effect transistor according to claim (1), the fourth step includes the step of applying a resist covering the entire surface of the semiconductor substrate, and exposing only the upper part of the temporary gate to the resist by a predetermined amount. a process of forming a groove in which a certain thickness of resist remains at the bottom and whose cross-sectional shape becomes an inversely tapered shape that becomes wider from the resist surface toward the semiconductor substrate; and removing the temporary gate in this groove. A step of depositing a gate material thinner than the depth of the trench on the entire surface of the semiconductor substrate treated in the step, and a step of removing the resist. Method. (4) In the method for manufacturing a field effect transistor according to claim (1), a region where a source electrode and a drain electrode are to be formed either before the first step or between the first and second steps. and forming a third active layer containing highly concentrated impurities deeper than the first active layer using ion implantation in a region a certain distance away from the region where the temporary gate is to be formed. A method for manufacturing a field effect transistor characterized by: (5) A first step of forming a first active layer of a predetermined conductivity type in a predetermined region of a semiconductor substrate, a second step of forming a temporary gate on this first active layer, and using this temporary gate as a mask. a third step of selectively epitaxially growing a second active layer containing a high concentration of impurities on the semiconductor substrate; and a fourth step of forming a gate electrode by replacing the temporary gate with a conductive material; and a step of removing or insulating the second active layer formed by selective epitaxial growth in a region other than the region that becomes a field effect transistor after the third step or the fourth step. A method of manufacturing a field effect transistor.