JPH046076Y2 - - Google Patents

Description

[Detailed description of the invention] This invention relates to an automatic piano performance device that automatically plays the piano based on performance data recorded in a storage means. An object of the present invention is to provide an automatic piano performance device that can faithfully reproduce music.

In order to achieve this purpose, this invention uses a plurality of solenoids arranged in correspondence with the keys of the piano, and solenoids corresponding to key position data indicating the key to be pressed, based on keystroke strength data indicating the strength of the keystroke. In an automatic piano performance device having a solenoid drive means that drives at a corresponding speed, the position of the key in the arrangement direction of the key specified by the key position data, the weight of the key, the center of swing of the key, and the solenoid for the key are determined. The keystroke strength is determined based on at least one variation of the required driving force of the key that varies depending on the distance from the acting force transmission point, and the characteristics of the solenoid corresponding to the key specified by the key position data. It is equipped with a correction means for correcting an increase or decrease in data.

An embodiment of this invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the structure of an automatic piano performance device according to this invention. First, an outline of the configuration of this automatic piano performance device will be explained.

First, each key on the keyboard 20 is equipped with two key switches and key drive solenoids 47 and 4.
7... is provided. In this case, the two key switches provided for each key operate at different timings in response to key operations (details will be described later), and the plunger of the key drive solenoid 47 is a solenoid. 4
When it protrudes from 7, it drives the key. Further, a damper pedal, a sostenuto pedal, etc. (together shown as a pedal device 21) provided on the piano each include a pedal switch and a solenoid 4 for driving the pedal.
7 is provided. Key press/release is detected based on the output of each key switch, and key operation speed, that is, key press strength is determined based on the operation interval of the two key switches provided on one key. Detected. This is due to the following reason. First, the stronger the key is played, the faster the key is pressed, so the interval between one turning on and the other becomes shorter. Conversely, if the key is played weakly, the speed at which the key is pressed becomes faster. Because it will be late,
The operation interval between one turning on and the other turning on becomes longer. Therefore, by measuring the movement interval, it is possible to know the strength of keystrokes. Furthermore, depression/release of each pedal is detected based on the output of the pedal switch. Then, performance data is created based on these detection results and written on the disk of the floppy disk device 22. When reproducing performance data (when performing automatic piano performance), the performance data recorded in the floppy disk device 22 is sequentially read out, and after predetermined data conversion is performed, the solenoid drive circuit 23
supply to As a result, the solenoids 47 provided on each key and each pedal are driven based on the performance data, and automatic performance of the piano is performed.

The automatic piano performance device described above will be described in detail below.

In FIG. 1, the key switch group 24 corresponds to the keyboard 2.
This block shows a set of key switches provided for each key of 0. Here, a configuration example of two key switches provided corresponding to one key will be explained with reference to FIG. 2. In this figure, reference numeral 24a represents a key, and a first key switch _K1 and a second key switch _K2 are arranged in parallel below the front end of the key 24a, corresponding to each key 24a. In this case, the first key switch
K ₁ and the second key switch K ₂ each have a movable contact SK ₁ whose tip portion is bent upward in a substantially inverted J-shape and constitutes parts A and B to be pressed by the key 24a.
SK ₃ and fixed contacts SK ₂ and SK ₄ that are close to the lower surface of the movable contacts SK ₁ and SK ₃ , and the pressed part of the movable contact SK ₁ of the first key switch K ₁ is the second
It is set higher than the pressed portion (b) of the movable contact _SK3 of the key switch _K2 and is close to the lower surface of the key 24a. Therefore, when the operation part of the key 24a is pressed down, the pressed part I first elastically deforms downward and comes into contact with the fixed contact _SK2 , the first key switch _K1 is turned on, and then the pressed part I is turned on. is elastically deformed downward, thereby turning on the second key switch _K2 .

The pedal switch group 25 is made up of pedal switches provided for each pedal of the pedal device 21, and the output of each pedal switch is supplied to a pedal switch interface 26.

The key information generating circuit 27 scans each key switch K ₁ and K ₂ of the key switch group 24 to generate
The on/off status of each key switch _K1 , _K2 is detected, and the key code KC is set according to the detection result.
(7 bits), keystroke strength data SD (8 bits; 1st
keystroke strength data) and keystroke confirmation code KD
This circuit outputs key information consisting of (1 bit). That is, this key information generation circuit 27 is
Three shift registers 28 (16 stages, 7 bits), 2 driven by clock pulse φ ₀
It consists of 9 (16 stages, 8 bits) and 30 (16 stages, 1 bit). When any key (hereinafter referred to as key A) is pressed anew, the key code KC of key A is activated when the first key switch _K1 of key A is turned on.
is written to an empty stage (assuming this empty stage is the 10th stage) of the shift register 28, and the second key switch _K2 is turned on from the moment the first key switch K1 of key A is turned on _. The time until the state is reached is measured, and the measurement result is stored in the shift register 29 as keystroke strength data SD.
write to the 10th stage of key A, and then write to the 2nd stage of key A
When the key switch _K2 is turned on, a key press confirmation code KD (“1” signal) is written to the 10th stage of the shift register 30. Further, when the key A is released, the data of the 10th stage of each shift register 28 to 30 is erased (set to "0") at the time when the first key switch _K1 is turned off.

Here, as is clear from the fact that each of the shift registers 28 to 30 described above has a 16-stage configuration, this key information generation circuit 27 allocates key information of a maximum of 16 keys to each stage of the shift registers 28 to 30. be able to. The key information assigned to each stage of the shift registers 28 to 30 is output to the FI-FO memory 34 in a time-division manner in accordance with the clock pulse φ ₀ described above. In addition, in this embodiment, keystroke strength data
To obtain SD, the following steps are taken. That is, in the above-described example of key A, for example, when the first key switch _K1 is turned on, "1" is added to the 10th stage of the shift register 29 at regular intervals thereafter. (In addition, shift register 29
The content of the 10th stage is "0" before the first key switch of key A is turned on. ) Then, when the second key switch _K2 of key A is closed, the above-mentioned addition of "1" stops, and from then on, this addition result is stored in the 10th stage of the shift register 29 as long as key A is on. Keystroke strength data from
Output as SD. As described above, in this embodiment, the contents of the shift register 29 before the second key switch _K2 is closed indicate the progress in the middle of time measurement, and do not indicate the correct keystroke strength data SD. After the second key switch is turned on, in other words, after the keystroke confirmation code KD becomes "1", the correct keystroke strength data
SD is output from the shift register 29. The above is the configuration of the key information generation circuit 27.

Next, the central processing unit (hereinafter referred to as CPU) 3
5 controls each part of the apparatus based on a program, and is connected to each part of the apparatus via a bus line 36.

A ROM (read-on memory) 37 is a memory in which a program used by the CPU 35, an intensity data conversion table, and an intensity data correction table, which will be described later, are respectively stored. The RAM (random access memory) 38 is a 16K word memory having areas 38a to 38d as shown in FIG. 3, and each area 38a to 38d has a storage capacity of 4K words. And areas 38a to 3
The area 8c is used as a buffer memory when writing data to or reading data from the disk of the floppy disk device 22, and the area 38d is used as a working area.

The FI-FO memory 34 is a 16.times.16 bit first-in/first-out memory, and its writing/reading is controlled by a memory controller 39. That is, when a write command is supplied from the CPU 35 to the memory controller 39,
The memory controller 39 puts the FI-FO memory 34 into a writing state. As a result, all the data in the shift registers 28 to 30 of the key information generation circuit 27 are transferred to the FI-FO memory ₃ based on the clock pulse φ0.
Written to 4. Furthermore, when a read command is supplied from the CPU 35 to the memory controller 39, the memory controller 39
4 is in the read state. As a result, all data in the FI-FO memory 34 is transferred to the RAM via the CPU 35.
The data is written to the new data area NDE (FIG. 3) in the area 38d of No. 38. The reason for inserting this FI-FO memory 34 is that the CPU 35 and key information generation circuit 27 are different (not synchronized).
This is because it is driven by clock pulses.

The pedal switch interface 26 turns on/off each pedal switch in the pedal switch group 25.
This circuit detects the off state and outputs pedal data PD corresponding to the detected on/off state.

The control signal generation circuit 41 receives a 2MHz clock pulse _φ1 supplied from the basic clock generation circuit 42.
The control signal obtained by counting based on the repetition data BD supplied from the CPU 35
SS is output to the CPU 35 via the bus line 36. The period of this control signal SS is normally 4 msec, but may be changed to 3.5 msec, 3 msec, or 200 usc depending on the case.

The operation unit 43 specifies switches such as a start switch, a stop switch, a write designation switch that designates writing to the disk of the floppy disk device 22, and a read designation switch that designates reading from the disk, as well as song numbers. The output of each switch and operation button is encoded and output to the bus line 36.

The solenoid drive circuit 23 receives solenoid drive data supplied from the CPU 35 via the bus line 36 and output interface 45.
Based on SKD, the period is constant and the same data
A solenoid drive signal having a pulse width corresponding to the SKD is created, and this solenoid drive signal is sent to the solenoids 47, 47... corresponding to the key code KC or pedal data PD supplied from the CPU 35 via the amplifiers 46, 46... Supply to...

Next, the operation of the automatic piano performance device with the above configuration will be explained.

[1] When data related to a performer's performance is recorded on the disk of the floppy disk device 22.

In this case, the player turns on the disk write designation switch provided on the operation section 43, presses the start switch, and then performs the normal piano performance using the keyboard 20 and pedal device 21. When the song has finished playing, press the stop switch. If the user wants to continue playing the second piece of music, the user presses the start switch again to begin playing the second piece of music, and when the performance is finished, the user presses the stop switch.

When the start switch is pressed by the performer, the CPU 35 first outputs repetition data BD specifying a 4 msec cycle to the control signal generation circuit 41. As a result, from now on, the control signal SS with a 4 msec period
is output from the control signal generation circuit 41, and the CPU 3
5. The CPU 35 performs the following processes every time the control signal SS is supplied.

First, a write command is output to the memory controller 39 to transfer all data in the shift registers 28 to 30 of the key information generation circuit 27 to the FI-FO memory 34.

Next, the data transferred to the FI-FO memory 34 is written into the new data area NDE set within the area 38d of the RAM 38.

Next, the pedal switch interface 26
The pedal data PD output from the RAM
38 new data area NDE.

Next, "1" is added to the data in the timer area TE set in the area 38d of the RAM 38. The meaning of this will be explained later.

Next, the new data area NDE of RAM38
By comparing the data in the old data area ODE set in the area 38d of the RAM 38, changes in the key depression state of the keyboard 20 and the operation state of the pedal device 21 (hereinafter, these changes are referred to as (referred to as an event). Note that the contents of the shift registers 28 to 30 and the pedal data PD when the control signal SS was output last time (4 msec ago) are stored in the old data area ODE.

Here, the above-mentioned event detection will be further explained. First, regarding the pedal device 21,
A change in pedal data PD is detected as an event. Next, when a new key is pressed (key-on), it is not detected as an event just because the first key switch _K1 is turned on. 2nd key switch K ₂
An event is detected when the keystroke confirmation code KD becomes an "1" signal. Strictly speaking, the event detection time is the time when the control signal SS is output for the first time after the keystroke confirmation code becomes a "1" signal. Also, when the key is released (key off), the first
Key code when key switch K ₁ is turned off
KC, keystroke confirmation code KD, etc. return to "0",
Therefore, an event is detected at this point (strictly speaking, the first time the control signal SS is output after this point).

If no event is detected in the above processing, the contents of the new data area NDE of the RAM 38 are moved to the old data area ODE, and the series of processing ends. After that, CPU3
5 waits for generation of the next control signal SS.

If an event is detected in the above process, a data group shown in FIG. 4 (hereinafter referred to as event frame EF) is created and written to area 38a of RAM 38. In addition, the event frame
EF will be explained in detail later.

Next, if an event is detected, clear the timer area TE.

Next, the contents of the new data area NDE are transferred to the old data area ODE, and the series of operations ends.

Thereafter, the CPU 35 waits for the next control signal SS to be generated.

The above means that every time the control signal SS is generated, the CPU 3
This is the process performed by No. 5.

Here, the data in the timer area TE and the event frame EF described above will be explained.

First, the data in the timer area TE is cleared every time an event occurs, as is clear from the process described above, and the data in the timer area TE is cleared to "1" every time the control signal SS occurs, as is clear from the process described above. is added. That is, the data in the timer area TE at the time of event occurrence indicates the time from the time when the previous event occurred to the time when the current event occurred (time with the basic unit being the period of 4 msec of the control signal SS).

Next, the event frame EF includes the first word count data WD1 and the timer data as shown in Figure 4.
TD, event data ED, second word count data
It consists of 4 data of WD2. Below, these data will be explained in order.

() First word count data WD1 This data indicates the total number of words of the timer data TD and the event data ED.

() Timer data TD This is data stored in the timer area TE of the RAM 38 at the time of performing the above processing, and is data indicating the time from the time when the previous event occurred to the time when the current event occurred. In addition,
This timer data TD has a 2-word configuration.

() Event data ED This data is related to the key or pedal where the event occurred. That is, when a new key is pressed and the second key switch _K2 is turned on, the key code KC (7 bits) of the pressed key, the key-on code (“1”), and Two words of data consisting of keystroke strength data SD (8 bits) for the same key become event data ED (key position data is constituted by the above-mentioned key code KC). In addition, the above key code
KC and keystroke strength data SD are stored in the new data area NDE. Further, when the key is released, as shown in FIG. 5B, one word of data consisting of the key code KC of the released key and the key-off code ("0") becomes event data ED. Furthermore, when any pedal of the pedal device 21 is turned on, one word of data consisting of the pedal data PD and the pedal on code (“1”) becomes the event data ED, as shown in FIG. 5C. When the pedal in the on state is turned off, one word of data consisting of the pedal data PD and the pedal off code ("0") becomes the event data ED, as shown in FIG. 5D.
Also, for example, if two keys are turned on at the same time, the two sets of data shown in Figure 5 A become the event data ED; for example, if a key and a pedal are turned on at the same time, the two sets of data shown in Figure 5 A and The data shown in C becomes event data ED. Note that the above-mentioned timer data TD and event data ED are collectively referred to as performance data.

() Second word count data WD2 This data is exactly the same as the first word count data WD1. That is, in this embodiment, the same number of words data is added to the beginning and end of the event frame EF.

Next, the event frame EF mentioned above is in area 3.
The process of writing into 8a will be specifically explained using an example.

Now, for example, at time t ₀ shown in FIG. 6, the start switch is turned on, and at time t ₄ , the start switch is turned on.
Key switch K ₂ of F ₃ (third octave/F note) is turned on, and at time t ₈ key switch K 2 of key G ₃ (third octave/F note) is turned on.
Assume that the key switch _K2 of the octave/G tone key is turned on, the key switch _K1 of the key _G3 is turned off at time _t11 , and the key switch _K1 of the key _F3 is turned off at time _t14 . When the start switch is turned on at time t ₀ , the control signal is then turned on at times t ₁ , t ₂ , and t ₃ every 4 msec.
Although SS occurs, there is no change in the key press state at these times _t1 to _t3 , and no event is detected.
Next, when an event check is performed at time _t5 , an event is detected because the pressed state of key _F3 has changed compared to the state at time _t3 , and as a result, the event frame shown in FIG. EF-1
is written into area 38a of RAM 38. In this case, the timer data TD-1 is "4" (this data indicates time _T1 in FIG. 6), and the event data ED-1 is the key code KC of key _F3 , the key-on code "1", and The keystroke strength data is SD, and the first and second word number data WD1-1 and WD2-1 are both "4".

Next, an event check is performed at times t ₆ and t ₇ , but no event is detected at these times t ₆ and t ₇ , and therefore no event frame EF is created. Next, at time _t9 , when an event check is performed, an event is detected because the pressed state of key _G3 has changed, and as a result, the event frame shown in FIG.
EF-2 is written into the area 38a of the RAM 38 consecutively to the event frame EF-1 described above.
Similarly, at time _t12 , an event is detected because the pressed state of key _G3 changes,
As a result, the event frame EF-3 shown in FIG. 7 is created in the area 38a of the RAM 38, and
At time _t15 , since the pressed state of key _F3 has changed, an event is detected, and as a result, event frame EF-4 shown in FIG. 7 is created.

In this way, in this embodiment, each time an event is detected, the performance data (timer data
TD and event data ED) are recorded in the area 38a of the RAM 38 in the form of an event frame EF. And area 38a is full
When the state is reached, the event frame EF will be
Written in the area 38b of the RAM 38, and
The CPU 35 sequentially DMAs the data in the area 38a.
The floppy disk device 22 is operated via the disk controller 49 under the control of the controller 50.
The data is supplied to the disk device 22 and written to the disk disk in the disk device 22. Next, when the area 38b becomes Full, the event frame EF is placed in the area 38c.
is created, and the data in area 38b is written to the disk. In this way, the areas 38a, 38
b and 38c are used for cycling.

The above is the process of recording the performance data related to the piano player's performance on the disk in the floppy disk device 22.

Incidentally, in this embodiment, the performance data of a plurality of songs can be written on each disk, but the following procedure is taken for convenience when reading out the performance data of each recorded song.

That is, when the start switch is first pressed, all bits become "0" as shown in Figure 8A.
The inter-song code MC-1 is in the area 38a of the RAM 38.
After that, each time an event occurs, the event frame EF is written to the first address of the song code MC.
-1 is sequentially written into the area 38a.
Note that the symbol MC-1 in FIG. 7 also indicates the above-mentioned inter-song chord. After the performance of the first song is finished, when the performer presses the start switch again and starts playing the second song, the inter-music code MC-2 is again changed to area 38a (or area 38a).
8b, 38c), and thereafter, an event frame EF is written following this inter-music code MC-2. The same applies to the case where the third song, the fourth song, etc. are played continuously. Then, each time the performance of each song is completed, when the performer presses the stop switch, the data in the areas 38a to 38c are written to the disk of the floppy disk device 22, and then the address of the inter-song code ( The addresses of the disc are sequentially written to different tracks of the disc starting from the first track, thereby creating the index table IDT shown in FIG. 8B.

In this way, in this embodiment, by writing the inter-song code at the beginning of the first track and between the songs, and by creating the index table IDT in the disc, the performance data can be read out easily. We are trying to make it more convenient for you.

[2] When performing an automatic performance Next, the performance data written on the disk of the floppy disk device 22 is read out, and FIG. 1 shows a case where the automatic performance of the piano is performed based on the read performance data. The operation of the shown device will be explained.

In this case, the operator first turns on the disk read designation switch on the operation section 43, and then
Specify the song number using the operation button, and then press the start switch.

When the start switch is pressed, the CPU 35
First, the address (address of the inter-music code) corresponding to the music number designated by the operation button is read from the index table of the disk of the floppy disk device 22 (see FIG. 8B). Then,
The read address is supplied to the floppy disk device 22 via the disk controller 49, and 12K words of data recorded after the same address on the disk are stored in areas 38a to 38 of the RAM 38.
Sequentially transfer to c. Next, the CPU 35 outputs the repetition data BD specifying 4 msec to the control signal generation circuit 41 as in the case of data recording described above. As a result, from the control signal generation circuit 41
A control signal SS with a period of 4 msec is output, and the CPU 35
supplied to Thereafter, the CPU 35 processes data in the areas 38a to 38c based on the control signal SS. This processing process will be explained below.
For convenience of explanation, it is assumed that the inter-music code MC-1 and event frames EF-1, EF-2, . . . shown in FIG. 7 are written in order from the first address of the area 38a.

Now, after outputting the repetition data BD specifying a 4 msec period to the control signal generation circuit 41, the CPU 35 outputs the first word data WD1-1 shown in FIG.
(“4”) and timing data TD-1 (“4”)
is read from the area 38a of the RAM 38, and
d temporary storage area SPE and timer area TE
Write each to. Thereafter, each time the control signal SS is output, "1" is subtracted from the contents of the timer area TE, and the result of this subtraction is written into the timer area TE again. And the content of timer area TE is "0"
, that is, the time T ₁ shown in Figure 6
When the time period has elapsed, perform the following processing.

(a) First word count data WD1-1 (“4”) stored in the temporary storage area SPE of RAM38
Subtract the number of words of timer data TD "2" from.

(b) This subtraction result, i.e., event data
Area 38 based on the word count “2” of ED-1
Event data ED-1 (FIG. 7) is read from a, and the read event data ED-1 is written in the event data area EDE of area 38d.

(c) First word count data WD1-2 (“4”) and timer data shown in FIG. 7 from area 38a
TD-2 ("3") is read and written into the temporary recording area SPE and timer area TE of area 38d, respectively.

When event data ED-1 is written to event data area EDE in area 38d (processing in (b) above), this event data ED-1 (key code KC of key _F3 , key press strength data SD, key on code " Solenoid drive data SKD based on 1”)
is created and supplied to the solenoid drive circuit 23. The solenoid drive circuit 23 creates a solenoid drive signal based on the solenoid drive data SKD, and supplies it to the solenoid 47 provided at the key F ₃ via the amplifier 46 . This will cause the key F ₃
is driven with a strength corresponding to the keystroke strength data SD. Note that the process of driving this solenoid 47 will be described in detail later.

Thereafter, each time the control signal SS is output, "1" is subtracted from the contents of the timer area TE ("3" in this case), as in the case described above. Then, when the contents of the timer area TE become "0" (when time _T2 shown in FIG. 6 has elapsed),
The same process as described above is performed again. That is, (a) the word number "2" of the timer data TD is subtracted from the first word number data WD1-2 ("4").

(b) Based on this subtraction result (“2”), the area 38a
Event data ED-2 is read from the event data area EDE and written to the event data area EDE.

(c) First word count data WD1- from area 38a
3 (“3”) and timer data TD-3
(“2”) is read and written to the temporary storage area SPE and timer area TE, respectively.

Then, when event data ED-2 (key code KC of key G ₃ , key press strength data SD, key-on code "1") is written in the event data area EDE, key G Solenoid 47 provided at ₃ is driven.

Next, when time T ₃ (Figure 6) corresponding to timer data TD-3 ("2") has elapsed, the same processing as in (a) to (c) above is performed again, and as a result, the timer area Timer data TD-4 (“2”) is in TE,
Event data ED in event data area EDE
-3 and the first word number data WD1-4 are respectively written into the temporary storage area SPE. Then, event data ED-3 is placed in the event data area EDE.
When (key code KC and key off code "0" of key _G3 ) is written, the solenoid 47 provided in key _G3 is turned off.

The same process is repeated thereafter, and the piano is automatically played. And area 38 of RAM 38
When the automatic performance of all data in area 38a is completed, automatic performance is subsequently performed based on the data in area 38b. Further, while automatic performance is being performed using the data in the area 38b, the next data is read from the disk of the floppy disk device 22,
It is written in area 38a. When the automatic performance of the data in the area 38b is completed, the data in the area 38b is
Automatic performance is performed in the order of c→38a→38b→..., and when data writing in area 38a is completed, data is subsequently written in each area in the order of area 38b→38c→38a... .

In the above example, only the driving of the keys of the keyboard 20 has been described, but the driving of the pedals of the pedal device 21 is performed in the same manner.

Also, if you want to change the tempo of automatic performance,
Instead of the repetition data BD specifying a cycle of 4 msec, repeat data BD specifying a cycle of 3 msec, 3.5 msec, etc. may be supplied to the control signal generation circuit 41, for example.

Next, a process in which the solenoid 47 provided in the key is driven based on the event data ED written in the event data area EDE will be described. In addition, in the following explanation, the key
Take for example the case where F ₃ is driven.

First, the keystroke strength data SD (keystroke strength data of key F ₃ ) in the event data area EDE is stored in the ROM.
The data is converted based on the keystroke strength data conversion table in 37. The reason for this conversion is as follows.

While the keystroke strength data SD has a value proportional to the player's keystroke strength, the operating speed of the plunger of the solenoid 47 does not correspond linearly to the pulse width of the solenoid drive signal. That is, even if a solenoid drive signal having a pulse width proportional to the keystroke strength data SD is applied to the solenoid 47, it is not possible to obtain a plunger operating speed proportional to the keystroke strength data SD. Therefore, it is necessary to convert the keystroke strength data SD so that the operating speed of the plunger corresponding to the keystroke strength data SD can be obtained. The keystroke strength data conversion table is a table for this conversion, and the data corresponding to each value of the keystroke strength data SD (hereinafter referred to as
This data is referred to as keystroke strength data SD') and is stored in advance. Note that the ROM 37 includes the operation unit 43 as this keystroke strength data conversion table.
Separate tables are prepared for each of, for example, five levels of volume set by a volume setting switch provided in the.

Next, the keystroke strength data SD' obtained by the above conversion is further corrected by the keystroke strength data correction table in the ROM 37. The reason for this correction is as follows.

() The force required to drive the key differs depending on whether the key is a black key or a white key, so it is necessary to correct the keystroke strength data depending on whether the key is a black key or a white key. This is because the black and white keys have different shapes, and therefore their total weight and the position of the balance pin, which is the center of rotation, relative to the overall length of the key.

() Due to the installation space, the solenoids 47, 47... cannot be arranged in a straight line along the direction in which the keys are arranged, and may be arranged, for example, in a staggered manner, staggered alternately. In this way, if they are arranged alternately, the adjacent solenoids 4
Since the solenoids 7 can be installed so as to partially overlap, the installation space for the solenoids 47, 47, . . . can be reduced. However, if the solenoids 47 are arranged alternately, the distance between the point of action of the solenoid 47 on the key and the center of swing of the key (the position of the balance pin) will alternate in the direction in which the keys are arranged. As a result, it becomes necessary to correct the keystroke strength depending on the position of the solenoid.

() The key driving force is different for bass keys and treble keys (generally, the key touch is heavier on the bass side because the hammer and damper are larger), so the solenoid drive signal with the same pulse width is applied to the bass key. When the voltage is applied to the solenoid 47 and the solenoid 47 of the high key, the operating speed of the plunger of the solenoid 47 of the low key becomes slower than that of the high key. Therefore, it is necessary to correct this difference in operation depending on the position of the key.

Normally, all of the above-mentioned reasons () to () are involved, so comprehensive correction is required, but it goes without saying that correction is not necessary for those that have no or can be ignored. For example, when the solenoids 47 are arranged in a straight line, correction due to the above-mentioned reason () is not necessary.

The keystroke strength data correction table is for performing the above-mentioned correction, and contains correction data (for example, "+1", "0", "-1", etc.) corresponding to each key code KC.
etc.) are stored in advance. Then, the above-mentioned keystroke strength data SD' is corrected by correction data corresponding to the key code KC of the key _F3 . This corrected data is hereinafter referred to as keystroke strength data HSD.

Note that both the keystroke strength data conversion table and the keystroke strength data correction table described above are created based on experimental results.

Next, based on the above-mentioned keystroke strength data HSD, solenoid drive data SKD whose value changes as time passes as shown by the broken line DL in FIG. 9 is created. In addition, in Fig. 9, at time _t1 , event data ED-1 is in the event data area EDE.
The time written in , time t ₂ is event data ED
-4 (see Figure 7) is the event data area
This is the time written to EDE. Also, this ninth
In the waveform shown in the figure, times T ₁ to T ₄ and solenoid drive data SKD ₁ to SKD ₃ are the following times and data, respectively.

_T1 : On-delay time, that is, when a weak note and a strong note are played at the same time, the weak note will be played later than the weak note. In order to eliminate this inconvenience, the time T ₁ is made small when the sound is weak, and the time T ₁ is made large when the sound is strong.

SKD ₁ : Data for static friction escape.

In other words, this solenoid drive data
SKD ₁ is converted to solenoid drive signal,
When supplied to the solenoid 47, the plunger of the solenoid 47 is released from static friction.

T ₂ : Time for static friction escape.

SKD ₂ : Data corresponding to keystroke strength data HSD.

In other words, this solenoid drive data
Depending on the value of SKD ₂ , solenoid 47
The operating speed of the plunger is determined.

T ₃ : Time required for the plunger of the solenoid 47 to be fully extended; in other words, time required for the key to be fully turned on.

SKD ₃ : Solenoid holding data.

That is, one driven solenoid 47
Data for holding the plunger in the protruding state.

T ₄ : Off-day delay time.

Since on-day delay time T ₁ is provided,
If the solenoid drive signal is immediately turned off at time _t2 , the sound generation time during playback will be shorter than the sound generation time during performance. Time to eliminate this inconvenience.

And each solenoid drive data mentioned above
SKD ₁ to SKD ₃ sequentially at the timing shown in Figure 9,
It is output to the solenoid drive circuit 23 together with the key code KC of key _F3 . Solenoid drive circuit 23
is supplied with each solenoid drive data SKD ₁ ~
A solenoid drive signal with a constant period having a pulse width corresponding to SKD ₃ is created and supplied via an amplifier 46 to a solenoid 47 provided at key F ₃ .
As a result, solenoid 4 provided on key F ₃
7 is driven with a strength corresponding to the keystroke strength data SD.

As explained in detail above, according to this invention, the keystroke strength conversion table (the first keystroke strength data conversion means) and the keystroke strength correction table (the second keystroke strength data conversion means)
A keystroke strength data conversion means) is provided to convert the keystroke strength data SD (first keystroke strength data) using these tables, and convert the keystroke strength data HSD (second keystroke strength data) obtained as a result. Since the solenoid is driven based on the performance, the strength of the keystrokes during the performance can be reproduced with great fidelity.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the structure of an embodiment of this invention, Fig. 2 is a side sectional view showing the structure of key switches K ₁ and K ₂ provided on each key of the piano,
The figure shows the internal structure of the RAM 38 in Fig. 1, Fig. 4 shows the structure of the event frame EF, Fig. 5 A to D show the format of the event data ED, and Fig. 6 shows the key FIG. 7 is a timing diagram showing an example of an operation. FIG. 7 is a diagram showing data written to the RAM 38 shown in FIG. 1 in response to the key operation shown in FIG. 6. FIG. FIG. 9, which is a diagram for explaining the index table IDT, is a waveform diagram showing changes in the solenoid drive data SKD for driving the solenoid 47 in FIG. 1. 20...keyboard, 35...central processing unit (CPU), 37...read only memory (ROM),
47...Solenoid.

Claims (1)

[Claim for Utility Model Registration] A plurality of solenoids arranged in correspondence with the keys of a piano and solenoids corresponding to key position data indicating the key to be pressed are driven at a speed corresponding to key press intensity data indicating the key press force. In an automatic piano performance device having a solenoid driving means, the position of the key in the arrangement direction of the key specified by the key position data, the weight of the key, the swing center of the key, and the acting force transmission point of the solenoid with respect to the key. The keystroke strength data is increased or decreased based on a variation in at least one of the required driving forces of the key that varies depending on the distance between the keys and the characteristics of the solenoid corresponding to the key specified by the key position data. An automatic piano performance device characterized by comprising a correction means.